1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/i2c/i2c_mux_pca954x.h" 18 #include "hw/i2c/smbus_eeprom.h" 19 #include "hw/misc/pca9552.h" 20 #include "hw/sensor/tmp105.h" 21 #include "hw/misc/led.h" 22 #include "hw/qdev-properties.h" 23 #include "sysemu/block-backend.h" 24 #include "sysemu/reset.h" 25 #include "hw/loader.h" 26 #include "qemu/error-report.h" 27 #include "qemu/units.h" 28 #include "hw/qdev-clock.h" 29 30 static struct arm_boot_info aspeed_board_binfo = { 31 .board_id = -1, /* device-tree-only board */ 32 }; 33 34 struct AspeedMachineState { 35 /* Private */ 36 MachineState parent_obj; 37 /* Public */ 38 39 AspeedSoCState soc; 40 MemoryRegion ram_container; 41 MemoryRegion max_ram; 42 bool mmio_exec; 43 char *fmc_model; 44 char *spi_model; 45 }; 46 47 /* Palmetto hardware value: 0x120CE416 */ 48 #define PALMETTO_BMC_HW_STRAP1 ( \ 49 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 50 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 51 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 52 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 53 SCU_HW_STRAP_VGA_CLASS_CODE | \ 54 SCU_HW_STRAP_LPC_RESET_PIN | \ 55 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 56 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 57 SCU_HW_STRAP_SPI_WIDTH | \ 58 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 59 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 60 61 /* TODO: Find the actual hardware value */ 62 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 63 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 64 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 65 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 66 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 67 SCU_HW_STRAP_VGA_CLASS_CODE | \ 68 SCU_HW_STRAP_LPC_RESET_PIN | \ 69 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 70 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 71 SCU_HW_STRAP_SPI_WIDTH | \ 72 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 73 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 74 75 /* AST2500 evb hardware value: 0xF100C2E6 */ 76 #define AST2500_EVB_HW_STRAP1 (( \ 77 AST2500_HW_STRAP1_DEFAULTS | \ 78 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 79 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 80 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 81 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 82 SCU_HW_STRAP_MAC1_RGMII | \ 83 SCU_HW_STRAP_MAC0_RGMII) & \ 84 ~SCU_HW_STRAP_2ND_BOOT_WDT) 85 86 /* Romulus hardware value: 0xF10AD206 */ 87 #define ROMULUS_BMC_HW_STRAP1 ( \ 88 AST2500_HW_STRAP1_DEFAULTS | \ 89 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 90 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 91 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 92 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 93 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 94 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 95 96 /* Sonorapass hardware value: 0xF100D216 */ 97 #define SONORAPASS_BMC_HW_STRAP1 ( \ 98 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 99 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 100 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 101 SCU_AST2500_HW_STRAP_RESERVED28 | \ 102 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 103 SCU_HW_STRAP_VGA_CLASS_CODE | \ 104 SCU_HW_STRAP_LPC_RESET_PIN | \ 105 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 106 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 107 SCU_HW_STRAP_VGA_BIOS_ROM | \ 108 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 109 SCU_AST2500_HW_STRAP_RESERVED1) 110 111 #define G220A_BMC_HW_STRAP1 ( \ 112 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 113 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 114 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 115 SCU_AST2500_HW_STRAP_RESERVED28 | \ 116 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 117 SCU_HW_STRAP_2ND_BOOT_WDT | \ 118 SCU_HW_STRAP_VGA_CLASS_CODE | \ 119 SCU_HW_STRAP_LPC_RESET_PIN | \ 120 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 121 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 122 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 123 SCU_AST2500_HW_STRAP_RESERVED1) 124 125 /* FP5280G2 hardware value: 0XF100D286 */ 126 #define FP5280G2_BMC_HW_STRAP1 ( \ 127 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 128 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 129 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 130 SCU_AST2500_HW_STRAP_RESERVED28 | \ 131 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 132 SCU_HW_STRAP_VGA_CLASS_CODE | \ 133 SCU_HW_STRAP_LPC_RESET_PIN | \ 134 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 135 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 136 SCU_HW_STRAP_MAC1_RGMII | \ 137 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 138 SCU_AST2500_HW_STRAP_RESERVED1) 139 140 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 141 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 142 143 /* Quanta-Q71l hardware value */ 144 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 145 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 146 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 147 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 148 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 149 SCU_HW_STRAP_VGA_CLASS_CODE | \ 150 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 151 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 152 SCU_HW_STRAP_SPI_WIDTH | \ 153 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 154 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 155 156 /* AST2600 evb hardware value */ 157 #define AST2600_EVB_HW_STRAP1 0x000000C0 158 #define AST2600_EVB_HW_STRAP2 0x00000003 159 160 /* Tacoma hardware value */ 161 #define TACOMA_BMC_HW_STRAP1 0x00000000 162 #define TACOMA_BMC_HW_STRAP2 0x00000040 163 164 /* Rainier hardware value: (QEMU prototype) */ 165 #define RAINIER_BMC_HW_STRAP1 0x00422016 166 #define RAINIER_BMC_HW_STRAP2 0x80000848 167 168 /* Fuji hardware value */ 169 #define FUJI_BMC_HW_STRAP1 0x00000000 170 #define FUJI_BMC_HW_STRAP2 0x00000000 171 172 /* Bletchley hardware value */ 173 /* TODO: Leave same as EVB for now. */ 174 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 175 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 176 177 /* 178 * The max ram region is for firmwares that scan the address space 179 * with load/store to guess how much RAM the SoC has. 180 */ 181 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 182 { 183 return 0; 184 } 185 186 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 187 unsigned size) 188 { 189 /* Discard writes */ 190 } 191 192 static const MemoryRegionOps max_ram_ops = { 193 .read = max_ram_read, 194 .write = max_ram_write, 195 .endianness = DEVICE_NATIVE_ENDIAN, 196 }; 197 198 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 199 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 200 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 201 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 202 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 203 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 204 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 205 206 static void aspeed_write_smpboot(ARMCPU *cpu, 207 const struct arm_boot_info *info) 208 { 209 static const uint32_t poll_mailbox_ready[] = { 210 /* 211 * r2 = per-cpu go sign value 212 * r1 = AST_SMP_MBOX_FIELD_ENTRY 213 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 214 */ 215 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 216 0xe21000ff, /* ands r0, r0, #255 */ 217 0xe59f201c, /* ldr r2, [pc, #28] */ 218 0xe1822000, /* orr r2, r2, r0 */ 219 220 0xe59f1018, /* ldr r1, [pc, #24] */ 221 0xe59f0018, /* ldr r0, [pc, #24] */ 222 223 0xe320f002, /* wfe */ 224 0xe5904000, /* ldr r4, [r0] */ 225 0xe1520004, /* cmp r2, r4 */ 226 0x1afffffb, /* bne <wfe> */ 227 0xe591f000, /* ldr pc, [r1] */ 228 AST_SMP_MBOX_GOSIGN, 229 AST_SMP_MBOX_FIELD_ENTRY, 230 AST_SMP_MBOX_FIELD_GOSIGN, 231 }; 232 233 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 234 sizeof(poll_mailbox_ready), 235 info->smp_loader_start); 236 } 237 238 static void aspeed_reset_secondary(ARMCPU *cpu, 239 const struct arm_boot_info *info) 240 { 241 AddressSpace *as = arm_boot_address_space(cpu, info); 242 CPUState *cs = CPU(cpu); 243 244 /* info->smp_bootreg_addr */ 245 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 246 MEMTXATTRS_UNSPECIFIED, NULL); 247 cpu_set_pc(cs, info->smp_loader_start); 248 } 249 250 #define FIRMWARE_ADDR 0x0 251 252 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 253 Error **errp) 254 { 255 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 256 g_autofree void *storage = NULL; 257 int64_t size; 258 259 /* The block backend size should have already been 'validated' by 260 * the creation of the m25p80 object. 261 */ 262 size = blk_getlength(blk); 263 if (size <= 0) { 264 error_setg(errp, "failed to get flash size"); 265 return; 266 } 267 268 if (rom_size > size) { 269 rom_size = size; 270 } 271 272 storage = g_malloc0(rom_size); 273 if (blk_pread(blk, 0, storage, rom_size) < 0) { 274 error_setg(errp, "failed to read the initial flash content"); 275 return; 276 } 277 278 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 279 } 280 281 static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 282 unsigned int count, int unit0) 283 { 284 int i; 285 286 if (!flashtype) { 287 return; 288 } 289 290 for (i = 0; i < count; ++i) { 291 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 292 qemu_irq cs_line; 293 DeviceState *dev; 294 295 dev = qdev_new(flashtype); 296 if (dinfo) { 297 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 298 } 299 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 300 301 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); 302 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 303 } 304 } 305 306 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 307 { 308 DeviceState *card; 309 310 if (!dinfo) { 311 return; 312 } 313 card = qdev_new(TYPE_SD_CARD); 314 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 315 &error_fatal); 316 qdev_realize_and_unref(card, 317 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 318 &error_fatal); 319 } 320 321 static void aspeed_machine_init(MachineState *machine) 322 { 323 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 324 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 325 AspeedSoCClass *sc; 326 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 327 ram_addr_t max_ram_size; 328 int i; 329 NICInfo *nd = &nd_table[0]; 330 331 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 332 4 * GiB); 333 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 334 335 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 336 337 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 338 339 /* 340 * This will error out if isize is not supported by memory controller. 341 */ 342 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size, 343 &error_fatal); 344 345 for (i = 0; i < sc->macs_num; i++) { 346 if ((amc->macs_mask & (1 << i)) && nd->used) { 347 qemu_check_nic_model(nd, TYPE_FTGMAC100); 348 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 349 nd++; 350 } 351 } 352 353 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 354 &error_abort); 355 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 356 &error_abort); 357 object_property_set_link(OBJECT(&bmc->soc), "dram", 358 OBJECT(machine->ram), &error_abort); 359 if (machine->kernel_filename) { 360 /* 361 * When booting with a -kernel command line there is no u-boot 362 * that runs to unlock the SCU. In this case set the default to 363 * be unlocked as the kernel expects 364 */ 365 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 366 ASPEED_SCU_PROT_KEY, &error_abort); 367 } 368 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", 369 amc->uart_default); 370 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 371 372 memory_region_add_subregion(get_system_memory(), 373 sc->memmap[ASPEED_DEV_SDRAM], 374 &bmc->ram_container); 375 376 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 377 &error_abort); 378 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 379 "max_ram", max_ram_size - machine->ram_size); 380 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram); 381 382 aspeed_board_init_flashes(&bmc->soc.fmc, 383 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 384 amc->num_cs, 0); 385 aspeed_board_init_flashes(&bmc->soc.spi[0], 386 bmc->spi_model ? bmc->spi_model : amc->spi_model, 387 1, amc->num_cs); 388 389 /* Install first FMC flash content as a boot rom. */ 390 if (drive0) { 391 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 392 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 393 uint64_t size = memory_region_size(&fl->mmio); 394 395 /* 396 * create a ROM region using the default mapping window size of 397 * the flash module. The window size is 64MB for the AST2400 398 * SoC and 128MB for the AST2500 SoC, which is twice as big as 399 * needed by the flash modules of the Aspeed machines. 400 */ 401 if (ASPEED_MACHINE(machine)->mmio_exec) { 402 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", 403 &fl->mmio, 0, size); 404 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 405 boot_rom); 406 } else { 407 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", 408 size, &error_abort); 409 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 410 boot_rom); 411 write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort); 412 } 413 } 414 415 if (machine->kernel_filename && sc->num_cpus > 1) { 416 /* With no u-boot we must set up a boot stub for the secondary CPU */ 417 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 418 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 419 0x80, &error_abort); 420 memory_region_add_subregion(get_system_memory(), 421 AST_SMP_MAILBOX_BASE, smpboot); 422 423 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 424 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 425 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 426 } 427 428 aspeed_board_binfo.ram_size = machine->ram_size; 429 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 430 431 if (amc->i2c_init) { 432 amc->i2c_init(bmc); 433 } 434 435 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 436 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], 437 drive_get(IF_SD, 0, i)); 438 } 439 440 if (bmc->soc.emmc.num_slots) { 441 sdhci_attach_drive(&bmc->soc.emmc.slots[0], 442 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots)); 443 } 444 445 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 446 } 447 448 static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize) 449 { 450 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 451 DeviceState *dev = DEVICE(i2c_dev); 452 453 qdev_prop_set_uint32(dev, "rom-size", rsize); 454 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); 455 } 456 457 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 458 { 459 AspeedSoCState *soc = &bmc->soc; 460 DeviceState *dev; 461 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 462 463 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 464 * enough to provide basic RTC features. Alarms will be missing */ 465 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 466 467 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 468 eeprom_buf); 469 470 /* add a TMP423 temperature sensor */ 471 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 472 "tmp423", 0x4c)); 473 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 474 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 475 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 476 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 477 } 478 479 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 480 { 481 AspeedSoCState *soc = &bmc->soc; 482 483 /* 484 * The quanta-q71l platform expects tmp75s which are compatible with 485 * tmp105s. 486 */ 487 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 488 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 489 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 490 491 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 492 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 493 /* TODO: Add Memory Riser i2c mux and eeproms. */ 494 495 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 496 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 497 498 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 499 500 /* i2c-7 */ 501 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 502 /* - i2c@0: pmbus@59 */ 503 /* - i2c@1: pmbus@58 */ 504 /* - i2c@2: pmbus@58 */ 505 /* - i2c@3: pmbus@59 */ 506 507 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 508 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 509 } 510 511 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 512 { 513 AspeedSoCState *soc = &bmc->soc; 514 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 515 516 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 517 eeprom_buf); 518 519 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 520 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 521 TYPE_TMP105, 0x4d); 522 523 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 524 * plugged on the I2C bus header */ 525 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 526 } 527 528 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 529 { 530 AspeedSoCState *soc = &bmc->soc; 531 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 532 533 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 534 eeprom_buf); 535 536 /* LM75 is compatible with TMP105 driver */ 537 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 538 TYPE_TMP105, 0x4d); 539 } 540 541 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 542 { 543 AspeedSoCState *soc = &bmc->soc; 544 545 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 546 * good enough */ 547 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 548 } 549 550 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 551 { 552 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 553 TYPE_PCA9552, addr); 554 } 555 556 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 557 { 558 AspeedSoCState *soc = &bmc->soc; 559 560 /* bus 2 : */ 561 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 562 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 563 /* bus 2 : pca9546 @ 0x73 */ 564 565 /* bus 3 : pca9548 @ 0x70 */ 566 567 /* bus 4 : */ 568 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 569 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 570 eeprom4_54); 571 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 572 create_pca9552(soc, 4, 0x76); 573 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 574 create_pca9552(soc, 4, 0x77); 575 576 /* bus 6 : */ 577 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 578 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 579 /* bus 6 : pca9546 @ 0x73 */ 580 581 /* bus 8 : */ 582 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 583 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 584 eeprom8_56); 585 create_pca9552(soc, 8, 0x60); 586 create_pca9552(soc, 8, 0x61); 587 /* bus 8 : adc128d818 @ 0x1d */ 588 /* bus 8 : adc128d818 @ 0x1f */ 589 590 /* 591 * bus 13 : pca9548 @ 0x71 592 * - channel 3: 593 * - tmm421 @ 0x4c 594 * - tmp421 @ 0x4e 595 * - tmp421 @ 0x4f 596 */ 597 598 } 599 600 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 601 { 602 static const struct { 603 unsigned gpio_id; 604 LEDColor color; 605 const char *description; 606 bool gpio_polarity; 607 } pca1_leds[] = { 608 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 609 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 610 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 611 }; 612 AspeedSoCState *soc = &bmc->soc; 613 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 614 DeviceState *dev; 615 LEDState *led; 616 617 /* Bus 3: TODO bmp280@77 */ 618 /* Bus 3: TODO max31785@52 */ 619 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 620 qdev_prop_set_string(dev, "description", "pca1"); 621 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 622 aspeed_i2c_get_bus(&soc->i2c, 3), 623 &error_fatal); 624 625 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 626 led = led_create_simple(OBJECT(bmc), 627 pca1_leds[i].gpio_polarity, 628 pca1_leds[i].color, 629 pca1_leds[i].description); 630 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 631 qdev_get_gpio_in(DEVICE(led), 0)); 632 } 633 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 634 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 635 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 636 637 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 638 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 639 0x4a); 640 641 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 642 * good enough */ 643 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 644 645 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 646 eeprom_buf); 647 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 648 qdev_prop_set_string(dev, "description", "pca0"); 649 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 650 aspeed_i2c_get_bus(&soc->i2c, 11), 651 &error_fatal); 652 /* Bus 11: TODO ucd90160@64 */ 653 } 654 655 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 656 { 657 AspeedSoCState *soc = &bmc->soc; 658 DeviceState *dev; 659 660 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 661 "emc1413", 0x4c)); 662 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 663 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 664 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 665 666 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 667 "emc1413", 0x4c)); 668 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 669 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 670 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 671 672 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 673 "emc1413", 0x4c)); 674 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 675 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 676 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 677 678 static uint8_t eeprom_buf[2 * 1024] = { 679 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 680 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 681 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 682 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 683 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 684 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 685 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 686 }; 687 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 688 eeprom_buf); 689 } 690 691 static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize) 692 { 693 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 694 DeviceState *dev = DEVICE(i2c_dev); 695 696 qdev_prop_set_uint32(dev, "rom-size", rsize); 697 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); 698 } 699 700 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 701 { 702 AspeedSoCState *soc = &bmc->soc; 703 I2CSlave *i2c_mux; 704 705 /* The at24c256 */ 706 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 707 708 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 709 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 710 0x48); 711 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 712 0x49); 713 714 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 715 "pca9546", 0x70); 716 /* It expects a TMP112 but a TMP105 is compatible */ 717 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 718 0x4a); 719 720 /* It expects a ds3232 but a ds1338 is good enough */ 721 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 722 723 /* It expects a pca9555 but a pca9552 is compatible */ 724 create_pca9552(soc, 8, 0x30); 725 } 726 727 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 728 { 729 AspeedSoCState *soc = &bmc->soc; 730 I2CSlave *i2c_mux; 731 732 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 733 734 create_pca9552(soc, 3, 0x61); 735 736 /* The rainier expects a TMP275 but a TMP105 is compatible */ 737 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 738 0x48); 739 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 740 0x49); 741 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 742 0x4a); 743 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 744 "pca9546", 0x70); 745 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 746 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 747 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 748 create_pca9552(soc, 4, 0x60); 749 750 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 751 0x48); 752 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 753 0x49); 754 create_pca9552(soc, 5, 0x60); 755 create_pca9552(soc, 5, 0x61); 756 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 757 "pca9546", 0x70); 758 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 759 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 760 761 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 762 0x48); 763 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 764 0x4a); 765 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 766 0x4b); 767 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 768 "pca9546", 0x70); 769 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 770 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 771 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 772 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 773 774 create_pca9552(soc, 7, 0x30); 775 create_pca9552(soc, 7, 0x31); 776 create_pca9552(soc, 7, 0x32); 777 create_pca9552(soc, 7, 0x33); 778 /* Bus 7: TODO max31785@52 */ 779 create_pca9552(soc, 7, 0x60); 780 create_pca9552(soc, 7, 0x61); 781 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 782 /* Bus 7: TODO si7021-a20@20 */ 783 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 784 0x48); 785 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 786 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 787 788 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 789 0x48); 790 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 791 0x4a); 792 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB); 793 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB); 794 create_pca9552(soc, 8, 0x60); 795 create_pca9552(soc, 8, 0x61); 796 /* Bus 8: ucd90320@11 */ 797 /* Bus 8: ucd90320@b */ 798 /* Bus 8: ucd90320@c */ 799 800 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 801 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 802 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 803 804 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 805 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 806 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 807 808 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 809 0x48); 810 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 811 0x49); 812 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 813 "pca9546", 0x70); 814 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 815 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 816 create_pca9552(soc, 11, 0x60); 817 818 819 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 820 create_pca9552(soc, 13, 0x60); 821 822 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 823 create_pca9552(soc, 14, 0x60); 824 825 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 826 create_pca9552(soc, 15, 0x60); 827 } 828 829 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 830 I2CBus **channels) 831 { 832 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 833 for (int i = 0; i < 8; i++) { 834 channels[i] = pca954x_i2c_get_bus(mux, i); 835 } 836 } 837 838 #define TYPE_LM75 TYPE_TMP105 839 #define TYPE_TMP75 TYPE_TMP105 840 #define TYPE_TMP422 "tmp422" 841 842 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 843 { 844 AspeedSoCState *soc = &bmc->soc; 845 I2CBus *i2c[144] = {}; 846 847 for (int i = 0; i < 16; i++) { 848 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 849 } 850 I2CBus *i2c180 = i2c[2]; 851 I2CBus *i2c480 = i2c[8]; 852 I2CBus *i2c600 = i2c[11]; 853 854 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 855 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 856 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 857 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 858 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 859 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 860 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 861 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 862 for (int i = 0; i < 8; i++) { 863 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 864 } 865 866 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 867 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 868 869 aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB); 870 aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB); 871 aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB); 872 873 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 874 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 875 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 876 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 877 878 aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB); 879 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 880 881 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 882 aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB); 883 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 884 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 885 886 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 887 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 888 889 aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB); 890 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 891 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 892 aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB); 893 aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB); 894 aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB); 895 aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB); 896 897 aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB); 898 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 899 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 900 aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB); 901 aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB); 902 aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB); 903 aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB); 904 aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB); 905 906 for (int i = 0; i < 8; i++) { 907 aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 908 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 909 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 910 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 911 } 912 } 913 914 #define TYPE_TMP421 "tmp421" 915 916 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 917 { 918 AspeedSoCState *soc = &bmc->soc; 919 I2CBus *i2c[13] = {}; 920 for (int i = 0; i < 13; i++) { 921 if ((i == 8) || (i == 11)) { 922 continue; 923 } 924 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 925 } 926 927 /* Bus 0 - 5 all have the same config. */ 928 for (int i = 0; i < 6; i++) { 929 /* Missing model: ti,ina230 @ 0x45 */ 930 /* Missing model: mps,mp5023 @ 0x40 */ 931 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 932 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 933 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 934 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 935 /* Missing model: fsc,fusb302 @ 0x22 */ 936 } 937 938 /* Bus 6 */ 939 at24c_eeprom_init(i2c[6], 0x56, 65536); 940 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 941 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 942 943 944 /* Bus 7 */ 945 at24c_eeprom_init(i2c[7], 0x54, 65536); 946 947 /* Bus 9 */ 948 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 949 950 /* Bus 10 */ 951 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 952 /* Missing model: ti,hdc1080 @ 0x40 */ 953 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 954 955 /* Bus 12 */ 956 /* Missing model: adi,adm1278 @ 0x11 */ 957 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 958 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 959 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 960 } 961 962 static void fby35_i2c_init(AspeedMachineState *bmc) 963 { 964 AspeedSoCState *soc = &bmc->soc; 965 I2CBus *i2c[16]; 966 967 for (int i = 0; i < 16; i++) { 968 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 969 } 970 971 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 972 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 973 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 974 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 975 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 976 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 977 978 aspeed_eeprom_init(i2c[4], 0x51, 128 * KiB); 979 aspeed_eeprom_init(i2c[6], 0x51, 128 * KiB); 980 aspeed_eeprom_init(i2c[8], 0x50, 32 * KiB); 981 aspeed_eeprom_init(i2c[11], 0x51, 128 * KiB); 982 aspeed_eeprom_init(i2c[11], 0x54, 128 * KiB); 983 984 /* 985 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 986 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 987 * each. 988 */ 989 } 990 991 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 992 { 993 return ASPEED_MACHINE(obj)->mmio_exec; 994 } 995 996 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 997 { 998 ASPEED_MACHINE(obj)->mmio_exec = value; 999 } 1000 1001 static void aspeed_machine_instance_init(Object *obj) 1002 { 1003 ASPEED_MACHINE(obj)->mmio_exec = false; 1004 } 1005 1006 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1007 { 1008 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1009 return g_strdup(bmc->fmc_model); 1010 } 1011 1012 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1013 { 1014 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1015 1016 g_free(bmc->fmc_model); 1017 bmc->fmc_model = g_strdup(value); 1018 } 1019 1020 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1021 { 1022 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1023 return g_strdup(bmc->spi_model); 1024 } 1025 1026 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1027 { 1028 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1029 1030 g_free(bmc->spi_model); 1031 bmc->spi_model = g_strdup(value); 1032 } 1033 1034 static void aspeed_machine_class_props_init(ObjectClass *oc) 1035 { 1036 object_class_property_add_bool(oc, "execute-in-place", 1037 aspeed_get_mmio_exec, 1038 aspeed_set_mmio_exec); 1039 object_class_property_set_description(oc, "execute-in-place", 1040 "boot directly from CE0 flash device"); 1041 1042 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1043 aspeed_set_fmc_model); 1044 object_class_property_set_description(oc, "fmc-model", 1045 "Change the FMC Flash model"); 1046 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1047 aspeed_set_spi_model); 1048 object_class_property_set_description(oc, "spi-model", 1049 "Change the SPI Flash model"); 1050 } 1051 1052 static int aspeed_soc_num_cpus(const char *soc_name) 1053 { 1054 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 1055 return sc->num_cpus; 1056 } 1057 1058 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1059 { 1060 MachineClass *mc = MACHINE_CLASS(oc); 1061 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1062 1063 mc->init = aspeed_machine_init; 1064 mc->no_floppy = 1; 1065 mc->no_cdrom = 1; 1066 mc->no_parallel = 1; 1067 mc->default_ram_id = "ram"; 1068 amc->macs_mask = ASPEED_MAC0_ON; 1069 amc->uart_default = ASPEED_DEV_UART5; 1070 1071 aspeed_machine_class_props_init(oc); 1072 } 1073 1074 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1075 { 1076 MachineClass *mc = MACHINE_CLASS(oc); 1077 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1078 1079 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1080 amc->soc_name = "ast2400-a1"; 1081 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1082 amc->fmc_model = "n25q256a"; 1083 amc->spi_model = "mx25l25635e"; 1084 amc->num_cs = 1; 1085 amc->i2c_init = palmetto_bmc_i2c_init; 1086 mc->default_ram_size = 256 * MiB; 1087 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1088 aspeed_soc_num_cpus(amc->soc_name); 1089 }; 1090 1091 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1092 { 1093 MachineClass *mc = MACHINE_CLASS(oc); 1094 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1095 1096 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1097 amc->soc_name = "ast2400-a1"; 1098 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1099 amc->fmc_model = "n25q256a"; 1100 amc->spi_model = "mx25l25635e"; 1101 amc->num_cs = 1; 1102 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1103 mc->default_ram_size = 128 * MiB; 1104 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1105 aspeed_soc_num_cpus(amc->soc_name); 1106 } 1107 1108 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1109 void *data) 1110 { 1111 MachineClass *mc = MACHINE_CLASS(oc); 1112 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1113 1114 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1115 amc->soc_name = "ast2400-a1"; 1116 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1117 amc->fmc_model = "mx25l25635e"; 1118 amc->spi_model = "mx25l25635e"; 1119 amc->num_cs = 1; 1120 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1121 amc->i2c_init = palmetto_bmc_i2c_init; 1122 mc->default_ram_size = 256 * MiB; 1123 } 1124 1125 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1126 { 1127 MachineClass *mc = MACHINE_CLASS(oc); 1128 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1129 1130 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1131 amc->soc_name = "ast2500-a1"; 1132 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1133 amc->fmc_model = "mx25l25635e"; 1134 amc->spi_model = "mx25l25635e"; 1135 amc->num_cs = 1; 1136 amc->i2c_init = ast2500_evb_i2c_init; 1137 mc->default_ram_size = 512 * MiB; 1138 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1139 aspeed_soc_num_cpus(amc->soc_name); 1140 }; 1141 1142 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1143 { 1144 MachineClass *mc = MACHINE_CLASS(oc); 1145 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1146 1147 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1148 amc->soc_name = "ast2500-a1"; 1149 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1150 amc->fmc_model = "n25q256a"; 1151 amc->spi_model = "mx66l1g45g"; 1152 amc->num_cs = 2; 1153 amc->i2c_init = romulus_bmc_i2c_init; 1154 mc->default_ram_size = 512 * MiB; 1155 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1156 aspeed_soc_num_cpus(amc->soc_name); 1157 }; 1158 1159 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1160 { 1161 MachineClass *mc = MACHINE_CLASS(oc); 1162 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1163 1164 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1165 amc->soc_name = "ast2500-a1"; 1166 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1167 amc->fmc_model = "mx66l1g45g"; 1168 amc->spi_model = "mx66l1g45g"; 1169 amc->num_cs = 2; 1170 amc->i2c_init = sonorapass_bmc_i2c_init; 1171 mc->default_ram_size = 512 * MiB; 1172 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1173 aspeed_soc_num_cpus(amc->soc_name); 1174 }; 1175 1176 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1177 { 1178 MachineClass *mc = MACHINE_CLASS(oc); 1179 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1180 1181 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1182 amc->soc_name = "ast2500-a1"; 1183 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1184 amc->fmc_model = "mx25l25635e"; 1185 amc->spi_model = "mx66l1g45g"; 1186 amc->num_cs = 2; 1187 amc->i2c_init = witherspoon_bmc_i2c_init; 1188 mc->default_ram_size = 512 * MiB; 1189 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1190 aspeed_soc_num_cpus(amc->soc_name); 1191 }; 1192 1193 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1194 { 1195 MachineClass *mc = MACHINE_CLASS(oc); 1196 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1197 1198 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1199 amc->soc_name = "ast2600-a3"; 1200 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1201 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1202 amc->fmc_model = "mx66u51235f"; 1203 amc->spi_model = "mx66u51235f"; 1204 amc->num_cs = 1; 1205 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1206 ASPEED_MAC3_ON; 1207 amc->i2c_init = ast2600_evb_i2c_init; 1208 mc->default_ram_size = 1 * GiB; 1209 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1210 aspeed_soc_num_cpus(amc->soc_name); 1211 }; 1212 1213 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1214 { 1215 MachineClass *mc = MACHINE_CLASS(oc); 1216 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1217 1218 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1219 amc->soc_name = "ast2600-a3"; 1220 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1221 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1222 amc->fmc_model = "mx66l1g45g"; 1223 amc->spi_model = "mx66l1g45g"; 1224 amc->num_cs = 2; 1225 amc->macs_mask = ASPEED_MAC2_ON; 1226 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1227 mc->default_ram_size = 1 * GiB; 1228 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1229 aspeed_soc_num_cpus(amc->soc_name); 1230 }; 1231 1232 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1233 { 1234 MachineClass *mc = MACHINE_CLASS(oc); 1235 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1236 1237 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1238 amc->soc_name = "ast2500-a1"; 1239 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1240 amc->fmc_model = "n25q512a"; 1241 amc->spi_model = "mx25l25635e"; 1242 amc->num_cs = 2; 1243 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1244 amc->i2c_init = g220a_bmc_i2c_init; 1245 mc->default_ram_size = 1024 * MiB; 1246 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1247 aspeed_soc_num_cpus(amc->soc_name); 1248 }; 1249 1250 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1251 { 1252 MachineClass *mc = MACHINE_CLASS(oc); 1253 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1254 1255 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1256 amc->soc_name = "ast2500-a1"; 1257 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1258 amc->fmc_model = "n25q512a"; 1259 amc->spi_model = "mx25l25635e"; 1260 amc->num_cs = 2; 1261 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1262 amc->i2c_init = fp5280g2_bmc_i2c_init; 1263 mc->default_ram_size = 512 * MiB; 1264 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1265 aspeed_soc_num_cpus(amc->soc_name); 1266 }; 1267 1268 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1269 { 1270 MachineClass *mc = MACHINE_CLASS(oc); 1271 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1272 1273 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1274 amc->soc_name = "ast2600-a3"; 1275 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1276 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1277 amc->fmc_model = "mx66l1g45g"; 1278 amc->spi_model = "mx66l1g45g"; 1279 amc->num_cs = 2; 1280 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1281 amc->i2c_init = rainier_bmc_i2c_init; 1282 mc->default_ram_size = 1 * GiB; 1283 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1284 aspeed_soc_num_cpus(amc->soc_name); 1285 }; 1286 1287 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 1288 #if HOST_LONG_BITS == 32 1289 #define FUJI_BMC_RAM_SIZE (1 * GiB) 1290 #else 1291 #define FUJI_BMC_RAM_SIZE (2 * GiB) 1292 #endif 1293 1294 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1295 { 1296 MachineClass *mc = MACHINE_CLASS(oc); 1297 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1298 1299 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1300 amc->soc_name = "ast2600-a3"; 1301 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1302 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1303 amc->fmc_model = "mx66l1g45g"; 1304 amc->spi_model = "mx66l1g45g"; 1305 amc->num_cs = 2; 1306 amc->macs_mask = ASPEED_MAC3_ON; 1307 amc->i2c_init = fuji_bmc_i2c_init; 1308 amc->uart_default = ASPEED_DEV_UART1; 1309 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1310 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1311 aspeed_soc_num_cpus(amc->soc_name); 1312 }; 1313 1314 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1315 { 1316 MachineClass *mc = MACHINE_CLASS(oc); 1317 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1318 1319 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1320 amc->soc_name = "ast2600-a3"; 1321 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1322 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1323 amc->fmc_model = "w25q01jvq"; 1324 amc->spi_model = NULL; 1325 amc->num_cs = 2; 1326 amc->macs_mask = ASPEED_MAC2_ON; 1327 amc->i2c_init = bletchley_bmc_i2c_init; 1328 mc->default_ram_size = 512 * MiB; 1329 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1330 aspeed_soc_num_cpus(amc->soc_name); 1331 } 1332 1333 static void fby35_reset(MachineState *state) 1334 { 1335 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1336 AspeedGPIOState *gpio = &bmc->soc.gpio; 1337 1338 qemu_devices_reset(); 1339 1340 /* Board ID */ 1341 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1342 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1343 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1344 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1345 } 1346 1347 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) 1348 { 1349 MachineClass *mc = MACHINE_CLASS(oc); 1350 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1351 1352 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1353 mc->reset = fby35_reset; 1354 amc->fmc_model = "mx66l1g45g"; 1355 amc->num_cs = 2; 1356 amc->macs_mask = ASPEED_MAC3_ON; 1357 amc->i2c_init = fby35_i2c_init; 1358 /* FIXME: Replace this macro with something more general */ 1359 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1360 } 1361 1362 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1363 /* Main SYSCLK frequency in Hz (200MHz) */ 1364 #define SYSCLK_FRQ 200000000ULL 1365 1366 static void aspeed_minibmc_machine_init(MachineState *machine) 1367 { 1368 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1369 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1370 Clock *sysclk; 1371 1372 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1373 clock_set_hz(sysclk, SYSCLK_FRQ); 1374 1375 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 1376 qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk); 1377 1378 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", 1379 amc->uart_default); 1380 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 1381 1382 aspeed_board_init_flashes(&bmc->soc.fmc, 1383 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1384 amc->num_cs, 1385 0); 1386 1387 aspeed_board_init_flashes(&bmc->soc.spi[0], 1388 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1389 amc->num_cs, amc->num_cs); 1390 1391 aspeed_board_init_flashes(&bmc->soc.spi[1], 1392 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1393 amc->num_cs, (amc->num_cs * 2)); 1394 1395 if (amc->i2c_init) { 1396 amc->i2c_init(bmc); 1397 } 1398 1399 armv7m_load_kernel(ARM_CPU(first_cpu), 1400 machine->kernel_filename, 1401 AST1030_INTERNAL_FLASH_SIZE); 1402 } 1403 1404 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1405 void *data) 1406 { 1407 MachineClass *mc = MACHINE_CLASS(oc); 1408 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1409 1410 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1411 amc->soc_name = "ast1030-a1"; 1412 amc->hw_strap1 = 0; 1413 amc->hw_strap2 = 0; 1414 mc->init = aspeed_minibmc_machine_init; 1415 mc->default_ram_size = 0; 1416 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1; 1417 amc->fmc_model = "sst25vf032b"; 1418 amc->spi_model = "sst25vf032b"; 1419 amc->num_cs = 2; 1420 amc->macs_mask = 0; 1421 } 1422 1423 static const TypeInfo aspeed_machine_types[] = { 1424 { 1425 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1426 .parent = TYPE_ASPEED_MACHINE, 1427 .class_init = aspeed_machine_palmetto_class_init, 1428 }, { 1429 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1430 .parent = TYPE_ASPEED_MACHINE, 1431 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1432 }, { 1433 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1434 .parent = TYPE_ASPEED_MACHINE, 1435 .class_init = aspeed_machine_ast2500_evb_class_init, 1436 }, { 1437 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1438 .parent = TYPE_ASPEED_MACHINE, 1439 .class_init = aspeed_machine_romulus_class_init, 1440 }, { 1441 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1442 .parent = TYPE_ASPEED_MACHINE, 1443 .class_init = aspeed_machine_sonorapass_class_init, 1444 }, { 1445 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1446 .parent = TYPE_ASPEED_MACHINE, 1447 .class_init = aspeed_machine_witherspoon_class_init, 1448 }, { 1449 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1450 .parent = TYPE_ASPEED_MACHINE, 1451 .class_init = aspeed_machine_ast2600_evb_class_init, 1452 }, { 1453 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1454 .parent = TYPE_ASPEED_MACHINE, 1455 .class_init = aspeed_machine_tacoma_class_init, 1456 }, { 1457 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1458 .parent = TYPE_ASPEED_MACHINE, 1459 .class_init = aspeed_machine_g220a_class_init, 1460 }, { 1461 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1462 .parent = TYPE_ASPEED_MACHINE, 1463 .class_init = aspeed_machine_fp5280g2_class_init, 1464 }, { 1465 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1466 .parent = TYPE_ASPEED_MACHINE, 1467 .class_init = aspeed_machine_quanta_q71l_class_init, 1468 }, { 1469 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1470 .parent = TYPE_ASPEED_MACHINE, 1471 .class_init = aspeed_machine_rainier_class_init, 1472 }, { 1473 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1474 .parent = TYPE_ASPEED_MACHINE, 1475 .class_init = aspeed_machine_fuji_class_init, 1476 }, { 1477 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1478 .parent = TYPE_ASPEED_MACHINE, 1479 .class_init = aspeed_machine_bletchley_class_init, 1480 }, { 1481 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1482 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1483 .class_init = aspeed_machine_fby35_class_init, 1484 }, { 1485 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1486 .parent = TYPE_ASPEED_MACHINE, 1487 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1488 }, { 1489 .name = TYPE_ASPEED_MACHINE, 1490 .parent = TYPE_MACHINE, 1491 .instance_size = sizeof(AspeedMachineState), 1492 .instance_init = aspeed_machine_instance_init, 1493 .class_size = sizeof(AspeedMachineClass), 1494 .class_init = aspeed_machine_class_init, 1495 .abstract = true, 1496 } 1497 }; 1498 1499 DEFINE_TYPES(aspeed_machine_types) 1500