1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/i2c/i2c_mux_pca954x.h" 19 #include "hw/i2c/smbus_eeprom.h" 20 #include "hw/misc/pca9552.h" 21 #include "hw/nvram/eeprom_at24c.h" 22 #include "hw/sensor/tmp105.h" 23 #include "hw/misc/led.h" 24 #include "hw/qdev-properties.h" 25 #include "sysemu/block-backend.h" 26 #include "sysemu/reset.h" 27 #include "hw/loader.h" 28 #include "qemu/error-report.h" 29 #include "qemu/units.h" 30 #include "hw/qdev-clock.h" 31 #include "sysemu/sysemu.h" 32 33 static struct arm_boot_info aspeed_board_binfo = { 34 .board_id = -1, /* device-tree-only board */ 35 }; 36 37 struct AspeedMachineState { 38 /* Private */ 39 MachineState parent_obj; 40 /* Public */ 41 42 AspeedSoCState soc; 43 MemoryRegion boot_rom; 44 bool mmio_exec; 45 uint32_t uart_chosen; 46 char *fmc_model; 47 char *spi_model; 48 }; 49 50 /* Palmetto hardware value: 0x120CE416 */ 51 #define PALMETTO_BMC_HW_STRAP1 ( \ 52 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 53 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 54 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 55 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 56 SCU_HW_STRAP_VGA_CLASS_CODE | \ 57 SCU_HW_STRAP_LPC_RESET_PIN | \ 58 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 59 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 60 SCU_HW_STRAP_SPI_WIDTH | \ 61 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 62 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 63 64 /* TODO: Find the actual hardware value */ 65 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 66 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 67 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 68 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 69 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 70 SCU_HW_STRAP_VGA_CLASS_CODE | \ 71 SCU_HW_STRAP_LPC_RESET_PIN | \ 72 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 73 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 74 SCU_HW_STRAP_SPI_WIDTH | \ 75 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 76 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 77 78 /* TODO: Find the actual hardware value */ 79 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 80 AST2500_HW_STRAP1_DEFAULTS | \ 81 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 82 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 83 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 84 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 85 SCU_HW_STRAP_SPI_WIDTH | \ 86 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 87 88 /* AST2500 evb hardware value: 0xF100C2E6 */ 89 #define AST2500_EVB_HW_STRAP1 (( \ 90 AST2500_HW_STRAP1_DEFAULTS | \ 91 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 92 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 93 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 94 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 95 SCU_HW_STRAP_MAC1_RGMII | \ 96 SCU_HW_STRAP_MAC0_RGMII) & \ 97 ~SCU_HW_STRAP_2ND_BOOT_WDT) 98 99 /* Romulus hardware value: 0xF10AD206 */ 100 #define ROMULUS_BMC_HW_STRAP1 ( \ 101 AST2500_HW_STRAP1_DEFAULTS | \ 102 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 103 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 104 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 105 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 106 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 107 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 108 109 /* Sonorapass hardware value: 0xF100D216 */ 110 #define SONORAPASS_BMC_HW_STRAP1 ( \ 111 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 112 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 113 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 114 SCU_AST2500_HW_STRAP_RESERVED28 | \ 115 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 116 SCU_HW_STRAP_VGA_CLASS_CODE | \ 117 SCU_HW_STRAP_LPC_RESET_PIN | \ 118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 119 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 120 SCU_HW_STRAP_VGA_BIOS_ROM | \ 121 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 122 SCU_AST2500_HW_STRAP_RESERVED1) 123 124 #define G220A_BMC_HW_STRAP1 ( \ 125 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 126 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 127 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 128 SCU_AST2500_HW_STRAP_RESERVED28 | \ 129 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 130 SCU_HW_STRAP_2ND_BOOT_WDT | \ 131 SCU_HW_STRAP_VGA_CLASS_CODE | \ 132 SCU_HW_STRAP_LPC_RESET_PIN | \ 133 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 134 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 135 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 136 SCU_AST2500_HW_STRAP_RESERVED1) 137 138 /* FP5280G2 hardware value: 0XF100D286 */ 139 #define FP5280G2_BMC_HW_STRAP1 ( \ 140 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 141 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 142 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 143 SCU_AST2500_HW_STRAP_RESERVED28 | \ 144 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 145 SCU_HW_STRAP_VGA_CLASS_CODE | \ 146 SCU_HW_STRAP_LPC_RESET_PIN | \ 147 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 148 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 149 SCU_HW_STRAP_MAC1_RGMII | \ 150 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 151 SCU_AST2500_HW_STRAP_RESERVED1) 152 153 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 154 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 155 156 /* Quanta-Q71l hardware value */ 157 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 158 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 159 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 160 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 161 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 162 SCU_HW_STRAP_VGA_CLASS_CODE | \ 163 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 164 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 165 SCU_HW_STRAP_SPI_WIDTH | \ 166 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 167 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 168 169 /* AST2600 evb hardware value */ 170 #define AST2600_EVB_HW_STRAP1 0x000000C0 171 #define AST2600_EVB_HW_STRAP2 0x00000003 172 173 /* Tacoma hardware value */ 174 #define TACOMA_BMC_HW_STRAP1 0x00000000 175 #define TACOMA_BMC_HW_STRAP2 0x00000040 176 177 /* Rainier hardware value: (QEMU prototype) */ 178 #define RAINIER_BMC_HW_STRAP1 0x00422016 179 #define RAINIER_BMC_HW_STRAP2 0x80000848 180 181 /* Fuji hardware value */ 182 #define FUJI_BMC_HW_STRAP1 0x00000000 183 #define FUJI_BMC_HW_STRAP2 0x00000000 184 185 /* Bletchley hardware value */ 186 /* TODO: Leave same as EVB for now. */ 187 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 188 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 189 190 /* Qualcomm DC-SCM hardware value */ 191 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 192 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 193 194 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 195 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 196 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 197 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 198 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 199 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 200 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 201 202 static void aspeed_write_smpboot(ARMCPU *cpu, 203 const struct arm_boot_info *info) 204 { 205 AddressSpace *as = arm_boot_address_space(cpu, info); 206 static const ARMInsnFixup poll_mailbox_ready[] = { 207 /* 208 * r2 = per-cpu go sign value 209 * r1 = AST_SMP_MBOX_FIELD_ENTRY 210 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 211 */ 212 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 213 { 0xe21000ff }, /* ands r0, r0, #255 */ 214 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 215 { 0xe1822000 }, /* orr r2, r2, r0 */ 216 217 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 218 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 219 220 { 0xe320f002 }, /* wfe */ 221 { 0xe5904000 }, /* ldr r4, [r0] */ 222 { 0xe1520004 }, /* cmp r2, r4 */ 223 { 0x1afffffb }, /* bne <wfe> */ 224 { 0xe591f000 }, /* ldr pc, [r1] */ 225 { AST_SMP_MBOX_GOSIGN }, 226 { AST_SMP_MBOX_FIELD_ENTRY }, 227 { AST_SMP_MBOX_FIELD_GOSIGN }, 228 { 0, FIXUP_TERMINATOR } 229 }; 230 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 231 232 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 233 poll_mailbox_ready, fixupcontext); 234 } 235 236 static void aspeed_reset_secondary(ARMCPU *cpu, 237 const struct arm_boot_info *info) 238 { 239 AddressSpace *as = arm_boot_address_space(cpu, info); 240 CPUState *cs = CPU(cpu); 241 242 /* info->smp_bootreg_addr */ 243 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 244 MEMTXATTRS_UNSPECIFIED, NULL); 245 cpu_set_pc(cs, info->smp_loader_start); 246 } 247 248 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 249 Error **errp) 250 { 251 g_autofree void *storage = NULL; 252 int64_t size; 253 254 /* The block backend size should have already been 'validated' by 255 * the creation of the m25p80 object. 256 */ 257 size = blk_getlength(blk); 258 if (size <= 0) { 259 error_setg(errp, "failed to get flash size"); 260 return; 261 } 262 263 if (rom_size > size) { 264 rom_size = size; 265 } 266 267 storage = g_malloc0(rom_size); 268 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 269 error_setg(errp, "failed to read the initial flash content"); 270 return; 271 } 272 273 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 274 } 275 276 /* 277 * Create a ROM and copy the flash contents at the expected address 278 * (0x0). Boots faster than execute-in-place. 279 */ 280 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 281 uint64_t rom_size) 282 { 283 AspeedSoCState *soc = &bmc->soc; 284 285 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 286 &error_abort); 287 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 288 &bmc->boot_rom, 1); 289 write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort); 290 } 291 292 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 293 unsigned int count, int unit0) 294 { 295 int i; 296 297 if (!flashtype) { 298 return; 299 } 300 301 for (i = 0; i < count; ++i) { 302 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 303 qemu_irq cs_line; 304 DeviceState *dev; 305 306 dev = qdev_new(flashtype); 307 if (dinfo) { 308 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 309 } 310 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 311 312 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); 313 qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line); 314 } 315 } 316 317 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 318 { 319 DeviceState *card; 320 321 if (!dinfo) { 322 return; 323 } 324 card = qdev_new(TYPE_SD_CARD); 325 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 326 &error_fatal); 327 qdev_realize_and_unref(card, 328 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 329 &error_fatal); 330 } 331 332 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 333 { 334 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 335 AspeedSoCState *s = &bmc->soc; 336 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 337 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 338 339 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 340 for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) { 341 if (uart == uart_chosen) { 342 continue; 343 } 344 aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); 345 } 346 } 347 348 static void aspeed_machine_init(MachineState *machine) 349 { 350 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 351 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 352 AspeedSoCClass *sc; 353 int i; 354 NICInfo *nd = &nd_table[0]; 355 356 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 357 358 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 359 360 /* 361 * This will error out if the RAM size is not supported by the 362 * memory controller of the SoC. 363 */ 364 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size, 365 &error_fatal); 366 367 for (i = 0; i < sc->macs_num; i++) { 368 if ((amc->macs_mask & (1 << i)) && nd->used) { 369 qemu_check_nic_model(nd, TYPE_FTGMAC100); 370 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 371 nd++; 372 } 373 } 374 375 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 376 &error_abort); 377 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 378 &error_abort); 379 object_property_set_link(OBJECT(&bmc->soc), "memory", 380 OBJECT(get_system_memory()), &error_abort); 381 object_property_set_link(OBJECT(&bmc->soc), "dram", 382 OBJECT(machine->ram), &error_abort); 383 if (machine->kernel_filename) { 384 /* 385 * When booting with a -kernel command line there is no u-boot 386 * that runs to unlock the SCU. In this case set the default to 387 * be unlocked as the kernel expects 388 */ 389 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 390 ASPEED_SCU_PROT_KEY, &error_abort); 391 } 392 connect_serial_hds_to_uarts(bmc); 393 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 394 395 aspeed_board_init_flashes(&bmc->soc.fmc, 396 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 397 amc->num_cs, 0); 398 aspeed_board_init_flashes(&bmc->soc.spi[0], 399 bmc->spi_model ? bmc->spi_model : amc->spi_model, 400 1, amc->num_cs); 401 402 if (machine->kernel_filename && sc->num_cpus > 1) { 403 /* With no u-boot we must set up a boot stub for the secondary CPU */ 404 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 405 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 406 0x80, &error_abort); 407 memory_region_add_subregion(get_system_memory(), 408 AST_SMP_MAILBOX_BASE, smpboot); 409 410 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 411 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 412 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 413 } 414 415 aspeed_board_binfo.ram_size = machine->ram_size; 416 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 417 418 if (amc->i2c_init) { 419 amc->i2c_init(bmc); 420 } 421 422 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 423 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], 424 drive_get(IF_SD, 0, i)); 425 } 426 427 if (bmc->soc.emmc.num_slots) { 428 sdhci_attach_drive(&bmc->soc.emmc.slots[0], 429 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots)); 430 } 431 432 if (!bmc->mmio_exec) { 433 DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0); 434 435 if (mtd0) { 436 uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot); 437 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(mtd0), rom_size); 438 } 439 } 440 441 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 442 } 443 444 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 445 { 446 AspeedSoCState *soc = &bmc->soc; 447 DeviceState *dev; 448 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 449 450 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 451 * enough to provide basic RTC features. Alarms will be missing */ 452 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 453 454 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 455 eeprom_buf); 456 457 /* add a TMP423 temperature sensor */ 458 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 459 "tmp423", 0x4c)); 460 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 461 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 462 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 463 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 464 } 465 466 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 467 { 468 AspeedSoCState *soc = &bmc->soc; 469 470 /* 471 * The quanta-q71l platform expects tmp75s which are compatible with 472 * tmp105s. 473 */ 474 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 475 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 476 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 477 478 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 479 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 480 /* TODO: Add Memory Riser i2c mux and eeproms. */ 481 482 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 483 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 484 485 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 486 487 /* i2c-7 */ 488 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 489 /* - i2c@0: pmbus@59 */ 490 /* - i2c@1: pmbus@58 */ 491 /* - i2c@2: pmbus@58 */ 492 /* - i2c@3: pmbus@59 */ 493 494 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 495 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 496 } 497 498 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 499 { 500 AspeedSoCState *soc = &bmc->soc; 501 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 502 503 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 504 eeprom_buf); 505 506 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 507 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 508 TYPE_TMP105, 0x4d); 509 } 510 511 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 512 { 513 AspeedSoCState *soc = &bmc->soc; 514 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 515 516 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 517 eeprom_buf); 518 519 /* LM75 is compatible with TMP105 driver */ 520 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 521 TYPE_TMP105, 0x4d); 522 } 523 524 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 525 { 526 AspeedSoCState *soc = &bmc->soc; 527 528 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 529 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 530 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 531 /* TMP421 */ 532 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 533 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 534 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 535 536 } 537 538 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 539 { 540 AspeedSoCState *soc = &bmc->soc; 541 542 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 543 * good enough */ 544 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 545 } 546 547 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 548 { 549 AspeedSoCState *soc = &bmc->soc; 550 551 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 552 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 553 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 554 /* TMP421 */ 555 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 556 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 557 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 558 } 559 560 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 561 { 562 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 563 TYPE_PCA9552, addr); 564 } 565 566 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 567 { 568 AspeedSoCState *soc = &bmc->soc; 569 570 /* bus 2 : */ 571 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 572 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 573 /* bus 2 : pca9546 @ 0x73 */ 574 575 /* bus 3 : pca9548 @ 0x70 */ 576 577 /* bus 4 : */ 578 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 579 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 580 eeprom4_54); 581 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 582 create_pca9552(soc, 4, 0x76); 583 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 584 create_pca9552(soc, 4, 0x77); 585 586 /* bus 6 : */ 587 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 588 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 589 /* bus 6 : pca9546 @ 0x73 */ 590 591 /* bus 8 : */ 592 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 593 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 594 eeprom8_56); 595 create_pca9552(soc, 8, 0x60); 596 create_pca9552(soc, 8, 0x61); 597 /* bus 8 : adc128d818 @ 0x1d */ 598 /* bus 8 : adc128d818 @ 0x1f */ 599 600 /* 601 * bus 13 : pca9548 @ 0x71 602 * - channel 3: 603 * - tmm421 @ 0x4c 604 * - tmp421 @ 0x4e 605 * - tmp421 @ 0x4f 606 */ 607 608 } 609 610 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 611 { 612 static const struct { 613 unsigned gpio_id; 614 LEDColor color; 615 const char *description; 616 bool gpio_polarity; 617 } pca1_leds[] = { 618 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 619 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 620 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 621 }; 622 AspeedSoCState *soc = &bmc->soc; 623 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 624 DeviceState *dev; 625 LEDState *led; 626 627 /* Bus 3: TODO bmp280@77 */ 628 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 629 qdev_prop_set_string(dev, "description", "pca1"); 630 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 631 aspeed_i2c_get_bus(&soc->i2c, 3), 632 &error_fatal); 633 634 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 635 led = led_create_simple(OBJECT(bmc), 636 pca1_leds[i].gpio_polarity, 637 pca1_leds[i].color, 638 pca1_leds[i].description); 639 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 640 qdev_get_gpio_in(DEVICE(led), 0)); 641 } 642 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 643 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 644 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 645 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 646 647 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 648 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 649 0x4a); 650 651 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 652 * good enough */ 653 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 654 655 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 656 eeprom_buf); 657 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 658 qdev_prop_set_string(dev, "description", "pca0"); 659 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 660 aspeed_i2c_get_bus(&soc->i2c, 11), 661 &error_fatal); 662 /* Bus 11: TODO ucd90160@64 */ 663 } 664 665 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 666 { 667 AspeedSoCState *soc = &bmc->soc; 668 DeviceState *dev; 669 670 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 671 "emc1413", 0x4c)); 672 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 673 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 674 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 675 676 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 677 "emc1413", 0x4c)); 678 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 679 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 680 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 681 682 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 683 "emc1413", 0x4c)); 684 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 685 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 686 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 687 688 static uint8_t eeprom_buf[2 * 1024] = { 689 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 690 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 691 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 692 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 693 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 694 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 695 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 696 }; 697 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 698 eeprom_buf); 699 } 700 701 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 702 { 703 AspeedSoCState *soc = &bmc->soc; 704 I2CSlave *i2c_mux; 705 706 /* The at24c256 */ 707 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 708 709 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 710 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 711 0x48); 712 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 713 0x49); 714 715 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 716 "pca9546", 0x70); 717 /* It expects a TMP112 but a TMP105 is compatible */ 718 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 719 0x4a); 720 721 /* It expects a ds3232 but a ds1338 is good enough */ 722 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 723 724 /* It expects a pca9555 but a pca9552 is compatible */ 725 create_pca9552(soc, 8, 0x30); 726 } 727 728 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 729 { 730 AspeedSoCState *soc = &bmc->soc; 731 I2CSlave *i2c_mux; 732 733 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 734 735 create_pca9552(soc, 3, 0x61); 736 737 /* The rainier expects a TMP275 but a TMP105 is compatible */ 738 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 739 0x48); 740 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 741 0x49); 742 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 743 0x4a); 744 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 745 "pca9546", 0x70); 746 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 747 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 748 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 749 create_pca9552(soc, 4, 0x60); 750 751 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 752 0x48); 753 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 754 0x49); 755 create_pca9552(soc, 5, 0x60); 756 create_pca9552(soc, 5, 0x61); 757 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 758 "pca9546", 0x70); 759 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 760 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 761 762 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 763 0x48); 764 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 765 0x4a); 766 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 767 0x4b); 768 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 769 "pca9546", 0x70); 770 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 771 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 772 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 773 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 774 775 create_pca9552(soc, 7, 0x30); 776 create_pca9552(soc, 7, 0x31); 777 create_pca9552(soc, 7, 0x32); 778 create_pca9552(soc, 7, 0x33); 779 create_pca9552(soc, 7, 0x60); 780 create_pca9552(soc, 7, 0x61); 781 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 782 /* Bus 7: TODO si7021-a20@20 */ 783 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 784 0x48); 785 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 786 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 787 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 788 789 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 790 0x48); 791 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 792 0x4a); 793 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 794 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 795 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 796 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 797 create_pca9552(soc, 8, 0x60); 798 create_pca9552(soc, 8, 0x61); 799 /* Bus 8: ucd90320@11 */ 800 /* Bus 8: ucd90320@b */ 801 /* Bus 8: ucd90320@c */ 802 803 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 804 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 805 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 806 807 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 808 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 809 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 810 811 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 812 0x48); 813 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 814 0x49); 815 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 816 "pca9546", 0x70); 817 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 818 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 819 create_pca9552(soc, 11, 0x60); 820 821 822 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 823 create_pca9552(soc, 13, 0x60); 824 825 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 826 create_pca9552(soc, 14, 0x60); 827 828 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 829 create_pca9552(soc, 15, 0x60); 830 } 831 832 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 833 I2CBus **channels) 834 { 835 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 836 for (int i = 0; i < 8; i++) { 837 channels[i] = pca954x_i2c_get_bus(mux, i); 838 } 839 } 840 841 #define TYPE_LM75 TYPE_TMP105 842 #define TYPE_TMP75 TYPE_TMP105 843 #define TYPE_TMP422 "tmp422" 844 845 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 846 { 847 AspeedSoCState *soc = &bmc->soc; 848 I2CBus *i2c[144] = {}; 849 850 for (int i = 0; i < 16; i++) { 851 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 852 } 853 I2CBus *i2c180 = i2c[2]; 854 I2CBus *i2c480 = i2c[8]; 855 I2CBus *i2c600 = i2c[11]; 856 857 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 858 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 859 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 860 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 861 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 862 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 863 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 864 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 865 for (int i = 0; i < 8; i++) { 866 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 867 } 868 869 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 870 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 871 872 /* 873 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 874 * 24c02 size is 2Kbits or 256 bytes 875 */ 876 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 877 at24c_eeprom_init(i2c[20], 0x50, 256); 878 at24c_eeprom_init(i2c[22], 0x52, 256); 879 880 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 881 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 882 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 883 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 884 885 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 886 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 887 888 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 889 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 890 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 891 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 892 893 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 894 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 895 896 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 897 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 898 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 899 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 900 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 901 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 902 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 903 904 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 905 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 906 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 907 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 908 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 909 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 910 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 911 at24c_eeprom_init(i2c[28], 0x50, 256); 912 913 for (int i = 0; i < 8; i++) { 914 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 915 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 916 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 917 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 918 } 919 } 920 921 #define TYPE_TMP421 "tmp421" 922 923 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 924 { 925 AspeedSoCState *soc = &bmc->soc; 926 I2CBus *i2c[13] = {}; 927 for (int i = 0; i < 13; i++) { 928 if ((i == 8) || (i == 11)) { 929 continue; 930 } 931 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 932 } 933 934 /* Bus 0 - 5 all have the same config. */ 935 for (int i = 0; i < 6; i++) { 936 /* Missing model: ti,ina230 @ 0x45 */ 937 /* Missing model: mps,mp5023 @ 0x40 */ 938 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 939 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 940 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 941 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 942 /* Missing model: fsc,fusb302 @ 0x22 */ 943 } 944 945 /* Bus 6 */ 946 at24c_eeprom_init(i2c[6], 0x56, 65536); 947 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 948 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 949 950 951 /* Bus 7 */ 952 at24c_eeprom_init(i2c[7], 0x54, 65536); 953 954 /* Bus 9 */ 955 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 956 957 /* Bus 10 */ 958 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 959 /* Missing model: ti,hdc1080 @ 0x40 */ 960 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 961 962 /* Bus 12 */ 963 /* Missing model: adi,adm1278 @ 0x11 */ 964 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 965 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 966 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 967 } 968 969 static void fby35_i2c_init(AspeedMachineState *bmc) 970 { 971 AspeedSoCState *soc = &bmc->soc; 972 I2CBus *i2c[16]; 973 974 for (int i = 0; i < 16; i++) { 975 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 976 } 977 978 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 979 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 980 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 981 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 982 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 983 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 984 985 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 986 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 987 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 988 fby35_nic_fruid_len); 989 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 990 fby35_bb_fruid_len); 991 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 992 fby35_bmc_fruid_len); 993 994 /* 995 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 996 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 997 * each. 998 */ 999 } 1000 1001 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1002 { 1003 AspeedSoCState *soc = &bmc->soc; 1004 1005 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1006 } 1007 1008 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1009 { 1010 AspeedSoCState *soc = &bmc->soc; 1011 I2CSlave *therm_mux, *cpuvr_mux; 1012 1013 /* Create the generic DC-SCM hardware */ 1014 qcom_dc_scm_bmc_i2c_init(bmc); 1015 1016 /* Now create the Firework specific hardware */ 1017 1018 /* I2C7 CPUVR MUX */ 1019 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1020 "pca9546", 0x70); 1021 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1022 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1023 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1024 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1025 1026 /* I2C8 Thermal Diodes*/ 1027 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1028 "pca9548", 0x70); 1029 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1030 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1031 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1032 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1033 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1034 1035 /* I2C9 Fan Controller (MAX31785) */ 1036 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1037 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1038 } 1039 1040 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1041 { 1042 return ASPEED_MACHINE(obj)->mmio_exec; 1043 } 1044 1045 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1046 { 1047 ASPEED_MACHINE(obj)->mmio_exec = value; 1048 } 1049 1050 static void aspeed_machine_instance_init(Object *obj) 1051 { 1052 ASPEED_MACHINE(obj)->mmio_exec = false; 1053 } 1054 1055 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1056 { 1057 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1058 return g_strdup(bmc->fmc_model); 1059 } 1060 1061 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1062 { 1063 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1064 1065 g_free(bmc->fmc_model); 1066 bmc->fmc_model = g_strdup(value); 1067 } 1068 1069 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1070 { 1071 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1072 return g_strdup(bmc->spi_model); 1073 } 1074 1075 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1076 { 1077 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1078 1079 g_free(bmc->spi_model); 1080 bmc->spi_model = g_strdup(value); 1081 } 1082 1083 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1084 { 1085 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1086 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1087 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1088 1089 return g_strdup_printf("uart%d", uart_chosen - ASPEED_DEV_UART1 + 1); 1090 } 1091 1092 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1093 { 1094 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1095 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1096 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1097 int val; 1098 1099 if (sscanf(value, "uart%u", &val) != 1) { 1100 error_setg(errp, "Bad value for \"uart\" property"); 1101 return; 1102 } 1103 1104 /* The number of UART depends on the SoC */ 1105 if (val < 1 || val > sc->uarts_num) { 1106 error_setg(errp, "\"uart\" should be in range [1 - %d]", sc->uarts_num); 1107 return; 1108 } 1109 bmc->uart_chosen = ASPEED_DEV_UART1 + val - 1; 1110 } 1111 1112 static void aspeed_machine_class_props_init(ObjectClass *oc) 1113 { 1114 object_class_property_add_bool(oc, "execute-in-place", 1115 aspeed_get_mmio_exec, 1116 aspeed_set_mmio_exec); 1117 object_class_property_set_description(oc, "execute-in-place", 1118 "boot directly from CE0 flash device"); 1119 1120 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1121 aspeed_set_bmc_console); 1122 object_class_property_set_description(oc, "bmc-console", 1123 "Change the default UART to \"uartX\""); 1124 1125 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1126 aspeed_set_fmc_model); 1127 object_class_property_set_description(oc, "fmc-model", 1128 "Change the FMC Flash model"); 1129 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1130 aspeed_set_spi_model); 1131 object_class_property_set_description(oc, "spi-model", 1132 "Change the SPI Flash model"); 1133 } 1134 1135 static int aspeed_soc_num_cpus(const char *soc_name) 1136 { 1137 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 1138 return sc->num_cpus; 1139 } 1140 1141 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1142 { 1143 MachineClass *mc = MACHINE_CLASS(oc); 1144 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1145 1146 mc->init = aspeed_machine_init; 1147 mc->no_floppy = 1; 1148 mc->no_cdrom = 1; 1149 mc->no_parallel = 1; 1150 mc->default_ram_id = "ram"; 1151 amc->macs_mask = ASPEED_MAC0_ON; 1152 amc->uart_default = ASPEED_DEV_UART5; 1153 1154 aspeed_machine_class_props_init(oc); 1155 } 1156 1157 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1158 { 1159 MachineClass *mc = MACHINE_CLASS(oc); 1160 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1161 1162 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1163 amc->soc_name = "ast2400-a1"; 1164 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1165 amc->fmc_model = "n25q256a"; 1166 amc->spi_model = "mx25l25635f"; 1167 amc->num_cs = 1; 1168 amc->i2c_init = palmetto_bmc_i2c_init; 1169 mc->default_ram_size = 256 * MiB; 1170 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1171 aspeed_soc_num_cpus(amc->soc_name); 1172 }; 1173 1174 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1175 { 1176 MachineClass *mc = MACHINE_CLASS(oc); 1177 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1178 1179 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1180 amc->soc_name = "ast2400-a1"; 1181 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1182 amc->fmc_model = "n25q256a"; 1183 amc->spi_model = "mx25l25635e"; 1184 amc->num_cs = 1; 1185 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1186 mc->default_ram_size = 128 * MiB; 1187 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1188 aspeed_soc_num_cpus(amc->soc_name); 1189 } 1190 1191 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1192 void *data) 1193 { 1194 MachineClass *mc = MACHINE_CLASS(oc); 1195 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1196 1197 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1198 amc->soc_name = "ast2400-a1"; 1199 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1200 amc->fmc_model = "mx25l25635e"; 1201 amc->spi_model = "mx25l25635e"; 1202 amc->num_cs = 1; 1203 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1204 amc->i2c_init = palmetto_bmc_i2c_init; 1205 mc->default_ram_size = 256 * MiB; 1206 } 1207 1208 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1209 void *data) 1210 { 1211 MachineClass *mc = MACHINE_CLASS(oc); 1212 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1213 1214 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1215 amc->soc_name = "ast2500-a1"; 1216 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1217 amc->fmc_model = "mx25l25635e"; 1218 amc->spi_model = "mx25l25635e"; 1219 amc->num_cs = 1; 1220 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1221 amc->i2c_init = palmetto_bmc_i2c_init; 1222 mc->default_ram_size = 512 * MiB; 1223 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1224 aspeed_soc_num_cpus(amc->soc_name); 1225 } 1226 1227 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1228 { 1229 MachineClass *mc = MACHINE_CLASS(oc); 1230 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1231 1232 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1233 amc->soc_name = "ast2500-a1"; 1234 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1235 amc->fmc_model = "mx25l25635e"; 1236 amc->spi_model = "mx25l25635f"; 1237 amc->num_cs = 1; 1238 amc->i2c_init = ast2500_evb_i2c_init; 1239 mc->default_ram_size = 512 * MiB; 1240 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1241 aspeed_soc_num_cpus(amc->soc_name); 1242 }; 1243 1244 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data) 1245 { 1246 MachineClass *mc = MACHINE_CLASS(oc); 1247 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1248 1249 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1250 amc->soc_name = "ast2500-a1"; 1251 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1252 amc->hw_strap2 = 0; 1253 amc->fmc_model = "n25q256a"; 1254 amc->spi_model = "mx25l25635e"; 1255 amc->num_cs = 2; 1256 amc->i2c_init = yosemitev2_bmc_i2c_init; 1257 mc->default_ram_size = 512 * MiB; 1258 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1259 aspeed_soc_num_cpus(amc->soc_name); 1260 }; 1261 1262 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1263 { 1264 MachineClass *mc = MACHINE_CLASS(oc); 1265 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1266 1267 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1268 amc->soc_name = "ast2500-a1"; 1269 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1270 amc->fmc_model = "n25q256a"; 1271 amc->spi_model = "mx66l1g45g"; 1272 amc->num_cs = 2; 1273 amc->i2c_init = romulus_bmc_i2c_init; 1274 mc->default_ram_size = 512 * MiB; 1275 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1276 aspeed_soc_num_cpus(amc->soc_name); 1277 }; 1278 1279 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data) 1280 { 1281 MachineClass *mc = MACHINE_CLASS(oc); 1282 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1283 1284 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1285 amc->soc_name = "ast2500-a1"; 1286 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1287 amc->hw_strap2 = 0; 1288 amc->fmc_model = "n25q256a"; 1289 amc->spi_model = "mx25l25635e"; 1290 amc->num_cs = 2; 1291 amc->i2c_init = tiogapass_bmc_i2c_init; 1292 mc->default_ram_size = 1 * GiB; 1293 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1294 aspeed_soc_num_cpus(amc->soc_name); 1295 aspeed_soc_num_cpus(amc->soc_name); 1296 }; 1297 1298 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1299 { 1300 MachineClass *mc = MACHINE_CLASS(oc); 1301 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1302 1303 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1304 amc->soc_name = "ast2500-a1"; 1305 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1306 amc->fmc_model = "mx66l1g45g"; 1307 amc->spi_model = "mx66l1g45g"; 1308 amc->num_cs = 2; 1309 amc->i2c_init = sonorapass_bmc_i2c_init; 1310 mc->default_ram_size = 512 * MiB; 1311 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1312 aspeed_soc_num_cpus(amc->soc_name); 1313 }; 1314 1315 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1316 { 1317 MachineClass *mc = MACHINE_CLASS(oc); 1318 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1319 1320 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1321 amc->soc_name = "ast2500-a1"; 1322 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1323 amc->fmc_model = "mx25l25635f"; 1324 amc->spi_model = "mx66l1g45g"; 1325 amc->num_cs = 2; 1326 amc->i2c_init = witherspoon_bmc_i2c_init; 1327 mc->default_ram_size = 512 * MiB; 1328 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1329 aspeed_soc_num_cpus(amc->soc_name); 1330 }; 1331 1332 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1333 { 1334 MachineClass *mc = MACHINE_CLASS(oc); 1335 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1336 1337 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1338 amc->soc_name = "ast2600-a3"; 1339 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1340 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1341 amc->fmc_model = "mx66u51235f"; 1342 amc->spi_model = "mx66u51235f"; 1343 amc->num_cs = 1; 1344 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1345 ASPEED_MAC3_ON; 1346 amc->i2c_init = ast2600_evb_i2c_init; 1347 mc->default_ram_size = 1 * GiB; 1348 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1349 aspeed_soc_num_cpus(amc->soc_name); 1350 }; 1351 1352 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1353 { 1354 MachineClass *mc = MACHINE_CLASS(oc); 1355 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1356 1357 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1358 amc->soc_name = "ast2600-a3"; 1359 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1360 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1361 amc->fmc_model = "mx66l1g45g"; 1362 amc->spi_model = "mx66l1g45g"; 1363 amc->num_cs = 2; 1364 amc->macs_mask = ASPEED_MAC2_ON; 1365 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1366 mc->default_ram_size = 1 * GiB; 1367 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1368 aspeed_soc_num_cpus(amc->soc_name); 1369 }; 1370 1371 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1372 { 1373 MachineClass *mc = MACHINE_CLASS(oc); 1374 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1375 1376 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1377 amc->soc_name = "ast2500-a1"; 1378 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1379 amc->fmc_model = "n25q512a"; 1380 amc->spi_model = "mx25l25635e"; 1381 amc->num_cs = 2; 1382 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1383 amc->i2c_init = g220a_bmc_i2c_init; 1384 mc->default_ram_size = 1024 * MiB; 1385 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1386 aspeed_soc_num_cpus(amc->soc_name); 1387 }; 1388 1389 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1390 { 1391 MachineClass *mc = MACHINE_CLASS(oc); 1392 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1393 1394 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1395 amc->soc_name = "ast2500-a1"; 1396 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1397 amc->fmc_model = "n25q512a"; 1398 amc->spi_model = "mx25l25635e"; 1399 amc->num_cs = 2; 1400 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1401 amc->i2c_init = fp5280g2_bmc_i2c_init; 1402 mc->default_ram_size = 512 * MiB; 1403 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1404 aspeed_soc_num_cpus(amc->soc_name); 1405 }; 1406 1407 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1408 { 1409 MachineClass *mc = MACHINE_CLASS(oc); 1410 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1411 1412 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1413 amc->soc_name = "ast2600-a3"; 1414 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1415 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1416 amc->fmc_model = "mx66l1g45g"; 1417 amc->spi_model = "mx66l1g45g"; 1418 amc->num_cs = 2; 1419 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1420 amc->i2c_init = rainier_bmc_i2c_init; 1421 mc->default_ram_size = 1 * GiB; 1422 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1423 aspeed_soc_num_cpus(amc->soc_name); 1424 }; 1425 1426 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 1427 #if HOST_LONG_BITS == 32 1428 #define FUJI_BMC_RAM_SIZE (1 * GiB) 1429 #else 1430 #define FUJI_BMC_RAM_SIZE (2 * GiB) 1431 #endif 1432 1433 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1434 { 1435 MachineClass *mc = MACHINE_CLASS(oc); 1436 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1437 1438 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1439 amc->soc_name = "ast2600-a3"; 1440 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1441 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1442 amc->fmc_model = "mx66l1g45g"; 1443 amc->spi_model = "mx66l1g45g"; 1444 amc->num_cs = 2; 1445 amc->macs_mask = ASPEED_MAC3_ON; 1446 amc->i2c_init = fuji_bmc_i2c_init; 1447 amc->uart_default = ASPEED_DEV_UART1; 1448 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1449 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1450 aspeed_soc_num_cpus(amc->soc_name); 1451 }; 1452 1453 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 1454 #if HOST_LONG_BITS == 32 1455 #define BLETCHLEY_BMC_RAM_SIZE (1 * GiB) 1456 #else 1457 #define BLETCHLEY_BMC_RAM_SIZE (2 * GiB) 1458 #endif 1459 1460 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1461 { 1462 MachineClass *mc = MACHINE_CLASS(oc); 1463 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1464 1465 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1466 amc->soc_name = "ast2600-a3"; 1467 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1468 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1469 amc->fmc_model = "w25q01jvq"; 1470 amc->spi_model = NULL; 1471 amc->num_cs = 2; 1472 amc->macs_mask = ASPEED_MAC2_ON; 1473 amc->i2c_init = bletchley_bmc_i2c_init; 1474 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1475 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1476 aspeed_soc_num_cpus(amc->soc_name); 1477 } 1478 1479 static void fby35_reset(MachineState *state, ShutdownCause reason) 1480 { 1481 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1482 AspeedGPIOState *gpio = &bmc->soc.gpio; 1483 1484 qemu_devices_reset(reason); 1485 1486 /* Board ID: 7 (Class-1, 4 slots) */ 1487 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1488 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1489 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1490 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1491 1492 /* Slot presence pins, inverse polarity. (False means present) */ 1493 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1494 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1495 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1496 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1497 1498 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1499 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1500 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1501 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1502 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1503 } 1504 1505 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) 1506 { 1507 MachineClass *mc = MACHINE_CLASS(oc); 1508 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1509 1510 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1511 mc->reset = fby35_reset; 1512 amc->fmc_model = "mx66l1g45g"; 1513 amc->num_cs = 2; 1514 amc->macs_mask = ASPEED_MAC3_ON; 1515 amc->i2c_init = fby35_i2c_init; 1516 /* FIXME: Replace this macro with something more general */ 1517 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1518 } 1519 1520 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1521 /* Main SYSCLK frequency in Hz (200MHz) */ 1522 #define SYSCLK_FRQ 200000000ULL 1523 1524 static void aspeed_minibmc_machine_init(MachineState *machine) 1525 { 1526 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1527 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1528 Clock *sysclk; 1529 1530 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1531 clock_set_hz(sysclk, SYSCLK_FRQ); 1532 1533 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 1534 qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk); 1535 1536 object_property_set_link(OBJECT(&bmc->soc), "memory", 1537 OBJECT(get_system_memory()), &error_abort); 1538 connect_serial_hds_to_uarts(bmc); 1539 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 1540 1541 aspeed_board_init_flashes(&bmc->soc.fmc, 1542 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1543 amc->num_cs, 1544 0); 1545 1546 aspeed_board_init_flashes(&bmc->soc.spi[0], 1547 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1548 amc->num_cs, amc->num_cs); 1549 1550 aspeed_board_init_flashes(&bmc->soc.spi[1], 1551 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1552 amc->num_cs, (amc->num_cs * 2)); 1553 1554 if (amc->i2c_init) { 1555 amc->i2c_init(bmc); 1556 } 1557 1558 armv7m_load_kernel(ARM_CPU(first_cpu), 1559 machine->kernel_filename, 1560 0, 1561 AST1030_INTERNAL_FLASH_SIZE); 1562 } 1563 1564 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1565 { 1566 AspeedSoCState *soc = &bmc->soc; 1567 1568 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1569 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1570 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1571 1572 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1573 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1574 } 1575 1576 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1577 void *data) 1578 { 1579 MachineClass *mc = MACHINE_CLASS(oc); 1580 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1581 1582 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1583 amc->soc_name = "ast1030-a1"; 1584 amc->hw_strap1 = 0; 1585 amc->hw_strap2 = 0; 1586 mc->init = aspeed_minibmc_machine_init; 1587 amc->i2c_init = ast1030_evb_i2c_init; 1588 mc->default_ram_size = 0; 1589 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1; 1590 amc->fmc_model = "sst25vf032b"; 1591 amc->spi_model = "sst25vf032b"; 1592 amc->num_cs = 2; 1593 amc->macs_mask = 0; 1594 } 1595 1596 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1597 void *data) 1598 { 1599 MachineClass *mc = MACHINE_CLASS(oc); 1600 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1601 1602 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1603 amc->soc_name = "ast2600-a3"; 1604 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1605 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1606 amc->fmc_model = "n25q512a"; 1607 amc->spi_model = "n25q512a"; 1608 amc->num_cs = 2; 1609 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1610 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1611 mc->default_ram_size = 1 * GiB; 1612 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1613 aspeed_soc_num_cpus(amc->soc_name); 1614 }; 1615 1616 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1617 void *data) 1618 { 1619 MachineClass *mc = MACHINE_CLASS(oc); 1620 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1621 1622 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1623 amc->soc_name = "ast2600-a3"; 1624 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1625 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1626 amc->fmc_model = "n25q512a"; 1627 amc->spi_model = "n25q512a"; 1628 amc->num_cs = 2; 1629 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1630 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1631 mc->default_ram_size = 1 * GiB; 1632 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1633 aspeed_soc_num_cpus(amc->soc_name); 1634 }; 1635 1636 static const TypeInfo aspeed_machine_types[] = { 1637 { 1638 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1639 .parent = TYPE_ASPEED_MACHINE, 1640 .class_init = aspeed_machine_palmetto_class_init, 1641 }, { 1642 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1643 .parent = TYPE_ASPEED_MACHINE, 1644 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1645 }, { 1646 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 1647 .parent = TYPE_ASPEED_MACHINE, 1648 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 1649 }, { 1650 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1651 .parent = TYPE_ASPEED_MACHINE, 1652 .class_init = aspeed_machine_ast2500_evb_class_init, 1653 }, { 1654 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1655 .parent = TYPE_ASPEED_MACHINE, 1656 .class_init = aspeed_machine_romulus_class_init, 1657 }, { 1658 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1659 .parent = TYPE_ASPEED_MACHINE, 1660 .class_init = aspeed_machine_sonorapass_class_init, 1661 }, { 1662 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1663 .parent = TYPE_ASPEED_MACHINE, 1664 .class_init = aspeed_machine_witherspoon_class_init, 1665 }, { 1666 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1667 .parent = TYPE_ASPEED_MACHINE, 1668 .class_init = aspeed_machine_ast2600_evb_class_init, 1669 }, { 1670 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 1671 .parent = TYPE_ASPEED_MACHINE, 1672 .class_init = aspeed_machine_yosemitev2_class_init, 1673 }, { 1674 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1675 .parent = TYPE_ASPEED_MACHINE, 1676 .class_init = aspeed_machine_tacoma_class_init, 1677 }, { 1678 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 1679 .parent = TYPE_ASPEED_MACHINE, 1680 .class_init = aspeed_machine_tiogapass_class_init, 1681 }, { 1682 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1683 .parent = TYPE_ASPEED_MACHINE, 1684 .class_init = aspeed_machine_g220a_class_init, 1685 }, { 1686 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 1687 .parent = TYPE_ASPEED_MACHINE, 1688 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 1689 }, { 1690 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 1691 .parent = TYPE_ASPEED_MACHINE, 1692 .class_init = aspeed_machine_qcom_firework_class_init, 1693 }, { 1694 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1695 .parent = TYPE_ASPEED_MACHINE, 1696 .class_init = aspeed_machine_fp5280g2_class_init, 1697 }, { 1698 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1699 .parent = TYPE_ASPEED_MACHINE, 1700 .class_init = aspeed_machine_quanta_q71l_class_init, 1701 }, { 1702 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1703 .parent = TYPE_ASPEED_MACHINE, 1704 .class_init = aspeed_machine_rainier_class_init, 1705 }, { 1706 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1707 .parent = TYPE_ASPEED_MACHINE, 1708 .class_init = aspeed_machine_fuji_class_init, 1709 }, { 1710 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1711 .parent = TYPE_ASPEED_MACHINE, 1712 .class_init = aspeed_machine_bletchley_class_init, 1713 }, { 1714 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1715 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1716 .class_init = aspeed_machine_fby35_class_init, 1717 }, { 1718 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1719 .parent = TYPE_ASPEED_MACHINE, 1720 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1721 }, { 1722 .name = TYPE_ASPEED_MACHINE, 1723 .parent = TYPE_MACHINE, 1724 .instance_size = sizeof(AspeedMachineState), 1725 .instance_init = aspeed_machine_instance_init, 1726 .class_size = sizeof(AspeedMachineClass), 1727 .class_init = aspeed_machine_class_init, 1728 .abstract = true, 1729 } 1730 }; 1731 1732 DEFINE_TYPES(aspeed_machine_types) 1733