1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/i2c/i2c_mux_pca954x.h" 18 #include "hw/i2c/smbus_eeprom.h" 19 #include "hw/misc/pca9552.h" 20 #include "hw/sensor/tmp105.h" 21 #include "hw/misc/led.h" 22 #include "hw/qdev-properties.h" 23 #include "sysemu/block-backend.h" 24 #include "hw/loader.h" 25 #include "qemu/error-report.h" 26 #include "qemu/units.h" 27 28 static struct arm_boot_info aspeed_board_binfo = { 29 .board_id = -1, /* device-tree-only board */ 30 }; 31 32 struct AspeedMachineState { 33 /* Private */ 34 MachineState parent_obj; 35 /* Public */ 36 37 AspeedSoCState soc; 38 MemoryRegion ram_container; 39 MemoryRegion max_ram; 40 bool mmio_exec; 41 char *fmc_model; 42 char *spi_model; 43 }; 44 45 /* Palmetto hardware value: 0x120CE416 */ 46 #define PALMETTO_BMC_HW_STRAP1 ( \ 47 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 48 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 49 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 50 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 51 SCU_HW_STRAP_VGA_CLASS_CODE | \ 52 SCU_HW_STRAP_LPC_RESET_PIN | \ 53 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 54 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 55 SCU_HW_STRAP_SPI_WIDTH | \ 56 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 57 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 58 59 /* TODO: Find the actual hardware value */ 60 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 63 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 65 SCU_HW_STRAP_VGA_CLASS_CODE | \ 66 SCU_HW_STRAP_LPC_RESET_PIN | \ 67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 69 SCU_HW_STRAP_SPI_WIDTH | \ 70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 72 73 /* AST2500 evb hardware value: 0xF100C2E6 */ 74 #define AST2500_EVB_HW_STRAP1 (( \ 75 AST2500_HW_STRAP1_DEFAULTS | \ 76 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 77 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 78 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 79 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 80 SCU_HW_STRAP_MAC1_RGMII | \ 81 SCU_HW_STRAP_MAC0_RGMII) & \ 82 ~SCU_HW_STRAP_2ND_BOOT_WDT) 83 84 /* Romulus hardware value: 0xF10AD206 */ 85 #define ROMULUS_BMC_HW_STRAP1 ( \ 86 AST2500_HW_STRAP1_DEFAULTS | \ 87 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 88 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 89 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 90 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 91 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 92 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 93 94 /* Sonorapass hardware value: 0xF100D216 */ 95 #define SONORAPASS_BMC_HW_STRAP1 ( \ 96 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 97 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 98 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 99 SCU_AST2500_HW_STRAP_RESERVED28 | \ 100 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 101 SCU_HW_STRAP_VGA_CLASS_CODE | \ 102 SCU_HW_STRAP_LPC_RESET_PIN | \ 103 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 104 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 105 SCU_HW_STRAP_VGA_BIOS_ROM | \ 106 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 107 SCU_AST2500_HW_STRAP_RESERVED1) 108 109 /* Swift hardware value: 0xF11AD206 */ 110 #define SWIFT_BMC_HW_STRAP1 ( \ 111 AST2500_HW_STRAP1_DEFAULTS | \ 112 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 113 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 114 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 115 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 116 SCU_H_PLL_BYPASS_EN | \ 117 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 119 120 #define G220A_BMC_HW_STRAP1 ( \ 121 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 122 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 123 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 124 SCU_AST2500_HW_STRAP_RESERVED28 | \ 125 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 126 SCU_HW_STRAP_2ND_BOOT_WDT | \ 127 SCU_HW_STRAP_VGA_CLASS_CODE | \ 128 SCU_HW_STRAP_LPC_RESET_PIN | \ 129 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 130 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 131 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 132 SCU_AST2500_HW_STRAP_RESERVED1) 133 134 /* FP5280G2 hardware value: 0XF100D286 */ 135 #define FP5280G2_BMC_HW_STRAP1 ( \ 136 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 137 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 138 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 139 SCU_AST2500_HW_STRAP_RESERVED28 | \ 140 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 141 SCU_HW_STRAP_VGA_CLASS_CODE | \ 142 SCU_HW_STRAP_LPC_RESET_PIN | \ 143 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 144 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 145 SCU_HW_STRAP_MAC1_RGMII | \ 146 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 147 SCU_AST2500_HW_STRAP_RESERVED1) 148 149 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 150 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 151 152 /* Quanta-Q71l hardware value */ 153 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 154 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 155 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 156 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 157 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 158 SCU_HW_STRAP_VGA_CLASS_CODE | \ 159 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 160 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 161 SCU_HW_STRAP_SPI_WIDTH | \ 162 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 163 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 164 165 /* AST2600 evb hardware value */ 166 #define AST2600_EVB_HW_STRAP1 0x000000C0 167 #define AST2600_EVB_HW_STRAP2 0x00000003 168 169 /* Tacoma hardware value */ 170 #define TACOMA_BMC_HW_STRAP1 0x00000000 171 #define TACOMA_BMC_HW_STRAP2 0x00000040 172 173 /* Rainier hardware value: (QEMU prototype) */ 174 #define RAINIER_BMC_HW_STRAP1 0x00000000 175 #define RAINIER_BMC_HW_STRAP2 0x00000000 176 177 /* Fuji hardware value */ 178 #define FUJI_BMC_HW_STRAP1 0x00000000 179 #define FUJI_BMC_HW_STRAP2 0x00000000 180 181 /* 182 * The max ram region is for firmwares that scan the address space 183 * with load/store to guess how much RAM the SoC has. 184 */ 185 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 186 { 187 return 0; 188 } 189 190 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 191 unsigned size) 192 { 193 /* Discard writes */ 194 } 195 196 static const MemoryRegionOps max_ram_ops = { 197 .read = max_ram_read, 198 .write = max_ram_write, 199 .endianness = DEVICE_NATIVE_ENDIAN, 200 }; 201 202 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 203 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 204 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 205 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 206 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 207 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 208 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 209 210 static void aspeed_write_smpboot(ARMCPU *cpu, 211 const struct arm_boot_info *info) 212 { 213 static const uint32_t poll_mailbox_ready[] = { 214 /* 215 * r2 = per-cpu go sign value 216 * r1 = AST_SMP_MBOX_FIELD_ENTRY 217 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 218 */ 219 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 220 0xe21000ff, /* ands r0, r0, #255 */ 221 0xe59f201c, /* ldr r2, [pc, #28] */ 222 0xe1822000, /* orr r2, r2, r0 */ 223 224 0xe59f1018, /* ldr r1, [pc, #24] */ 225 0xe59f0018, /* ldr r0, [pc, #24] */ 226 227 0xe320f002, /* wfe */ 228 0xe5904000, /* ldr r4, [r0] */ 229 0xe1520004, /* cmp r2, r4 */ 230 0x1afffffb, /* bne <wfe> */ 231 0xe591f000, /* ldr pc, [r1] */ 232 AST_SMP_MBOX_GOSIGN, 233 AST_SMP_MBOX_FIELD_ENTRY, 234 AST_SMP_MBOX_FIELD_GOSIGN, 235 }; 236 237 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 238 sizeof(poll_mailbox_ready), 239 info->smp_loader_start); 240 } 241 242 static void aspeed_reset_secondary(ARMCPU *cpu, 243 const struct arm_boot_info *info) 244 { 245 AddressSpace *as = arm_boot_address_space(cpu, info); 246 CPUState *cs = CPU(cpu); 247 248 /* info->smp_bootreg_addr */ 249 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 250 MEMTXATTRS_UNSPECIFIED, NULL); 251 cpu_set_pc(cs, info->smp_loader_start); 252 } 253 254 #define FIRMWARE_ADDR 0x0 255 256 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 257 Error **errp) 258 { 259 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 260 uint8_t *storage; 261 int64_t size; 262 263 /* The block backend size should have already been 'validated' by 264 * the creation of the m25p80 object. 265 */ 266 size = blk_getlength(blk); 267 if (size <= 0) { 268 error_setg(errp, "failed to get flash size"); 269 return; 270 } 271 272 if (rom_size > size) { 273 rom_size = size; 274 } 275 276 storage = g_new0(uint8_t, rom_size); 277 if (blk_pread(blk, 0, storage, rom_size) < 0) { 278 error_setg(errp, "failed to read the initial flash content"); 279 return; 280 } 281 282 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 283 g_free(storage); 284 } 285 286 static void aspeed_board_init_flashes(AspeedSMCState *s, 287 const char *flashtype, 288 int unit0) 289 { 290 int i ; 291 292 for (i = 0; i < s->num_cs; ++i) { 293 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 294 qemu_irq cs_line; 295 DeviceState *dev; 296 297 dev = qdev_new(flashtype); 298 if (dinfo) { 299 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 300 } 301 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 302 303 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); 304 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 305 } 306 } 307 308 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 309 { 310 DeviceState *card; 311 312 if (!dinfo) { 313 return; 314 } 315 card = qdev_new(TYPE_SD_CARD); 316 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 317 &error_fatal); 318 qdev_realize_and_unref(card, 319 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 320 &error_fatal); 321 } 322 323 static void aspeed_machine_init(MachineState *machine) 324 { 325 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 326 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 327 AspeedSoCClass *sc; 328 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 329 ram_addr_t max_ram_size; 330 int i; 331 NICInfo *nd = &nd_table[0]; 332 333 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 334 4 * GiB); 335 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 336 337 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 338 339 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 340 341 /* 342 * This will error out if isize is not supported by memory controller. 343 */ 344 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size, 345 &error_fatal); 346 347 for (i = 0; i < sc->macs_num; i++) { 348 if ((amc->macs_mask & (1 << i)) && nd->used) { 349 qemu_check_nic_model(nd, TYPE_FTGMAC100); 350 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 351 nd++; 352 } 353 } 354 355 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 356 &error_abort); 357 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 358 &error_abort); 359 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs, 360 &error_abort); 361 object_property_set_link(OBJECT(&bmc->soc), "dram", 362 OBJECT(machine->ram), &error_abort); 363 if (machine->kernel_filename) { 364 /* 365 * When booting with a -kernel command line there is no u-boot 366 * that runs to unlock the SCU. In this case set the default to 367 * be unlocked as the kernel expects 368 */ 369 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 370 ASPEED_SCU_PROT_KEY, &error_abort); 371 } 372 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", 373 amc->uart_default); 374 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 375 376 memory_region_add_subregion(get_system_memory(), 377 sc->memmap[ASPEED_DEV_SDRAM], 378 &bmc->ram_container); 379 380 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 381 &error_abort); 382 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 383 "max_ram", max_ram_size - machine->ram_size); 384 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram); 385 386 aspeed_board_init_flashes(&bmc->soc.fmc, 387 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 388 0); 389 aspeed_board_init_flashes(&bmc->soc.spi[0], 390 bmc->spi_model ? bmc->spi_model : amc->spi_model, 391 bmc->soc.fmc.num_cs); 392 393 /* Install first FMC flash content as a boot rom. */ 394 if (drive0) { 395 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 396 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 397 uint64_t size = memory_region_size(&fl->mmio); 398 399 /* 400 * create a ROM region using the default mapping window size of 401 * the flash module. The window size is 64MB for the AST2400 402 * SoC and 128MB for the AST2500 SoC, which is twice as big as 403 * needed by the flash modules of the Aspeed machines. 404 */ 405 if (ASPEED_MACHINE(machine)->mmio_exec) { 406 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", 407 &fl->mmio, 0, size); 408 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 409 boot_rom); 410 } else { 411 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", 412 size, &error_abort); 413 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 414 boot_rom); 415 write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort); 416 } 417 } 418 419 if (machine->kernel_filename && sc->num_cpus > 1) { 420 /* With no u-boot we must set up a boot stub for the secondary CPU */ 421 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 422 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 423 0x80, &error_abort); 424 memory_region_add_subregion(get_system_memory(), 425 AST_SMP_MAILBOX_BASE, smpboot); 426 427 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 428 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 429 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 430 } 431 432 aspeed_board_binfo.ram_size = machine->ram_size; 433 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 434 435 if (amc->i2c_init) { 436 amc->i2c_init(bmc); 437 } 438 439 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 440 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], 441 drive_get(IF_SD, 0, i)); 442 } 443 444 if (bmc->soc.emmc.num_slots) { 445 sdhci_attach_drive(&bmc->soc.emmc.slots[0], 446 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots)); 447 } 448 449 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 450 } 451 452 static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize) 453 { 454 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 455 DeviceState *dev = DEVICE(i2c_dev); 456 457 qdev_prop_set_uint32(dev, "rom-size", rsize); 458 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); 459 } 460 461 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 462 { 463 AspeedSoCState *soc = &bmc->soc; 464 DeviceState *dev; 465 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 466 467 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 468 * enough to provide basic RTC features. Alarms will be missing */ 469 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 470 471 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 472 eeprom_buf); 473 474 /* add a TMP423 temperature sensor */ 475 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 476 "tmp423", 0x4c)); 477 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 478 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 479 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 480 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 481 } 482 483 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 484 { 485 AspeedSoCState *soc = &bmc->soc; 486 487 /* 488 * The quanta-q71l platform expects tmp75s which are compatible with 489 * tmp105s. 490 */ 491 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 492 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 493 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 494 495 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 496 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 497 /* TODO: Add Memory Riser i2c mux and eeproms. */ 498 499 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 500 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 501 502 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 503 504 /* i2c-7 */ 505 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 506 /* - i2c@0: pmbus@59 */ 507 /* - i2c@1: pmbus@58 */ 508 /* - i2c@2: pmbus@58 */ 509 /* - i2c@3: pmbus@59 */ 510 511 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 512 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 513 } 514 515 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 516 { 517 AspeedSoCState *soc = &bmc->soc; 518 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 519 520 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 521 eeprom_buf); 522 523 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 524 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 525 TYPE_TMP105, 0x4d); 526 527 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 528 * plugged on the I2C bus header */ 529 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 530 } 531 532 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 533 { 534 /* Start with some devices on our I2C busses */ 535 ast2500_evb_i2c_init(bmc); 536 } 537 538 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 539 { 540 AspeedSoCState *soc = &bmc->soc; 541 542 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 543 * good enough */ 544 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 545 } 546 547 static void swift_bmc_i2c_init(AspeedMachineState *bmc) 548 { 549 AspeedSoCState *soc = &bmc->soc; 550 551 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60); 552 553 /* The swift board expects a TMP275 but a TMP105 is compatible */ 554 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48); 555 /* The swift board expects a pca9551 but a pca9552 is compatible */ 556 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60); 557 558 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ 559 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32); 560 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 561 562 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 563 /* The swift board expects a pca9539 but a pca9552 is compatible */ 564 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74); 565 566 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 567 /* The swift board expects a pca9539 but a pca9552 is compatible */ 568 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552", 569 0x74); 570 571 /* The swift board expects a TMP275 but a TMP105 is compatible */ 572 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48); 573 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a); 574 } 575 576 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 577 { 578 AspeedSoCState *soc = &bmc->soc; 579 580 /* bus 2 : */ 581 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 582 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 583 /* bus 2 : pca9546 @ 0x73 */ 584 585 /* bus 3 : pca9548 @ 0x70 */ 586 587 /* bus 4 : */ 588 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 589 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 590 eeprom4_54); 591 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 592 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76); 593 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 594 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77); 595 596 /* bus 6 : */ 597 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 598 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 599 /* bus 6 : pca9546 @ 0x73 */ 600 601 /* bus 8 : */ 602 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 603 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 604 eeprom8_56); 605 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 606 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); 607 /* bus 8 : adc128d818 @ 0x1d */ 608 /* bus 8 : adc128d818 @ 0x1f */ 609 610 /* 611 * bus 13 : pca9548 @ 0x71 612 * - channel 3: 613 * - tmm421 @ 0x4c 614 * - tmp421 @ 0x4e 615 * - tmp421 @ 0x4f 616 */ 617 618 } 619 620 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 621 { 622 static const struct { 623 unsigned gpio_id; 624 LEDColor color; 625 const char *description; 626 bool gpio_polarity; 627 } pca1_leds[] = { 628 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 629 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 630 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 631 }; 632 AspeedSoCState *soc = &bmc->soc; 633 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 634 DeviceState *dev; 635 LEDState *led; 636 637 /* Bus 3: TODO bmp280@77 */ 638 /* Bus 3: TODO max31785@52 */ 639 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 640 qdev_prop_set_string(dev, "description", "pca1"); 641 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 642 aspeed_i2c_get_bus(&soc->i2c, 3), 643 &error_fatal); 644 645 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 646 led = led_create_simple(OBJECT(bmc), 647 pca1_leds[i].gpio_polarity, 648 pca1_leds[i].color, 649 pca1_leds[i].description); 650 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 651 qdev_get_gpio_in(DEVICE(led), 0)); 652 } 653 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 654 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 655 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 656 657 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 658 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 659 0x4a); 660 661 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 662 * good enough */ 663 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 664 665 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 666 eeprom_buf); 667 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 668 qdev_prop_set_string(dev, "description", "pca0"); 669 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 670 aspeed_i2c_get_bus(&soc->i2c, 11), 671 &error_fatal); 672 /* Bus 11: TODO ucd90160@64 */ 673 } 674 675 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 676 { 677 AspeedSoCState *soc = &bmc->soc; 678 DeviceState *dev; 679 680 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 681 "emc1413", 0x4c)); 682 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 683 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 684 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 685 686 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 687 "emc1413", 0x4c)); 688 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 689 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 690 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 691 692 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 693 "emc1413", 0x4c)); 694 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 695 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 696 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 697 698 static uint8_t eeprom_buf[2 * 1024] = { 699 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 700 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 701 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 702 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 703 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 704 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 705 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 706 }; 707 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 708 eeprom_buf); 709 } 710 711 static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize) 712 { 713 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 714 DeviceState *dev = DEVICE(i2c_dev); 715 716 qdev_prop_set_uint32(dev, "rom-size", rsize); 717 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); 718 } 719 720 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 721 { 722 AspeedSoCState *soc = &bmc->soc; 723 I2CSlave *i2c_mux; 724 725 /* The at24c256 */ 726 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 727 728 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 729 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 730 0x48); 731 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 732 0x49); 733 734 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 735 "pca9546", 0x70); 736 /* It expects a TMP112 but a TMP105 is compatible */ 737 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 738 0x4a); 739 740 /* It expects a ds3232 but a ds1338 is good enough */ 741 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 742 743 /* It expects a pca9555 but a pca9552 is compatible */ 744 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_PCA9552, 745 0x20); 746 } 747 748 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 749 { 750 AspeedSoCState *soc = &bmc->soc; 751 I2CSlave *i2c_mux; 752 753 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 754 755 /* The rainier expects a TMP275 but a TMP105 is compatible */ 756 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 757 0x48); 758 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 759 0x49); 760 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 761 0x4a); 762 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 763 "pca9546", 0x70); 764 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 765 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 766 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 767 768 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 769 0x48); 770 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 771 0x49); 772 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 773 "pca9546", 0x70); 774 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 775 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 776 777 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 778 0x48); 779 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 780 0x4a); 781 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 782 0x4b); 783 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 784 "pca9546", 0x70); 785 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 786 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 787 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 788 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 789 790 /* Bus 7: TODO max31785@52 */ 791 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61); 792 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 793 /* Bus 7: TODO si7021-a20@20 */ 794 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 795 0x48); 796 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 797 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 798 799 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 800 0x48); 801 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 802 0x4a); 803 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB); 804 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB); 805 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); 806 /* Bus 8: ucd90320@11 */ 807 /* Bus 8: ucd90320@b */ 808 /* Bus 8: ucd90320@c */ 809 810 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 811 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 812 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 813 814 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 815 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 816 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 817 818 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 819 0x48); 820 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 821 0x49); 822 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 823 "pca9546", 0x70); 824 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 825 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 826 827 828 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 829 830 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 831 832 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 833 } 834 835 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 836 I2CBus **channels) 837 { 838 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 839 for (int i = 0; i < 8; i++) { 840 channels[i] = pca954x_i2c_get_bus(mux, i); 841 } 842 } 843 844 #define TYPE_LM75 TYPE_TMP105 845 #define TYPE_TMP75 TYPE_TMP105 846 #define TYPE_TMP422 "tmp422" 847 848 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 849 { 850 AspeedSoCState *soc = &bmc->soc; 851 I2CBus *i2c[144] = {}; 852 853 for (int i = 0; i < 16; i++) { 854 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 855 } 856 I2CBus *i2c180 = i2c[2]; 857 I2CBus *i2c480 = i2c[8]; 858 I2CBus *i2c600 = i2c[11]; 859 860 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 861 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 862 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 863 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 864 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 865 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 866 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 867 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 868 for (int i = 0; i < 8; i++) { 869 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 870 } 871 872 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 873 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 874 875 aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB); 876 aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB); 877 aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB); 878 879 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 880 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 881 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 882 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 883 884 aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB); 885 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 886 887 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 888 aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB); 889 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 890 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 891 892 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 893 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 894 895 aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB); 896 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 897 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 898 aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB); 899 aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB); 900 aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB); 901 aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB); 902 903 aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB); 904 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 905 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 906 aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB); 907 aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB); 908 aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB); 909 aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB); 910 aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB); 911 912 for (int i = 0; i < 8; i++) { 913 aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 914 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 915 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 916 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 917 } 918 } 919 920 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 921 { 922 return ASPEED_MACHINE(obj)->mmio_exec; 923 } 924 925 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 926 { 927 ASPEED_MACHINE(obj)->mmio_exec = value; 928 } 929 930 static void aspeed_machine_instance_init(Object *obj) 931 { 932 ASPEED_MACHINE(obj)->mmio_exec = false; 933 } 934 935 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 936 { 937 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 938 return g_strdup(bmc->fmc_model); 939 } 940 941 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 942 { 943 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 944 945 g_free(bmc->fmc_model); 946 bmc->fmc_model = g_strdup(value); 947 } 948 949 static char *aspeed_get_spi_model(Object *obj, Error **errp) 950 { 951 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 952 return g_strdup(bmc->spi_model); 953 } 954 955 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 956 { 957 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 958 959 g_free(bmc->spi_model); 960 bmc->spi_model = g_strdup(value); 961 } 962 963 static void aspeed_machine_class_props_init(ObjectClass *oc) 964 { 965 object_class_property_add_bool(oc, "execute-in-place", 966 aspeed_get_mmio_exec, 967 aspeed_set_mmio_exec); 968 object_class_property_set_description(oc, "execute-in-place", 969 "boot directly from CE0 flash device"); 970 971 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 972 aspeed_set_fmc_model); 973 object_class_property_set_description(oc, "fmc-model", 974 "Change the FMC Flash model"); 975 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 976 aspeed_set_spi_model); 977 object_class_property_set_description(oc, "spi-model", 978 "Change the SPI Flash model"); 979 } 980 981 static int aspeed_soc_num_cpus(const char *soc_name) 982 { 983 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 984 return sc->num_cpus; 985 } 986 987 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 988 { 989 MachineClass *mc = MACHINE_CLASS(oc); 990 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 991 992 mc->init = aspeed_machine_init; 993 mc->no_floppy = 1; 994 mc->no_cdrom = 1; 995 mc->no_parallel = 1; 996 mc->default_ram_id = "ram"; 997 amc->macs_mask = ASPEED_MAC0_ON; 998 amc->uart_default = ASPEED_DEV_UART5; 999 1000 aspeed_machine_class_props_init(oc); 1001 } 1002 1003 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1004 { 1005 MachineClass *mc = MACHINE_CLASS(oc); 1006 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1007 1008 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1009 amc->soc_name = "ast2400-a1"; 1010 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1011 amc->fmc_model = "n25q256a"; 1012 amc->spi_model = "mx25l25635e"; 1013 amc->num_cs = 1; 1014 amc->i2c_init = palmetto_bmc_i2c_init; 1015 mc->default_ram_size = 256 * MiB; 1016 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1017 aspeed_soc_num_cpus(amc->soc_name); 1018 }; 1019 1020 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1021 { 1022 MachineClass *mc = MACHINE_CLASS(oc); 1023 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1024 1025 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1026 amc->soc_name = "ast2400-a1"; 1027 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1028 amc->fmc_model = "n25q256a"; 1029 amc->spi_model = "mx25l25635e"; 1030 amc->num_cs = 1; 1031 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1032 mc->default_ram_size = 128 * MiB; 1033 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1034 aspeed_soc_num_cpus(amc->soc_name); 1035 } 1036 1037 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1038 void *data) 1039 { 1040 MachineClass *mc = MACHINE_CLASS(oc); 1041 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1042 1043 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1044 amc->soc_name = "ast2400-a1"; 1045 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1046 amc->fmc_model = "mx25l25635e"; 1047 amc->spi_model = "mx25l25635e"; 1048 amc->num_cs = 1; 1049 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1050 amc->i2c_init = palmetto_bmc_i2c_init; 1051 mc->default_ram_size = 256 * MiB; 1052 } 1053 1054 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1055 { 1056 MachineClass *mc = MACHINE_CLASS(oc); 1057 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1058 1059 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1060 amc->soc_name = "ast2500-a1"; 1061 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1062 amc->fmc_model = "w25q256"; 1063 amc->spi_model = "mx25l25635e"; 1064 amc->num_cs = 1; 1065 amc->i2c_init = ast2500_evb_i2c_init; 1066 mc->default_ram_size = 512 * MiB; 1067 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1068 aspeed_soc_num_cpus(amc->soc_name); 1069 }; 1070 1071 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1072 { 1073 MachineClass *mc = MACHINE_CLASS(oc); 1074 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1075 1076 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1077 amc->soc_name = "ast2500-a1"; 1078 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1079 amc->fmc_model = "n25q256a"; 1080 amc->spi_model = "mx66l1g45g"; 1081 amc->num_cs = 2; 1082 amc->i2c_init = romulus_bmc_i2c_init; 1083 mc->default_ram_size = 512 * MiB; 1084 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1085 aspeed_soc_num_cpus(amc->soc_name); 1086 }; 1087 1088 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1089 { 1090 MachineClass *mc = MACHINE_CLASS(oc); 1091 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1092 1093 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1094 amc->soc_name = "ast2500-a1"; 1095 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1096 amc->fmc_model = "mx66l1g45g"; 1097 amc->spi_model = "mx66l1g45g"; 1098 amc->num_cs = 2; 1099 amc->i2c_init = sonorapass_bmc_i2c_init; 1100 mc->default_ram_size = 512 * MiB; 1101 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1102 aspeed_soc_num_cpus(amc->soc_name); 1103 }; 1104 1105 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) 1106 { 1107 MachineClass *mc = MACHINE_CLASS(oc); 1108 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1109 1110 mc->desc = "OpenPOWER Swift BMC (ARM1176)"; 1111 amc->soc_name = "ast2500-a1"; 1112 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1; 1113 amc->fmc_model = "mx66l1g45g"; 1114 amc->spi_model = "mx66l1g45g"; 1115 amc->num_cs = 2; 1116 amc->i2c_init = swift_bmc_i2c_init; 1117 mc->default_ram_size = 512 * MiB; 1118 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1119 aspeed_soc_num_cpus(amc->soc_name); 1120 1121 mc->deprecation_reason = "redundant system. Please use a similar " 1122 "OpenPOWER BMC, Witherspoon or Romulus."; 1123 }; 1124 1125 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1126 { 1127 MachineClass *mc = MACHINE_CLASS(oc); 1128 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1129 1130 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1131 amc->soc_name = "ast2500-a1"; 1132 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1133 amc->fmc_model = "mx25l25635e"; 1134 amc->spi_model = "mx66l1g45g"; 1135 amc->num_cs = 2; 1136 amc->i2c_init = witherspoon_bmc_i2c_init; 1137 mc->default_ram_size = 512 * MiB; 1138 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1139 aspeed_soc_num_cpus(amc->soc_name); 1140 }; 1141 1142 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1143 { 1144 MachineClass *mc = MACHINE_CLASS(oc); 1145 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1146 1147 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1148 amc->soc_name = "ast2600-a3"; 1149 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1150 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1151 amc->fmc_model = "w25q512jv"; 1152 amc->spi_model = "mx66u51235f"; 1153 amc->num_cs = 1; 1154 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1155 ASPEED_MAC3_ON; 1156 amc->i2c_init = ast2600_evb_i2c_init; 1157 mc->default_ram_size = 1 * GiB; 1158 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1159 aspeed_soc_num_cpus(amc->soc_name); 1160 }; 1161 1162 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1163 { 1164 MachineClass *mc = MACHINE_CLASS(oc); 1165 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1166 1167 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1168 amc->soc_name = "ast2600-a3"; 1169 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1170 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1171 amc->fmc_model = "mx66l1g45g"; 1172 amc->spi_model = "mx66l1g45g"; 1173 amc->num_cs = 2; 1174 amc->macs_mask = ASPEED_MAC2_ON; 1175 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1176 mc->default_ram_size = 1 * GiB; 1177 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1178 aspeed_soc_num_cpus(amc->soc_name); 1179 }; 1180 1181 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1182 { 1183 MachineClass *mc = MACHINE_CLASS(oc); 1184 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1185 1186 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1187 amc->soc_name = "ast2500-a1"; 1188 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1189 amc->fmc_model = "n25q512a"; 1190 amc->spi_model = "mx25l25635e"; 1191 amc->num_cs = 2; 1192 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1193 amc->i2c_init = g220a_bmc_i2c_init; 1194 mc->default_ram_size = 1024 * MiB; 1195 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1196 aspeed_soc_num_cpus(amc->soc_name); 1197 }; 1198 1199 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1200 { 1201 MachineClass *mc = MACHINE_CLASS(oc); 1202 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1203 1204 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1205 amc->soc_name = "ast2500-a1"; 1206 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1207 amc->fmc_model = "n25q512a"; 1208 amc->spi_model = "mx25l25635e"; 1209 amc->num_cs = 2; 1210 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1211 amc->i2c_init = fp5280g2_bmc_i2c_init; 1212 mc->default_ram_size = 512 * MiB; 1213 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1214 aspeed_soc_num_cpus(amc->soc_name); 1215 }; 1216 1217 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1218 { 1219 MachineClass *mc = MACHINE_CLASS(oc); 1220 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1221 1222 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1223 amc->soc_name = "ast2600-a3"; 1224 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1225 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1226 amc->fmc_model = "mx66l1g45g"; 1227 amc->spi_model = "mx66l1g45g"; 1228 amc->num_cs = 2; 1229 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1230 amc->i2c_init = rainier_bmc_i2c_init; 1231 mc->default_ram_size = 1 * GiB; 1232 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1233 aspeed_soc_num_cpus(amc->soc_name); 1234 }; 1235 1236 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 1237 #if HOST_LONG_BITS == 32 1238 #define FUJI_BMC_RAM_SIZE (1 * GiB) 1239 #else 1240 #define FUJI_BMC_RAM_SIZE (2 * GiB) 1241 #endif 1242 1243 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1244 { 1245 MachineClass *mc = MACHINE_CLASS(oc); 1246 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1247 1248 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1249 amc->soc_name = "ast2600-a3"; 1250 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1251 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1252 amc->fmc_model = "mx66l1g45g"; 1253 amc->spi_model = "mx66l1g45g"; 1254 amc->num_cs = 2; 1255 amc->macs_mask = ASPEED_MAC3_ON; 1256 amc->i2c_init = fuji_bmc_i2c_init; 1257 amc->uart_default = ASPEED_DEV_UART1; 1258 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1259 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1260 aspeed_soc_num_cpus(amc->soc_name); 1261 }; 1262 1263 static const TypeInfo aspeed_machine_types[] = { 1264 { 1265 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1266 .parent = TYPE_ASPEED_MACHINE, 1267 .class_init = aspeed_machine_palmetto_class_init, 1268 }, { 1269 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1270 .parent = TYPE_ASPEED_MACHINE, 1271 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1272 }, { 1273 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1274 .parent = TYPE_ASPEED_MACHINE, 1275 .class_init = aspeed_machine_ast2500_evb_class_init, 1276 }, { 1277 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1278 .parent = TYPE_ASPEED_MACHINE, 1279 .class_init = aspeed_machine_romulus_class_init, 1280 }, { 1281 .name = MACHINE_TYPE_NAME("swift-bmc"), 1282 .parent = TYPE_ASPEED_MACHINE, 1283 .class_init = aspeed_machine_swift_class_init, 1284 }, { 1285 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1286 .parent = TYPE_ASPEED_MACHINE, 1287 .class_init = aspeed_machine_sonorapass_class_init, 1288 }, { 1289 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1290 .parent = TYPE_ASPEED_MACHINE, 1291 .class_init = aspeed_machine_witherspoon_class_init, 1292 }, { 1293 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1294 .parent = TYPE_ASPEED_MACHINE, 1295 .class_init = aspeed_machine_ast2600_evb_class_init, 1296 }, { 1297 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1298 .parent = TYPE_ASPEED_MACHINE, 1299 .class_init = aspeed_machine_tacoma_class_init, 1300 }, { 1301 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1302 .parent = TYPE_ASPEED_MACHINE, 1303 .class_init = aspeed_machine_g220a_class_init, 1304 }, { 1305 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1306 .parent = TYPE_ASPEED_MACHINE, 1307 .class_init = aspeed_machine_fp5280g2_class_init, 1308 }, { 1309 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1310 .parent = TYPE_ASPEED_MACHINE, 1311 .class_init = aspeed_machine_quanta_q71l_class_init, 1312 }, { 1313 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1314 .parent = TYPE_ASPEED_MACHINE, 1315 .class_init = aspeed_machine_rainier_class_init, 1316 }, { 1317 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1318 .parent = TYPE_ASPEED_MACHINE, 1319 .class_init = aspeed_machine_fuji_class_init, 1320 }, { 1321 .name = TYPE_ASPEED_MACHINE, 1322 .parent = TYPE_MACHINE, 1323 .instance_size = sizeof(AspeedMachineState), 1324 .instance_init = aspeed_machine_instance_init, 1325 .class_size = sizeof(AspeedMachineClass), 1326 .class_init = aspeed_machine_class_init, 1327 .abstract = true, 1328 } 1329 }; 1330 1331 DEFINE_TYPES(aspeed_machine_types) 1332