1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "cpu.h" 15 #include "exec/address-spaces.h" 16 #include "hw/arm/boot.h" 17 #include "hw/arm/aspeed.h" 18 #include "hw/arm/aspeed_soc.h" 19 #include "hw/boards.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/misc/pca9552.h" 22 #include "hw/misc/tmp105.h" 23 #include "hw/qdev-properties.h" 24 #include "qemu/log.h" 25 #include "sysemu/block-backend.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/loader.h" 28 #include "qemu/error-report.h" 29 #include "qemu/units.h" 30 31 static struct arm_boot_info aspeed_board_binfo = { 32 .board_id = -1, /* device-tree-only board */ 33 }; 34 35 struct AspeedMachineState { 36 /* Private */ 37 MachineState parent_obj; 38 /* Public */ 39 40 AspeedSoCState soc; 41 MemoryRegion ram_container; 42 MemoryRegion max_ram; 43 bool mmio_exec; 44 }; 45 46 /* Palmetto hardware value: 0x120CE416 */ 47 #define PALMETTO_BMC_HW_STRAP1 ( \ 48 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 49 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 50 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 51 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 52 SCU_HW_STRAP_VGA_CLASS_CODE | \ 53 SCU_HW_STRAP_LPC_RESET_PIN | \ 54 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 55 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 56 SCU_HW_STRAP_SPI_WIDTH | \ 57 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 58 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 59 60 /* AST2500 evb hardware value: 0xF100C2E6 */ 61 #define AST2500_EVB_HW_STRAP1 (( \ 62 AST2500_HW_STRAP1_DEFAULTS | \ 63 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 64 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 65 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 66 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 67 SCU_HW_STRAP_MAC1_RGMII | \ 68 SCU_HW_STRAP_MAC0_RGMII) & \ 69 ~SCU_HW_STRAP_2ND_BOOT_WDT) 70 71 /* Romulus hardware value: 0xF10AD206 */ 72 #define ROMULUS_BMC_HW_STRAP1 ( \ 73 AST2500_HW_STRAP1_DEFAULTS | \ 74 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 75 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 76 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 77 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 78 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 79 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 80 81 /* Sonorapass hardware value: 0xF100D216 */ 82 #define SONORAPASS_BMC_HW_STRAP1 ( \ 83 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 84 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 85 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 86 SCU_AST2500_HW_STRAP_RESERVED28 | \ 87 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 88 SCU_HW_STRAP_VGA_CLASS_CODE | \ 89 SCU_HW_STRAP_LPC_RESET_PIN | \ 90 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 91 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 92 SCU_HW_STRAP_VGA_BIOS_ROM | \ 93 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 94 SCU_AST2500_HW_STRAP_RESERVED1) 95 96 /* Swift hardware value: 0xF11AD206 */ 97 #define SWIFT_BMC_HW_STRAP1 ( \ 98 AST2500_HW_STRAP1_DEFAULTS | \ 99 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 100 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 101 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 102 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 103 SCU_H_PLL_BYPASS_EN | \ 104 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 105 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 106 107 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 108 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 109 110 /* AST2600 evb hardware value */ 111 #define AST2600_EVB_HW_STRAP1 0x000000C0 112 #define AST2600_EVB_HW_STRAP2 0x00000003 113 114 /* Tacoma hardware value */ 115 #define TACOMA_BMC_HW_STRAP1 0x00000000 116 #define TACOMA_BMC_HW_STRAP2 0x00000040 117 118 /* 119 * The max ram region is for firmwares that scan the address space 120 * with load/store to guess how much RAM the SoC has. 121 */ 122 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 123 { 124 return 0; 125 } 126 127 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 128 unsigned size) 129 { 130 /* Discard writes */ 131 } 132 133 static const MemoryRegionOps max_ram_ops = { 134 .read = max_ram_read, 135 .write = max_ram_write, 136 .endianness = DEVICE_NATIVE_ENDIAN, 137 }; 138 139 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 140 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 141 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 142 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 143 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 144 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 145 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 146 147 static void aspeed_write_smpboot(ARMCPU *cpu, 148 const struct arm_boot_info *info) 149 { 150 static const uint32_t poll_mailbox_ready[] = { 151 /* 152 * r2 = per-cpu go sign value 153 * r1 = AST_SMP_MBOX_FIELD_ENTRY 154 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 155 */ 156 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 157 0xe21000ff, /* ands r0, r0, #255 */ 158 0xe59f201c, /* ldr r2, [pc, #28] */ 159 0xe1822000, /* orr r2, r2, r0 */ 160 161 0xe59f1018, /* ldr r1, [pc, #24] */ 162 0xe59f0018, /* ldr r0, [pc, #24] */ 163 164 0xe320f002, /* wfe */ 165 0xe5904000, /* ldr r4, [r0] */ 166 0xe1520004, /* cmp r2, r4 */ 167 0x1afffffb, /* bne <wfe> */ 168 0xe591f000, /* ldr pc, [r1] */ 169 AST_SMP_MBOX_GOSIGN, 170 AST_SMP_MBOX_FIELD_ENTRY, 171 AST_SMP_MBOX_FIELD_GOSIGN, 172 }; 173 174 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 175 sizeof(poll_mailbox_ready), 176 info->smp_loader_start); 177 } 178 179 static void aspeed_reset_secondary(ARMCPU *cpu, 180 const struct arm_boot_info *info) 181 { 182 AddressSpace *as = arm_boot_address_space(cpu, info); 183 CPUState *cs = CPU(cpu); 184 185 /* info->smp_bootreg_addr */ 186 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 187 MEMTXATTRS_UNSPECIFIED, NULL); 188 cpu_set_pc(cs, info->smp_loader_start); 189 } 190 191 #define FIRMWARE_ADDR 0x0 192 193 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 194 Error **errp) 195 { 196 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 197 uint8_t *storage; 198 int64_t size; 199 200 /* The block backend size should have already been 'validated' by 201 * the creation of the m25p80 object. 202 */ 203 size = blk_getlength(blk); 204 if (size <= 0) { 205 error_setg(errp, "failed to get flash size"); 206 return; 207 } 208 209 if (rom_size > size) { 210 rom_size = size; 211 } 212 213 storage = g_new0(uint8_t, rom_size); 214 if (blk_pread(blk, 0, storage, rom_size) < 0) { 215 error_setg(errp, "failed to read the initial flash content"); 216 return; 217 } 218 219 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 220 g_free(storage); 221 } 222 223 static void aspeed_board_init_flashes(AspeedSMCState *s, 224 const char *flashtype) 225 { 226 int i ; 227 228 for (i = 0; i < s->num_cs; ++i) { 229 AspeedSMCFlash *fl = &s->flashes[i]; 230 DriveInfo *dinfo = drive_get_next(IF_MTD); 231 qemu_irq cs_line; 232 233 fl->flash = qdev_new(flashtype); 234 if (dinfo) { 235 qdev_prop_set_drive(fl->flash, "drive", 236 blk_by_legacy_dinfo(dinfo)); 237 } 238 qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal); 239 240 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); 241 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 242 } 243 } 244 245 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 246 { 247 DeviceState *card; 248 249 if (!dinfo) { 250 return; 251 } 252 card = qdev_new(TYPE_SD_CARD); 253 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 254 &error_fatal); 255 qdev_realize_and_unref(card, 256 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 257 &error_fatal); 258 } 259 260 static void aspeed_machine_init(MachineState *machine) 261 { 262 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 263 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 264 AspeedSoCClass *sc; 265 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 266 ram_addr_t max_ram_size; 267 int i; 268 NICInfo *nd = &nd_table[0]; 269 270 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 271 4 * GiB); 272 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 273 274 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 275 276 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 277 278 /* 279 * This will error out if isize is not supported by memory controller. 280 */ 281 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", ram_size, 282 &error_fatal); 283 284 for (i = 0; i < sc->macs_num; i++) { 285 if ((amc->macs_mask & (1 << i)) && nd->used) { 286 qemu_check_nic_model(nd, TYPE_FTGMAC100); 287 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 288 nd++; 289 } 290 } 291 292 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 293 &error_abort); 294 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 295 &error_abort); 296 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs, 297 &error_abort); 298 object_property_set_link(OBJECT(&bmc->soc), "dram", 299 OBJECT(&bmc->ram_container), &error_abort); 300 if (machine->kernel_filename) { 301 /* 302 * When booting with a -kernel command line there is no u-boot 303 * that runs to unlock the SCU. In this case set the default to 304 * be unlocked as the kernel expects 305 */ 306 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 307 ASPEED_SCU_PROT_KEY, &error_abort); 308 } 309 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 310 311 memory_region_add_subregion(get_system_memory(), 312 sc->memmap[ASPEED_SDRAM], 313 &bmc->ram_container); 314 315 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 316 &error_abort); 317 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 318 "max_ram", max_ram_size - ram_size); 319 memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram); 320 321 aspeed_board_init_flashes(&bmc->soc.fmc, amc->fmc_model); 322 aspeed_board_init_flashes(&bmc->soc.spi[0], amc->spi_model); 323 324 /* Install first FMC flash content as a boot rom. */ 325 if (drive0) { 326 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 327 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 328 329 /* 330 * create a ROM region using the default mapping window size of 331 * the flash module. The window size is 64MB for the AST2400 332 * SoC and 128MB for the AST2500 SoC, which is twice as big as 333 * needed by the flash modules of the Aspeed machines. 334 */ 335 if (ASPEED_MACHINE(machine)->mmio_exec) { 336 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", 337 &fl->mmio, 0, fl->size); 338 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 339 boot_rom); 340 } else { 341 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", 342 fl->size, &error_abort); 343 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 344 boot_rom); 345 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); 346 } 347 } 348 349 if (machine->kernel_filename && sc->num_cpus > 1) { 350 /* With no u-boot we must set up a boot stub for the secondary CPU */ 351 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 352 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 353 0x80, &error_abort); 354 memory_region_add_subregion(get_system_memory(), 355 AST_SMP_MAILBOX_BASE, smpboot); 356 357 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 358 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 359 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 360 } 361 362 aspeed_board_binfo.ram_size = ram_size; 363 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM]; 364 aspeed_board_binfo.nb_cpus = sc->num_cpus; 365 366 if (amc->i2c_init) { 367 amc->i2c_init(bmc); 368 } 369 370 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 371 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); 372 } 373 374 if (bmc->soc.emmc.num_slots) { 375 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); 376 } 377 378 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 379 } 380 381 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 382 { 383 AspeedSoCState *soc = &bmc->soc; 384 DeviceState *dev; 385 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 386 387 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 388 * enough to provide basic RTC features. Alarms will be missing */ 389 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 390 391 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 392 eeprom_buf); 393 394 /* add a TMP423 temperature sensor */ 395 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 396 "tmp423", 0x4c)); 397 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 398 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 399 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 400 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 401 } 402 403 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 404 { 405 AspeedSoCState *soc = &bmc->soc; 406 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 407 408 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 409 eeprom_buf); 410 411 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 412 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 413 TYPE_TMP105, 0x4d); 414 415 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 416 * plugged on the I2C bus header */ 417 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 418 } 419 420 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 421 { 422 /* Start with some devices on our I2C busses */ 423 ast2500_evb_i2c_init(bmc); 424 } 425 426 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 427 { 428 AspeedSoCState *soc = &bmc->soc; 429 430 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 431 * good enough */ 432 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 433 } 434 435 static void swift_bmc_i2c_init(AspeedMachineState *bmc) 436 { 437 AspeedSoCState *soc = &bmc->soc; 438 439 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60); 440 441 /* The swift board expects a TMP275 but a TMP105 is compatible */ 442 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48); 443 /* The swift board expects a pca9551 but a pca9552 is compatible */ 444 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60); 445 446 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ 447 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32); 448 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 449 450 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 451 /* The swift board expects a pca9539 but a pca9552 is compatible */ 452 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74); 453 454 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 455 /* The swift board expects a pca9539 but a pca9552 is compatible */ 456 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552", 457 0x74); 458 459 /* The swift board expects a TMP275 but a TMP105 is compatible */ 460 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48); 461 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a); 462 } 463 464 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 465 { 466 AspeedSoCState *soc = &bmc->soc; 467 468 /* bus 2 : */ 469 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 470 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 471 /* bus 2 : pca9546 @ 0x73 */ 472 473 /* bus 3 : pca9548 @ 0x70 */ 474 475 /* bus 4 : */ 476 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 477 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 478 eeprom4_54); 479 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 480 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76); 481 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 482 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77); 483 484 /* bus 6 : */ 485 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 486 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 487 /* bus 6 : pca9546 @ 0x73 */ 488 489 /* bus 8 : */ 490 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 491 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 492 eeprom8_56); 493 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 494 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); 495 /* bus 8 : adc128d818 @ 0x1d */ 496 /* bus 8 : adc128d818 @ 0x1f */ 497 498 /* 499 * bus 13 : pca9548 @ 0x71 500 * - channel 3: 501 * - tmm421 @ 0x4c 502 * - tmp421 @ 0x4e 503 * - tmp421 @ 0x4f 504 */ 505 506 } 507 508 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 509 { 510 AspeedSoCState *soc = &bmc->soc; 511 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 512 DeviceState *dev; 513 514 /* Bus 3: TODO bmp280@77 */ 515 /* Bus 3: TODO max31785@52 */ 516 /* Bus 3: TODO dps310@76 */ 517 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 518 qdev_prop_set_string(dev, "description", "pca1"); 519 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 520 aspeed_i2c_get_bus(&soc->i2c, 3), 521 &error_fatal); 522 523 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 524 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 525 526 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 527 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 528 0x4a); 529 530 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 531 * good enough */ 532 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 533 534 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 535 eeprom_buf); 536 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 537 qdev_prop_set_string(dev, "description", "pca0"); 538 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 539 aspeed_i2c_get_bus(&soc->i2c, 11), 540 &error_fatal); 541 /* Bus 11: TODO ucd90160@64 */ 542 } 543 544 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 545 { 546 return ASPEED_MACHINE(obj)->mmio_exec; 547 } 548 549 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 550 { 551 ASPEED_MACHINE(obj)->mmio_exec = value; 552 } 553 554 static void aspeed_machine_instance_init(Object *obj) 555 { 556 ASPEED_MACHINE(obj)->mmio_exec = false; 557 } 558 559 static void aspeed_machine_class_props_init(ObjectClass *oc) 560 { 561 object_class_property_add_bool(oc, "execute-in-place", 562 aspeed_get_mmio_exec, 563 aspeed_set_mmio_exec); 564 object_class_property_set_description(oc, "execute-in-place", 565 "boot directly from CE0 flash device"); 566 } 567 568 static int aspeed_soc_num_cpus(const char *soc_name) 569 { 570 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 571 return sc->num_cpus; 572 } 573 574 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 575 { 576 MachineClass *mc = MACHINE_CLASS(oc); 577 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 578 579 mc->init = aspeed_machine_init; 580 mc->no_floppy = 1; 581 mc->no_cdrom = 1; 582 mc->no_parallel = 1; 583 mc->default_ram_id = "ram"; 584 amc->macs_mask = ASPEED_MAC0_ON; 585 586 aspeed_machine_class_props_init(oc); 587 } 588 589 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 590 { 591 MachineClass *mc = MACHINE_CLASS(oc); 592 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 593 594 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 595 amc->soc_name = "ast2400-a1"; 596 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 597 amc->fmc_model = "n25q256a"; 598 amc->spi_model = "mx25l25635e"; 599 amc->num_cs = 1; 600 amc->i2c_init = palmetto_bmc_i2c_init; 601 mc->default_ram_size = 256 * MiB; 602 mc->default_cpus = mc->min_cpus = mc->max_cpus = 603 aspeed_soc_num_cpus(amc->soc_name); 604 }; 605 606 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 607 { 608 MachineClass *mc = MACHINE_CLASS(oc); 609 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 610 611 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 612 amc->soc_name = "ast2500-a1"; 613 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 614 amc->fmc_model = "w25q256"; 615 amc->spi_model = "mx25l25635e"; 616 amc->num_cs = 1; 617 amc->i2c_init = ast2500_evb_i2c_init; 618 mc->default_ram_size = 512 * MiB; 619 mc->default_cpus = mc->min_cpus = mc->max_cpus = 620 aspeed_soc_num_cpus(amc->soc_name); 621 }; 622 623 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 624 { 625 MachineClass *mc = MACHINE_CLASS(oc); 626 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 627 628 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 629 amc->soc_name = "ast2500-a1"; 630 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 631 amc->fmc_model = "n25q256a"; 632 amc->spi_model = "mx66l1g45g"; 633 amc->num_cs = 2; 634 amc->i2c_init = romulus_bmc_i2c_init; 635 mc->default_ram_size = 512 * MiB; 636 mc->default_cpus = mc->min_cpus = mc->max_cpus = 637 aspeed_soc_num_cpus(amc->soc_name); 638 }; 639 640 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 641 { 642 MachineClass *mc = MACHINE_CLASS(oc); 643 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 644 645 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 646 amc->soc_name = "ast2500-a1"; 647 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 648 amc->fmc_model = "mx66l1g45g"; 649 amc->spi_model = "mx66l1g45g"; 650 amc->num_cs = 2; 651 amc->i2c_init = sonorapass_bmc_i2c_init; 652 mc->default_ram_size = 512 * MiB; 653 mc->default_cpus = mc->min_cpus = mc->max_cpus = 654 aspeed_soc_num_cpus(amc->soc_name); 655 }; 656 657 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) 658 { 659 MachineClass *mc = MACHINE_CLASS(oc); 660 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 661 662 mc->desc = "OpenPOWER Swift BMC (ARM1176)"; 663 amc->soc_name = "ast2500-a1"; 664 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1; 665 amc->fmc_model = "mx66l1g45g"; 666 amc->spi_model = "mx66l1g45g"; 667 amc->num_cs = 2; 668 amc->i2c_init = swift_bmc_i2c_init; 669 mc->default_ram_size = 512 * MiB; 670 mc->default_cpus = mc->min_cpus = mc->max_cpus = 671 aspeed_soc_num_cpus(amc->soc_name); 672 }; 673 674 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 675 { 676 MachineClass *mc = MACHINE_CLASS(oc); 677 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 678 679 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 680 amc->soc_name = "ast2500-a1"; 681 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 682 amc->fmc_model = "mx25l25635e"; 683 amc->spi_model = "mx66l1g45g"; 684 amc->num_cs = 2; 685 amc->i2c_init = witherspoon_bmc_i2c_init; 686 mc->default_ram_size = 512 * MiB; 687 mc->default_cpus = mc->min_cpus = mc->max_cpus = 688 aspeed_soc_num_cpus(amc->soc_name); 689 }; 690 691 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 692 { 693 MachineClass *mc = MACHINE_CLASS(oc); 694 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 695 696 mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; 697 amc->soc_name = "ast2600-a1"; 698 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 699 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 700 amc->fmc_model = "w25q512jv"; 701 amc->spi_model = "mx66u51235f"; 702 amc->num_cs = 1; 703 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON; 704 amc->i2c_init = ast2600_evb_i2c_init; 705 mc->default_ram_size = 1 * GiB; 706 mc->default_cpus = mc->min_cpus = mc->max_cpus = 707 aspeed_soc_num_cpus(amc->soc_name); 708 }; 709 710 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 711 { 712 MachineClass *mc = MACHINE_CLASS(oc); 713 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 714 715 mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)"; 716 amc->soc_name = "ast2600-a1"; 717 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 718 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 719 amc->fmc_model = "mx66l1g45g"; 720 amc->spi_model = "mx66l1g45g"; 721 amc->num_cs = 2; 722 amc->macs_mask = ASPEED_MAC2_ON; 723 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 724 mc->default_ram_size = 1 * GiB; 725 mc->default_cpus = mc->min_cpus = mc->max_cpus = 726 aspeed_soc_num_cpus(amc->soc_name); 727 }; 728 729 static const TypeInfo aspeed_machine_types[] = { 730 { 731 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 732 .parent = TYPE_ASPEED_MACHINE, 733 .class_init = aspeed_machine_palmetto_class_init, 734 }, { 735 .name = MACHINE_TYPE_NAME("ast2500-evb"), 736 .parent = TYPE_ASPEED_MACHINE, 737 .class_init = aspeed_machine_ast2500_evb_class_init, 738 }, { 739 .name = MACHINE_TYPE_NAME("romulus-bmc"), 740 .parent = TYPE_ASPEED_MACHINE, 741 .class_init = aspeed_machine_romulus_class_init, 742 }, { 743 .name = MACHINE_TYPE_NAME("swift-bmc"), 744 .parent = TYPE_ASPEED_MACHINE, 745 .class_init = aspeed_machine_swift_class_init, 746 }, { 747 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 748 .parent = TYPE_ASPEED_MACHINE, 749 .class_init = aspeed_machine_sonorapass_class_init, 750 }, { 751 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 752 .parent = TYPE_ASPEED_MACHINE, 753 .class_init = aspeed_machine_witherspoon_class_init, 754 }, { 755 .name = MACHINE_TYPE_NAME("ast2600-evb"), 756 .parent = TYPE_ASPEED_MACHINE, 757 .class_init = aspeed_machine_ast2600_evb_class_init, 758 }, { 759 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 760 .parent = TYPE_ASPEED_MACHINE, 761 .class_init = aspeed_machine_tacoma_class_init, 762 }, { 763 .name = TYPE_ASPEED_MACHINE, 764 .parent = TYPE_MACHINE, 765 .instance_size = sizeof(AspeedMachineState), 766 .instance_init = aspeed_machine_instance_init, 767 .class_size = sizeof(AspeedMachineClass), 768 .class_init = aspeed_machine_class_init, 769 .abstract = true, 770 } 771 }; 772 773 DEFINE_TYPES(aspeed_machine_types) 774