1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/block/flash.h" 19 #include "hw/i2c/i2c_mux_pca954x.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/gpio/pca9552.h" 22 #include "hw/nvram/eeprom_at24c.h" 23 #include "hw/sensor/tmp105.h" 24 #include "hw/misc/led.h" 25 #include "hw/qdev-properties.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/reset.h" 28 #include "hw/loader.h" 29 #include "qemu/error-report.h" 30 #include "qemu/units.h" 31 #include "hw/qdev-clock.h" 32 #include "sysemu/sysemu.h" 33 34 static struct arm_boot_info aspeed_board_binfo = { 35 .board_id = -1, /* device-tree-only board */ 36 }; 37 38 struct AspeedMachineState { 39 /* Private */ 40 MachineState parent_obj; 41 /* Public */ 42 43 AspeedSoCState *soc; 44 MemoryRegion boot_rom; 45 bool mmio_exec; 46 uint32_t uart_chosen; 47 char *fmc_model; 48 char *spi_model; 49 uint32_t hw_strap1; 50 }; 51 52 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 53 #if HOST_LONG_BITS == 32 54 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) 55 #else 56 #define ASPEED_RAM_SIZE(sz) (sz) 57 #endif 58 59 /* Palmetto hardware value: 0x120CE416 */ 60 #define PALMETTO_BMC_HW_STRAP1 ( \ 61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 63 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 65 SCU_HW_STRAP_VGA_CLASS_CODE | \ 66 SCU_HW_STRAP_LPC_RESET_PIN | \ 67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 69 SCU_HW_STRAP_SPI_WIDTH | \ 70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 72 73 /* TODO: Find the actual hardware value */ 74 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 75 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 76 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 77 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 78 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 79 SCU_HW_STRAP_VGA_CLASS_CODE | \ 80 SCU_HW_STRAP_LPC_RESET_PIN | \ 81 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 82 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 83 SCU_HW_STRAP_SPI_WIDTH | \ 84 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 85 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 86 87 /* TODO: Find the actual hardware value */ 88 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 89 AST2500_HW_STRAP1_DEFAULTS | \ 90 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 91 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 92 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 93 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 94 SCU_HW_STRAP_SPI_WIDTH | \ 95 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 96 97 /* AST2500 evb hardware value: 0xF100C2E6 */ 98 #define AST2500_EVB_HW_STRAP1 (( \ 99 AST2500_HW_STRAP1_DEFAULTS | \ 100 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 101 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 102 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 103 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 104 SCU_HW_STRAP_MAC1_RGMII | \ 105 SCU_HW_STRAP_MAC0_RGMII) & \ 106 ~SCU_HW_STRAP_2ND_BOOT_WDT) 107 108 /* Romulus hardware value: 0xF10AD206 */ 109 #define ROMULUS_BMC_HW_STRAP1 ( \ 110 AST2500_HW_STRAP1_DEFAULTS | \ 111 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 112 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 113 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 114 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 115 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 116 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 117 118 /* Sonorapass hardware value: 0xF100D216 */ 119 #define SONORAPASS_BMC_HW_STRAP1 ( \ 120 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 121 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 122 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 123 SCU_AST2500_HW_STRAP_RESERVED28 | \ 124 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 125 SCU_HW_STRAP_VGA_CLASS_CODE | \ 126 SCU_HW_STRAP_LPC_RESET_PIN | \ 127 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 128 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 129 SCU_HW_STRAP_VGA_BIOS_ROM | \ 130 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 131 SCU_AST2500_HW_STRAP_RESERVED1) 132 133 #define G220A_BMC_HW_STRAP1 ( \ 134 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 135 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 136 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 137 SCU_AST2500_HW_STRAP_RESERVED28 | \ 138 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 139 SCU_HW_STRAP_2ND_BOOT_WDT | \ 140 SCU_HW_STRAP_VGA_CLASS_CODE | \ 141 SCU_HW_STRAP_LPC_RESET_PIN | \ 142 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 143 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 144 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 145 SCU_AST2500_HW_STRAP_RESERVED1) 146 147 /* FP5280G2 hardware value: 0XF100D286 */ 148 #define FP5280G2_BMC_HW_STRAP1 ( \ 149 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 150 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 151 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 152 SCU_AST2500_HW_STRAP_RESERVED28 | \ 153 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 154 SCU_HW_STRAP_VGA_CLASS_CODE | \ 155 SCU_HW_STRAP_LPC_RESET_PIN | \ 156 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 157 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 158 SCU_HW_STRAP_MAC1_RGMII | \ 159 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 160 SCU_AST2500_HW_STRAP_RESERVED1) 161 162 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 163 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 164 165 /* Quanta-Q71l hardware value */ 166 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 167 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 168 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 169 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 170 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 171 SCU_HW_STRAP_VGA_CLASS_CODE | \ 172 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 173 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 174 SCU_HW_STRAP_SPI_WIDTH | \ 175 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 176 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 177 178 /* AST2600 evb hardware value */ 179 #define AST2600_EVB_HW_STRAP1 0x000000C0 180 #define AST2600_EVB_HW_STRAP2 0x00000003 181 182 #ifdef TARGET_AARCH64 183 /* AST2700 evb hardware value */ 184 #define AST2700_EVB_HW_STRAP1 0x000000C0 185 #define AST2700_EVB_HW_STRAP2 0x00000003 186 #endif 187 188 /* Rainier hardware value: (QEMU prototype) */ 189 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) 190 #define RAINIER_BMC_HW_STRAP2 0x80000848 191 192 /* Fuji hardware value */ 193 #define FUJI_BMC_HW_STRAP1 0x00000000 194 #define FUJI_BMC_HW_STRAP2 0x00000000 195 196 /* Bletchley hardware value */ 197 /* TODO: Leave same as EVB for now. */ 198 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 199 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 200 201 /* Qualcomm DC-SCM hardware value */ 202 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 203 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 204 205 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 206 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 207 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 208 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 209 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 210 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 211 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 212 213 static void aspeed_write_smpboot(ARMCPU *cpu, 214 const struct arm_boot_info *info) 215 { 216 AddressSpace *as = arm_boot_address_space(cpu, info); 217 static const ARMInsnFixup poll_mailbox_ready[] = { 218 /* 219 * r2 = per-cpu go sign value 220 * r1 = AST_SMP_MBOX_FIELD_ENTRY 221 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 222 */ 223 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 224 { 0xe21000ff }, /* ands r0, r0, #255 */ 225 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 226 { 0xe1822000 }, /* orr r2, r2, r0 */ 227 228 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 229 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 230 231 { 0xe320f002 }, /* wfe */ 232 { 0xe5904000 }, /* ldr r4, [r0] */ 233 { 0xe1520004 }, /* cmp r2, r4 */ 234 { 0x1afffffb }, /* bne <wfe> */ 235 { 0xe591f000 }, /* ldr pc, [r1] */ 236 { AST_SMP_MBOX_GOSIGN }, 237 { AST_SMP_MBOX_FIELD_ENTRY }, 238 { AST_SMP_MBOX_FIELD_GOSIGN }, 239 { 0, FIXUP_TERMINATOR } 240 }; 241 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 242 243 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 244 poll_mailbox_ready, fixupcontext); 245 } 246 247 static void aspeed_reset_secondary(ARMCPU *cpu, 248 const struct arm_boot_info *info) 249 { 250 AddressSpace *as = arm_boot_address_space(cpu, info); 251 CPUState *cs = CPU(cpu); 252 253 /* info->smp_bootreg_addr */ 254 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 255 MEMTXATTRS_UNSPECIFIED, NULL); 256 cpu_set_pc(cs, info->smp_loader_start); 257 } 258 259 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 260 Error **errp) 261 { 262 g_autofree void *storage = NULL; 263 int64_t size; 264 265 /* 266 * The block backend size should have already been 'validated' by 267 * the creation of the m25p80 object. 268 */ 269 size = blk_getlength(blk); 270 if (size <= 0) { 271 error_setg(errp, "failed to get flash size"); 272 return; 273 } 274 275 if (rom_size > size) { 276 rom_size = size; 277 } 278 279 storage = g_malloc0(rom_size); 280 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 281 error_setg(errp, "failed to read the initial flash content"); 282 return; 283 } 284 285 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 286 } 287 288 /* 289 * Create a ROM and copy the flash contents at the expected address 290 * (0x0). Boots faster than execute-in-place. 291 */ 292 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 293 uint64_t rom_size) 294 { 295 AspeedSoCState *soc = bmc->soc; 296 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); 297 298 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 299 &error_abort); 300 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 301 &bmc->boot_rom, 1); 302 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], 303 rom_size, &error_abort); 304 } 305 306 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 307 unsigned int count, int unit0) 308 { 309 int i; 310 311 if (!flashtype) { 312 return; 313 } 314 315 for (i = 0; i < count; ++i) { 316 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 317 DeviceState *dev; 318 319 dev = qdev_new(flashtype); 320 if (dinfo) { 321 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 322 } 323 qdev_prop_set_uint8(dev, "cs", i); 324 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 325 } 326 } 327 328 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc, 329 bool boot_emmc) 330 { 331 DeviceState *card; 332 333 if (!dinfo) { 334 return; 335 } 336 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); 337 338 /* 339 * Force the boot properties of the eMMC device only when the 340 * machine is strapped to boot from eMMC. Without these 341 * settings, the machine would not boot. 342 * 343 * This also allows the machine to use an eMMC device without 344 * boot areas when booting from the flash device (or -kernel) 345 * Ideally, the device and its properties should be defined on 346 * the command line. 347 */ 348 if (emmc && boot_emmc) { 349 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB); 350 qdev_prop_set_uint8(card, "boot-config", 0x1 << 3); 351 } 352 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 353 &error_fatal); 354 qdev_realize_and_unref(card, 355 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 356 &error_fatal); 357 } 358 359 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 360 { 361 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 362 AspeedSoCState *s = bmc->soc; 363 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 364 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 365 366 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 367 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) { 368 if (uart == uart_chosen) { 369 continue; 370 } 371 aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); 372 } 373 } 374 375 static void aspeed_machine_init(MachineState *machine) 376 { 377 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 378 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 379 AspeedSoCClass *sc; 380 int i; 381 DriveInfo *emmc0 = NULL; 382 bool boot_emmc; 383 384 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 385 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 386 object_unref(OBJECT(bmc->soc)); 387 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 388 389 /* 390 * This will error out if the RAM size is not supported by the 391 * memory controller of the SoC. 392 */ 393 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 394 &error_fatal); 395 396 for (i = 0; i < sc->macs_num; i++) { 397 if ((amc->macs_mask & (1 << i)) && 398 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), 399 true, NULL)) { 400 break; /* No configs left; stop asking */ 401 } 402 } 403 404 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1, 405 &error_abort); 406 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 407 &error_abort); 408 object_property_set_link(OBJECT(bmc->soc), "memory", 409 OBJECT(get_system_memory()), &error_abort); 410 object_property_set_link(OBJECT(bmc->soc), "dram", 411 OBJECT(machine->ram), &error_abort); 412 if (amc->sdhci_wp_inverted) { 413 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 414 object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), 415 "wp-inverted", true, &error_abort); 416 } 417 } 418 if (machine->kernel_filename) { 419 /* 420 * When booting with a -kernel command line there is no u-boot 421 * that runs to unlock the SCU. In this case set the default to 422 * be unlocked as the kernel expects 423 */ 424 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 425 ASPEED_SCU_PROT_KEY, &error_abort); 426 } 427 connect_serial_hds_to_uarts(bmc); 428 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 429 430 if (defaults_enabled()) { 431 aspeed_board_init_flashes(&bmc->soc->fmc, 432 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 433 amc->num_cs, 0); 434 aspeed_board_init_flashes(&bmc->soc->spi[0], 435 bmc->spi_model ? bmc->spi_model : amc->spi_model, 436 1, amc->num_cs); 437 } 438 439 if (machine->kernel_filename && sc->num_cpus > 1) { 440 /* With no u-boot we must set up a boot stub for the secondary CPU */ 441 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 442 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 443 0x80, &error_abort); 444 memory_region_add_subregion(get_system_memory(), 445 AST_SMP_MAILBOX_BASE, smpboot); 446 447 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 448 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 449 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 450 } 451 452 aspeed_board_binfo.ram_size = machine->ram_size; 453 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 454 455 if (amc->i2c_init) { 456 amc->i2c_init(bmc); 457 } 458 459 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 460 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 461 drive_get(IF_SD, 0, i), false, false); 462 } 463 464 boot_emmc = sc->boot_from_emmc(bmc->soc); 465 466 if (bmc->soc->emmc.num_slots) { 467 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); 468 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc); 469 } 470 471 if (!bmc->mmio_exec) { 472 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 473 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 474 475 if (fmc0 && !boot_emmc) { 476 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 477 aspeed_install_boot_rom(bmc, fmc0, rom_size); 478 } else if (emmc0) { 479 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB); 480 } 481 } 482 483 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 484 } 485 486 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 487 { 488 AspeedSoCState *soc = bmc->soc; 489 DeviceState *dev; 490 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 491 492 /* 493 * The palmetto platform expects a ds3231 RTC but a ds1338 is 494 * enough to provide basic RTC features. Alarms will be missing 495 */ 496 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 497 498 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 499 eeprom_buf); 500 501 /* add a TMP423 temperature sensor */ 502 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 503 "tmp423", 0x4c)); 504 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 505 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 506 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 507 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 508 } 509 510 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 511 { 512 AspeedSoCState *soc = bmc->soc; 513 514 /* 515 * The quanta-q71l platform expects tmp75s which are compatible with 516 * tmp105s. 517 */ 518 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 519 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 520 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 521 522 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 523 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 524 /* TODO: Add Memory Riser i2c mux and eeproms. */ 525 526 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 527 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 528 529 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 530 531 /* i2c-7 */ 532 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 533 /* - i2c@0: pmbus@59 */ 534 /* - i2c@1: pmbus@58 */ 535 /* - i2c@2: pmbus@58 */ 536 /* - i2c@3: pmbus@59 */ 537 538 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 539 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 540 } 541 542 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 543 { 544 AspeedSoCState *soc = bmc->soc; 545 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 546 547 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 548 eeprom_buf); 549 550 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 551 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 552 TYPE_TMP105, 0x4d); 553 } 554 555 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 556 { 557 AspeedSoCState *soc = bmc->soc; 558 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 559 560 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 561 eeprom_buf); 562 563 /* LM75 is compatible with TMP105 driver */ 564 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 565 TYPE_TMP105, 0x4d); 566 } 567 568 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 569 { 570 AspeedSoCState *soc = bmc->soc; 571 572 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 573 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 574 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 575 /* TMP421 */ 576 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 577 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 578 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 579 580 } 581 582 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 583 { 584 AspeedSoCState *soc = bmc->soc; 585 586 /* 587 * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 588 * good enough 589 */ 590 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 591 } 592 593 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 594 { 595 AspeedSoCState *soc = bmc->soc; 596 597 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 598 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 599 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 600 /* TMP421 */ 601 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 602 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 603 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 604 } 605 606 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 607 { 608 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 609 TYPE_PCA9552, addr); 610 } 611 612 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 613 { 614 AspeedSoCState *soc = bmc->soc; 615 616 /* bus 2 : */ 617 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 618 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 619 /* bus 2 : pca9546 @ 0x73 */ 620 621 /* bus 3 : pca9548 @ 0x70 */ 622 623 /* bus 4 : */ 624 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 625 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 626 eeprom4_54); 627 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 628 create_pca9552(soc, 4, 0x76); 629 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 630 create_pca9552(soc, 4, 0x77); 631 632 /* bus 6 : */ 633 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 634 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 635 /* bus 6 : pca9546 @ 0x73 */ 636 637 /* bus 8 : */ 638 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 639 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 640 eeprom8_56); 641 create_pca9552(soc, 8, 0x60); 642 create_pca9552(soc, 8, 0x61); 643 /* bus 8 : adc128d818 @ 0x1d */ 644 /* bus 8 : adc128d818 @ 0x1f */ 645 646 /* 647 * bus 13 : pca9548 @ 0x71 648 * - channel 3: 649 * - tmm421 @ 0x4c 650 * - tmp421 @ 0x4e 651 * - tmp421 @ 0x4f 652 */ 653 654 } 655 656 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 657 { 658 static const struct { 659 unsigned gpio_id; 660 LEDColor color; 661 const char *description; 662 bool gpio_polarity; 663 } pca1_leds[] = { 664 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 665 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 666 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 667 }; 668 AspeedSoCState *soc = bmc->soc; 669 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 670 DeviceState *dev; 671 LEDState *led; 672 673 /* Bus 3: TODO bmp280@77 */ 674 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 675 qdev_prop_set_string(dev, "description", "pca1"); 676 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 677 aspeed_i2c_get_bus(&soc->i2c, 3), 678 &error_fatal); 679 680 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 681 led = led_create_simple(OBJECT(bmc), 682 pca1_leds[i].gpio_polarity, 683 pca1_leds[i].color, 684 pca1_leds[i].description); 685 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 686 qdev_get_gpio_in(DEVICE(led), 0)); 687 } 688 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 689 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 690 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 691 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 692 693 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 694 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 695 0x4a); 696 697 /* 698 * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 699 * good enough 700 */ 701 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 702 703 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 704 eeprom_buf); 705 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 706 qdev_prop_set_string(dev, "description", "pca0"); 707 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 708 aspeed_i2c_get_bus(&soc->i2c, 11), 709 &error_fatal); 710 /* Bus 11: TODO ucd90160@64 */ 711 } 712 713 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 714 { 715 AspeedSoCState *soc = bmc->soc; 716 DeviceState *dev; 717 718 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 719 "emc1413", 0x4c)); 720 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 721 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 722 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 723 724 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 725 "emc1413", 0x4c)); 726 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 727 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 728 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 729 730 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 731 "emc1413", 0x4c)); 732 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 733 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 734 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 735 736 static uint8_t eeprom_buf[2 * 1024] = { 737 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 738 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 739 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 740 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 741 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 742 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 743 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 744 }; 745 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 746 eeprom_buf); 747 } 748 749 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 750 { 751 AspeedSoCState *soc = bmc->soc; 752 I2CSlave *i2c_mux; 753 754 /* The at24c256 */ 755 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 756 757 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 758 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 759 0x48); 760 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 761 0x49); 762 763 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 764 "pca9546", 0x70); 765 /* It expects a TMP112 but a TMP105 is compatible */ 766 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 767 0x4a); 768 769 /* It expects a ds3232 but a ds1338 is good enough */ 770 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 771 772 /* It expects a pca9555 but a pca9552 is compatible */ 773 create_pca9552(soc, 8, 0x30); 774 } 775 776 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 777 { 778 AspeedSoCState *soc = bmc->soc; 779 I2CSlave *i2c_mux; 780 781 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 782 783 create_pca9552(soc, 3, 0x61); 784 785 /* The rainier expects a TMP275 but a TMP105 is compatible */ 786 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 787 0x48); 788 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 789 0x49); 790 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 791 0x4a); 792 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 793 "pca9546", 0x70); 794 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 795 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 796 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 797 create_pca9552(soc, 4, 0x60); 798 799 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 800 0x48); 801 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 802 0x49); 803 create_pca9552(soc, 5, 0x60); 804 create_pca9552(soc, 5, 0x61); 805 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 806 "pca9546", 0x70); 807 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 808 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 809 810 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 811 0x48); 812 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 813 0x4a); 814 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 815 0x4b); 816 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 817 "pca9546", 0x70); 818 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 819 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 820 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 821 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 822 823 create_pca9552(soc, 7, 0x30); 824 create_pca9552(soc, 7, 0x31); 825 create_pca9552(soc, 7, 0x32); 826 create_pca9552(soc, 7, 0x33); 827 create_pca9552(soc, 7, 0x60); 828 create_pca9552(soc, 7, 0x61); 829 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 830 /* Bus 7: TODO si7021-a20@20 */ 831 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 832 0x48); 833 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 834 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 835 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 836 837 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 838 0x48); 839 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 840 0x4a); 841 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 842 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 843 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 844 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 845 create_pca9552(soc, 8, 0x60); 846 create_pca9552(soc, 8, 0x61); 847 /* Bus 8: ucd90320@11 */ 848 /* Bus 8: ucd90320@b */ 849 /* Bus 8: ucd90320@c */ 850 851 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 852 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 853 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 854 855 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 856 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 857 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 858 859 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 860 0x48); 861 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 862 0x49); 863 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 864 "pca9546", 0x70); 865 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 866 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 867 create_pca9552(soc, 11, 0x60); 868 869 870 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 871 create_pca9552(soc, 13, 0x60); 872 873 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 874 create_pca9552(soc, 14, 0x60); 875 876 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 877 create_pca9552(soc, 15, 0x60); 878 } 879 880 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 881 I2CBus **channels) 882 { 883 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 884 for (int i = 0; i < 8; i++) { 885 channels[i] = pca954x_i2c_get_bus(mux, i); 886 } 887 } 888 889 #define TYPE_LM75 TYPE_TMP105 890 #define TYPE_TMP75 TYPE_TMP105 891 #define TYPE_TMP422 "tmp422" 892 893 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 894 { 895 AspeedSoCState *soc = bmc->soc; 896 I2CBus *i2c[144] = {}; 897 898 for (int i = 0; i < 16; i++) { 899 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 900 } 901 I2CBus *i2c180 = i2c[2]; 902 I2CBus *i2c480 = i2c[8]; 903 I2CBus *i2c600 = i2c[11]; 904 905 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 906 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 907 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 908 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 909 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 910 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 911 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 912 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 913 for (int i = 0; i < 8; i++) { 914 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 915 } 916 917 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 918 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 919 920 /* 921 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 922 * 24c02 size is 2Kbits or 256 bytes 923 */ 924 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 925 at24c_eeprom_init(i2c[20], 0x50, 256); 926 at24c_eeprom_init(i2c[22], 0x52, 256); 927 928 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 929 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 930 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 931 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 932 933 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 934 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 935 936 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 937 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 938 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 939 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 940 941 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 942 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 943 944 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 945 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 946 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 947 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 948 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 949 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 950 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 951 952 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 953 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 954 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 955 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 956 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 957 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 958 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 959 at24c_eeprom_init(i2c[28], 0x50, 256); 960 961 for (int i = 0; i < 8; i++) { 962 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 963 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 964 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 965 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 966 } 967 } 968 969 #define TYPE_TMP421 "tmp421" 970 971 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 972 { 973 AspeedSoCState *soc = bmc->soc; 974 I2CBus *i2c[13] = {}; 975 for (int i = 0; i < 13; i++) { 976 if ((i == 8) || (i == 11)) { 977 continue; 978 } 979 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 980 } 981 982 /* Bus 0 - 5 all have the same config. */ 983 for (int i = 0; i < 6; i++) { 984 /* Missing model: ti,ina230 @ 0x45 */ 985 /* Missing model: mps,mp5023 @ 0x40 */ 986 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 987 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 988 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 989 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 990 /* Missing model: fsc,fusb302 @ 0x22 */ 991 } 992 993 /* Bus 6 */ 994 at24c_eeprom_init(i2c[6], 0x56, 65536); 995 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 996 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 997 998 999 /* Bus 7 */ 1000 at24c_eeprom_init(i2c[7], 0x54, 65536); 1001 1002 /* Bus 9 */ 1003 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 1004 1005 /* Bus 10 */ 1006 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 1007 /* Missing model: ti,hdc1080 @ 0x40 */ 1008 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 1009 1010 /* Bus 12 */ 1011 /* Missing model: adi,adm1278 @ 0x11 */ 1012 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 1013 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 1014 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 1015 } 1016 1017 static void fby35_i2c_init(AspeedMachineState *bmc) 1018 { 1019 AspeedSoCState *soc = bmc->soc; 1020 I2CBus *i2c[16]; 1021 1022 for (int i = 0; i < 16; i++) { 1023 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1024 } 1025 1026 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 1027 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 1028 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 1029 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 1030 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 1031 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 1032 1033 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 1034 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 1035 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 1036 fby35_nic_fruid_len); 1037 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 1038 fby35_bb_fruid_len); 1039 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 1040 fby35_bmc_fruid_len); 1041 1042 /* 1043 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 1044 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 1045 * each. 1046 */ 1047 } 1048 1049 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1050 { 1051 AspeedSoCState *soc = bmc->soc; 1052 1053 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1054 } 1055 1056 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1057 { 1058 AspeedSoCState *soc = bmc->soc; 1059 I2CSlave *therm_mux, *cpuvr_mux; 1060 1061 /* Create the generic DC-SCM hardware */ 1062 qcom_dc_scm_bmc_i2c_init(bmc); 1063 1064 /* Now create the Firework specific hardware */ 1065 1066 /* I2C7 CPUVR MUX */ 1067 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1068 "pca9546", 0x70); 1069 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1070 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1071 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1072 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1073 1074 /* I2C8 Thermal Diodes*/ 1075 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1076 "pca9548", 0x70); 1077 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1078 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1079 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1080 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1081 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1082 1083 /* I2C9 Fan Controller (MAX31785) */ 1084 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1085 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1086 } 1087 1088 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1089 { 1090 return ASPEED_MACHINE(obj)->mmio_exec; 1091 } 1092 1093 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1094 { 1095 ASPEED_MACHINE(obj)->mmio_exec = value; 1096 } 1097 1098 static void aspeed_machine_instance_init(Object *obj) 1099 { 1100 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj); 1101 1102 ASPEED_MACHINE(obj)->mmio_exec = false; 1103 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1; 1104 } 1105 1106 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1107 { 1108 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1109 return g_strdup(bmc->fmc_model); 1110 } 1111 1112 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1113 { 1114 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1115 1116 g_free(bmc->fmc_model); 1117 bmc->fmc_model = g_strdup(value); 1118 } 1119 1120 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1121 { 1122 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1123 return g_strdup(bmc->spi_model); 1124 } 1125 1126 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1127 { 1128 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1129 1130 g_free(bmc->spi_model); 1131 bmc->spi_model = g_strdup(value); 1132 } 1133 1134 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1135 { 1136 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1137 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1138 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1139 1140 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); 1141 } 1142 1143 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1144 { 1145 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1146 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1147 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1148 int val; 1149 int uart_first = aspeed_uart_first(sc); 1150 int uart_last = aspeed_uart_last(sc); 1151 1152 if (sscanf(value, "uart%u", &val) != 1) { 1153 error_setg(errp, "Bad value for \"uart\" property"); 1154 return; 1155 } 1156 1157 /* The number of UART depends on the SoC */ 1158 if (val < uart_first || val > uart_last) { 1159 error_setg(errp, "\"uart\" should be in range [%d - %d]", 1160 uart_first, uart_last); 1161 return; 1162 } 1163 bmc->uart_chosen = val + ASPEED_DEV_UART0; 1164 } 1165 1166 static void aspeed_machine_class_props_init(ObjectClass *oc) 1167 { 1168 object_class_property_add_bool(oc, "execute-in-place", 1169 aspeed_get_mmio_exec, 1170 aspeed_set_mmio_exec); 1171 object_class_property_set_description(oc, "execute-in-place", 1172 "boot directly from CE0 flash device"); 1173 1174 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1175 aspeed_set_bmc_console); 1176 object_class_property_set_description(oc, "bmc-console", 1177 "Change the default UART to \"uartX\""); 1178 1179 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1180 aspeed_set_fmc_model); 1181 object_class_property_set_description(oc, "fmc-model", 1182 "Change the FMC Flash model"); 1183 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1184 aspeed_set_spi_model); 1185 object_class_property_set_description(oc, "spi-model", 1186 "Change the SPI Flash model"); 1187 } 1188 1189 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) 1190 { 1191 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); 1192 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1193 1194 mc->default_cpus = sc->num_cpus; 1195 mc->min_cpus = sc->num_cpus; 1196 mc->max_cpus = sc->num_cpus; 1197 mc->valid_cpu_types = sc->valid_cpu_types; 1198 } 1199 1200 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp) 1201 { 1202 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1203 1204 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 1205 } 1206 1207 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value, 1208 Error **errp) 1209 { 1210 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1211 1212 if (value) { 1213 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1214 } else { 1215 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1216 } 1217 } 1218 1219 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc) 1220 { 1221 object_class_property_add_bool(oc, "boot-emmc", 1222 aspeed_machine_ast2600_get_boot_from_emmc, 1223 aspeed_machine_ast2600_set_boot_from_emmc); 1224 object_class_property_set_description(oc, "boot-emmc", 1225 "Set or unset boot from EMMC"); 1226 } 1227 1228 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1229 { 1230 MachineClass *mc = MACHINE_CLASS(oc); 1231 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1232 1233 mc->init = aspeed_machine_init; 1234 mc->no_floppy = 1; 1235 mc->no_cdrom = 1; 1236 mc->no_parallel = 1; 1237 mc->default_ram_id = "ram"; 1238 amc->macs_mask = ASPEED_MAC0_ON; 1239 amc->uart_default = ASPEED_DEV_UART5; 1240 1241 aspeed_machine_class_props_init(oc); 1242 } 1243 1244 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1245 { 1246 MachineClass *mc = MACHINE_CLASS(oc); 1247 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1248 1249 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1250 amc->soc_name = "ast2400-a1"; 1251 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1252 amc->fmc_model = "n25q256a"; 1253 amc->spi_model = "mx25l25635f"; 1254 amc->num_cs = 1; 1255 amc->i2c_init = palmetto_bmc_i2c_init; 1256 mc->default_ram_size = 256 * MiB; 1257 aspeed_machine_class_init_cpus_defaults(mc); 1258 }; 1259 1260 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1261 { 1262 MachineClass *mc = MACHINE_CLASS(oc); 1263 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1264 1265 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1266 amc->soc_name = "ast2400-a1"; 1267 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1268 amc->fmc_model = "n25q256a"; 1269 amc->spi_model = "mx25l25635e"; 1270 amc->num_cs = 1; 1271 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1272 mc->default_ram_size = 128 * MiB; 1273 aspeed_machine_class_init_cpus_defaults(mc); 1274 } 1275 1276 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1277 void *data) 1278 { 1279 MachineClass *mc = MACHINE_CLASS(oc); 1280 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1281 1282 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1283 amc->soc_name = "ast2400-a1"; 1284 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1285 amc->fmc_model = "mx25l25635e"; 1286 amc->spi_model = "mx25l25635e"; 1287 amc->num_cs = 1; 1288 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1289 amc->i2c_init = palmetto_bmc_i2c_init; 1290 mc->default_ram_size = 256 * MiB; 1291 aspeed_machine_class_init_cpus_defaults(mc); 1292 } 1293 1294 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1295 void *data) 1296 { 1297 MachineClass *mc = MACHINE_CLASS(oc); 1298 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1299 1300 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1301 amc->soc_name = "ast2500-a1"; 1302 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1303 amc->fmc_model = "mx25l25635e"; 1304 amc->spi_model = "mx25l25635e"; 1305 amc->num_cs = 1; 1306 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1307 amc->i2c_init = palmetto_bmc_i2c_init; 1308 mc->default_ram_size = 512 * MiB; 1309 aspeed_machine_class_init_cpus_defaults(mc); 1310 } 1311 1312 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1313 { 1314 MachineClass *mc = MACHINE_CLASS(oc); 1315 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1316 1317 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1318 amc->soc_name = "ast2500-a1"; 1319 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1320 amc->fmc_model = "mx25l25635e"; 1321 amc->spi_model = "mx25l25635f"; 1322 amc->num_cs = 1; 1323 amc->i2c_init = ast2500_evb_i2c_init; 1324 mc->default_ram_size = 512 * MiB; 1325 aspeed_machine_class_init_cpus_defaults(mc); 1326 }; 1327 1328 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data) 1329 { 1330 MachineClass *mc = MACHINE_CLASS(oc); 1331 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1332 1333 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1334 amc->soc_name = "ast2500-a1"; 1335 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1336 amc->hw_strap2 = 0; 1337 amc->fmc_model = "n25q256a"; 1338 amc->spi_model = "mx25l25635e"; 1339 amc->num_cs = 2; 1340 amc->i2c_init = yosemitev2_bmc_i2c_init; 1341 mc->default_ram_size = 512 * MiB; 1342 aspeed_machine_class_init_cpus_defaults(mc); 1343 }; 1344 1345 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1346 { 1347 MachineClass *mc = MACHINE_CLASS(oc); 1348 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1349 1350 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1351 amc->soc_name = "ast2500-a1"; 1352 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1353 amc->fmc_model = "n25q256a"; 1354 amc->spi_model = "mx66l1g45g"; 1355 amc->num_cs = 2; 1356 amc->i2c_init = romulus_bmc_i2c_init; 1357 mc->default_ram_size = 512 * MiB; 1358 aspeed_machine_class_init_cpus_defaults(mc); 1359 }; 1360 1361 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data) 1362 { 1363 MachineClass *mc = MACHINE_CLASS(oc); 1364 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1365 1366 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1367 amc->soc_name = "ast2500-a1"; 1368 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1369 amc->hw_strap2 = 0; 1370 amc->fmc_model = "n25q256a"; 1371 amc->spi_model = "mx25l25635e"; 1372 amc->num_cs = 2; 1373 amc->i2c_init = tiogapass_bmc_i2c_init; 1374 mc->default_ram_size = 1 * GiB; 1375 aspeed_machine_class_init_cpus_defaults(mc); 1376 }; 1377 1378 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1379 { 1380 MachineClass *mc = MACHINE_CLASS(oc); 1381 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1382 1383 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1384 amc->soc_name = "ast2500-a1"; 1385 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1386 amc->fmc_model = "mx66l1g45g"; 1387 amc->spi_model = "mx66l1g45g"; 1388 amc->num_cs = 2; 1389 amc->i2c_init = sonorapass_bmc_i2c_init; 1390 mc->default_ram_size = 512 * MiB; 1391 aspeed_machine_class_init_cpus_defaults(mc); 1392 }; 1393 1394 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1395 { 1396 MachineClass *mc = MACHINE_CLASS(oc); 1397 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1398 1399 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1400 amc->soc_name = "ast2500-a1"; 1401 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1402 amc->fmc_model = "mx25l25635f"; 1403 amc->spi_model = "mx66l1g45g"; 1404 amc->num_cs = 2; 1405 amc->i2c_init = witherspoon_bmc_i2c_init; 1406 mc->default_ram_size = 512 * MiB; 1407 aspeed_machine_class_init_cpus_defaults(mc); 1408 }; 1409 1410 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1411 { 1412 MachineClass *mc = MACHINE_CLASS(oc); 1413 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1414 1415 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1416 amc->soc_name = "ast2600-a3"; 1417 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1418 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1419 amc->fmc_model = "mx66u51235f"; 1420 amc->spi_model = "mx66u51235f"; 1421 amc->num_cs = 1; 1422 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1423 ASPEED_MAC3_ON; 1424 amc->sdhci_wp_inverted = true; 1425 amc->i2c_init = ast2600_evb_i2c_init; 1426 mc->default_ram_size = 1 * GiB; 1427 aspeed_machine_class_init_cpus_defaults(mc); 1428 aspeed_machine_ast2600_class_emmc_init(oc); 1429 }; 1430 1431 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1432 { 1433 MachineClass *mc = MACHINE_CLASS(oc); 1434 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1435 1436 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1437 amc->soc_name = "ast2500-a1"; 1438 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1439 amc->fmc_model = "n25q512a"; 1440 amc->spi_model = "mx25l25635e"; 1441 amc->num_cs = 2; 1442 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1443 amc->i2c_init = g220a_bmc_i2c_init; 1444 mc->default_ram_size = 1024 * MiB; 1445 aspeed_machine_class_init_cpus_defaults(mc); 1446 }; 1447 1448 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1449 { 1450 MachineClass *mc = MACHINE_CLASS(oc); 1451 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1452 1453 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1454 amc->soc_name = "ast2500-a1"; 1455 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1456 amc->fmc_model = "n25q512a"; 1457 amc->spi_model = "mx25l25635e"; 1458 amc->num_cs = 2; 1459 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1460 amc->i2c_init = fp5280g2_bmc_i2c_init; 1461 mc->default_ram_size = 512 * MiB; 1462 aspeed_machine_class_init_cpus_defaults(mc); 1463 }; 1464 1465 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1466 { 1467 MachineClass *mc = MACHINE_CLASS(oc); 1468 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1469 1470 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1471 amc->soc_name = "ast2600-a3"; 1472 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1473 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1474 amc->fmc_model = "mx66l1g45g"; 1475 amc->spi_model = "mx66l1g45g"; 1476 amc->num_cs = 2; 1477 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1478 amc->i2c_init = rainier_bmc_i2c_init; 1479 mc->default_ram_size = 1 * GiB; 1480 aspeed_machine_class_init_cpus_defaults(mc); 1481 aspeed_machine_ast2600_class_emmc_init(oc); 1482 }; 1483 1484 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1485 1486 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1487 { 1488 MachineClass *mc = MACHINE_CLASS(oc); 1489 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1490 1491 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1492 amc->soc_name = "ast2600-a3"; 1493 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1494 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1495 amc->fmc_model = "mx66l1g45g"; 1496 amc->spi_model = "mx66l1g45g"; 1497 amc->num_cs = 2; 1498 amc->macs_mask = ASPEED_MAC3_ON; 1499 amc->i2c_init = fuji_bmc_i2c_init; 1500 amc->uart_default = ASPEED_DEV_UART1; 1501 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1502 aspeed_machine_class_init_cpus_defaults(mc); 1503 }; 1504 1505 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1506 1507 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1508 { 1509 MachineClass *mc = MACHINE_CLASS(oc); 1510 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1511 1512 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1513 amc->soc_name = "ast2600-a3"; 1514 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1515 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1516 amc->fmc_model = "w25q01jvq"; 1517 amc->spi_model = NULL; 1518 amc->num_cs = 2; 1519 amc->macs_mask = ASPEED_MAC2_ON; 1520 amc->i2c_init = bletchley_bmc_i2c_init; 1521 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1522 aspeed_machine_class_init_cpus_defaults(mc); 1523 } 1524 1525 static void fby35_reset(MachineState *state, ResetType type) 1526 { 1527 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1528 AspeedGPIOState *gpio = &bmc->soc->gpio; 1529 1530 qemu_devices_reset(type); 1531 1532 /* Board ID: 7 (Class-1, 4 slots) */ 1533 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1534 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1535 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1536 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1537 1538 /* Slot presence pins, inverse polarity. (False means present) */ 1539 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1540 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1541 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1542 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1543 1544 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1545 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1546 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1547 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1548 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1549 } 1550 1551 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) 1552 { 1553 MachineClass *mc = MACHINE_CLASS(oc); 1554 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1555 1556 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1557 mc->reset = fby35_reset; 1558 amc->fmc_model = "mx66l1g45g"; 1559 amc->num_cs = 2; 1560 amc->macs_mask = ASPEED_MAC3_ON; 1561 amc->i2c_init = fby35_i2c_init; 1562 /* FIXME: Replace this macro with something more general */ 1563 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1564 aspeed_machine_class_init_cpus_defaults(mc); 1565 } 1566 1567 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1568 /* Main SYSCLK frequency in Hz (200MHz) */ 1569 #define SYSCLK_FRQ 200000000ULL 1570 1571 static void aspeed_minibmc_machine_init(MachineState *machine) 1572 { 1573 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1574 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1575 Clock *sysclk; 1576 1577 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1578 clock_set_hz(sysclk, SYSCLK_FRQ); 1579 1580 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 1581 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 1582 object_unref(OBJECT(bmc->soc)); 1583 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); 1584 1585 object_property_set_link(OBJECT(bmc->soc), "memory", 1586 OBJECT(get_system_memory()), &error_abort); 1587 connect_serial_hds_to_uarts(bmc); 1588 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 1589 1590 if (defaults_enabled()) { 1591 aspeed_board_init_flashes(&bmc->soc->fmc, 1592 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1593 amc->num_cs, 1594 0); 1595 1596 aspeed_board_init_flashes(&bmc->soc->spi[0], 1597 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1598 amc->num_cs, amc->num_cs); 1599 1600 aspeed_board_init_flashes(&bmc->soc->spi[1], 1601 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1602 amc->num_cs, (amc->num_cs * 2)); 1603 } 1604 1605 if (amc->i2c_init) { 1606 amc->i2c_init(bmc); 1607 } 1608 1609 armv7m_load_kernel(ARM_CPU(first_cpu), 1610 machine->kernel_filename, 1611 0, 1612 AST1030_INTERNAL_FLASH_SIZE); 1613 } 1614 1615 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1616 { 1617 AspeedSoCState *soc = bmc->soc; 1618 1619 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1620 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1621 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1622 1623 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1624 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1625 } 1626 1627 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1628 void *data) 1629 { 1630 MachineClass *mc = MACHINE_CLASS(oc); 1631 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1632 1633 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1634 amc->soc_name = "ast1030-a1"; 1635 amc->hw_strap1 = 0; 1636 amc->hw_strap2 = 0; 1637 mc->init = aspeed_minibmc_machine_init; 1638 amc->i2c_init = ast1030_evb_i2c_init; 1639 mc->default_ram_size = 0; 1640 amc->fmc_model = "w25q80bl"; 1641 amc->spi_model = "w25q256"; 1642 amc->num_cs = 2; 1643 amc->macs_mask = 0; 1644 aspeed_machine_class_init_cpus_defaults(mc); 1645 } 1646 1647 #ifdef TARGET_AARCH64 1648 static void ast2700_evb_i2c_init(AspeedMachineState *bmc) 1649 { 1650 AspeedSoCState *soc = bmc->soc; 1651 1652 /* LM75 is compatible with TMP105 driver */ 1653 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), 1654 TYPE_TMP105, 0x4d); 1655 } 1656 1657 static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data) 1658 { 1659 MachineClass *mc = MACHINE_CLASS(oc); 1660 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1661 1662 mc->desc = "Aspeed AST2700 EVB (Cortex-A35)"; 1663 amc->soc_name = "ast2700-a0"; 1664 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 1665 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 1666 amc->fmc_model = "w25q01jvq"; 1667 amc->spi_model = "w25q512jv"; 1668 amc->num_cs = 2; 1669 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 1670 amc->uart_default = ASPEED_DEV_UART12; 1671 amc->i2c_init = ast2700_evb_i2c_init; 1672 mc->default_ram_size = 1 * GiB; 1673 aspeed_machine_class_init_cpus_defaults(mc); 1674 } 1675 #endif 1676 1677 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1678 void *data) 1679 { 1680 MachineClass *mc = MACHINE_CLASS(oc); 1681 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1682 1683 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1684 amc->soc_name = "ast2600-a3"; 1685 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1686 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1687 amc->fmc_model = "n25q512a"; 1688 amc->spi_model = "n25q512a"; 1689 amc->num_cs = 2; 1690 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1691 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1692 mc->default_ram_size = 1 * GiB; 1693 aspeed_machine_class_init_cpus_defaults(mc); 1694 }; 1695 1696 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1697 void *data) 1698 { 1699 MachineClass *mc = MACHINE_CLASS(oc); 1700 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1701 1702 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1703 amc->soc_name = "ast2600-a3"; 1704 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1705 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1706 amc->fmc_model = "n25q512a"; 1707 amc->spi_model = "n25q512a"; 1708 amc->num_cs = 2; 1709 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1710 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1711 mc->default_ram_size = 1 * GiB; 1712 aspeed_machine_class_init_cpus_defaults(mc); 1713 }; 1714 1715 static const TypeInfo aspeed_machine_types[] = { 1716 { 1717 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1718 .parent = TYPE_ASPEED_MACHINE, 1719 .class_init = aspeed_machine_palmetto_class_init, 1720 }, { 1721 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1722 .parent = TYPE_ASPEED_MACHINE, 1723 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1724 }, { 1725 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 1726 .parent = TYPE_ASPEED_MACHINE, 1727 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 1728 }, { 1729 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1730 .parent = TYPE_ASPEED_MACHINE, 1731 .class_init = aspeed_machine_ast2500_evb_class_init, 1732 }, { 1733 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1734 .parent = TYPE_ASPEED_MACHINE, 1735 .class_init = aspeed_machine_romulus_class_init, 1736 }, { 1737 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1738 .parent = TYPE_ASPEED_MACHINE, 1739 .class_init = aspeed_machine_sonorapass_class_init, 1740 }, { 1741 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1742 .parent = TYPE_ASPEED_MACHINE, 1743 .class_init = aspeed_machine_witherspoon_class_init, 1744 }, { 1745 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1746 .parent = TYPE_ASPEED_MACHINE, 1747 .class_init = aspeed_machine_ast2600_evb_class_init, 1748 }, { 1749 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 1750 .parent = TYPE_ASPEED_MACHINE, 1751 .class_init = aspeed_machine_yosemitev2_class_init, 1752 }, { 1753 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 1754 .parent = TYPE_ASPEED_MACHINE, 1755 .class_init = aspeed_machine_tiogapass_class_init, 1756 }, { 1757 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1758 .parent = TYPE_ASPEED_MACHINE, 1759 .class_init = aspeed_machine_g220a_class_init, 1760 }, { 1761 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 1762 .parent = TYPE_ASPEED_MACHINE, 1763 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 1764 }, { 1765 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 1766 .parent = TYPE_ASPEED_MACHINE, 1767 .class_init = aspeed_machine_qcom_firework_class_init, 1768 }, { 1769 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1770 .parent = TYPE_ASPEED_MACHINE, 1771 .class_init = aspeed_machine_fp5280g2_class_init, 1772 }, { 1773 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1774 .parent = TYPE_ASPEED_MACHINE, 1775 .class_init = aspeed_machine_quanta_q71l_class_init, 1776 }, { 1777 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1778 .parent = TYPE_ASPEED_MACHINE, 1779 .class_init = aspeed_machine_rainier_class_init, 1780 }, { 1781 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1782 .parent = TYPE_ASPEED_MACHINE, 1783 .class_init = aspeed_machine_fuji_class_init, 1784 }, { 1785 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1786 .parent = TYPE_ASPEED_MACHINE, 1787 .class_init = aspeed_machine_bletchley_class_init, 1788 }, { 1789 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1790 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1791 .class_init = aspeed_machine_fby35_class_init, 1792 }, { 1793 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1794 .parent = TYPE_ASPEED_MACHINE, 1795 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1796 #ifdef TARGET_AARCH64 1797 }, { 1798 .name = MACHINE_TYPE_NAME("ast2700-evb"), 1799 .parent = TYPE_ASPEED_MACHINE, 1800 .class_init = aspeed_machine_ast2700_evb_class_init, 1801 #endif 1802 }, { 1803 .name = TYPE_ASPEED_MACHINE, 1804 .parent = TYPE_MACHINE, 1805 .instance_size = sizeof(AspeedMachineState), 1806 .instance_init = aspeed_machine_instance_init, 1807 .class_size = sizeof(AspeedMachineClass), 1808 .class_init = aspeed_machine_class_init, 1809 .abstract = true, 1810 } 1811 }; 1812 1813 DEFINE_TYPES(aspeed_machine_types) 1814