1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/block/flash.h" 19 #include "hw/i2c/i2c_mux_pca954x.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/misc/pca9552.h" 22 #include "hw/nvram/eeprom_at24c.h" 23 #include "hw/sensor/tmp105.h" 24 #include "hw/misc/led.h" 25 #include "hw/qdev-properties.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/reset.h" 28 #include "hw/loader.h" 29 #include "qemu/error-report.h" 30 #include "qemu/units.h" 31 #include "hw/qdev-clock.h" 32 #include "sysemu/sysemu.h" 33 34 static struct arm_boot_info aspeed_board_binfo = { 35 .board_id = -1, /* device-tree-only board */ 36 }; 37 38 struct AspeedMachineState { 39 /* Private */ 40 MachineState parent_obj; 41 /* Public */ 42 43 AspeedSoCState *soc; 44 MemoryRegion boot_rom; 45 bool mmio_exec; 46 uint32_t uart_chosen; 47 char *fmc_model; 48 char *spi_model; 49 }; 50 51 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 52 #if HOST_LONG_BITS == 32 53 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) 54 #else 55 #define ASPEED_RAM_SIZE(sz) (sz) 56 #endif 57 58 /* Palmetto hardware value: 0x120CE416 */ 59 #define PALMETTO_BMC_HW_STRAP1 ( \ 60 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 61 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 62 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 63 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 64 SCU_HW_STRAP_VGA_CLASS_CODE | \ 65 SCU_HW_STRAP_LPC_RESET_PIN | \ 66 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 67 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 68 SCU_HW_STRAP_SPI_WIDTH | \ 69 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 70 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 71 72 /* TODO: Find the actual hardware value */ 73 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 74 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 75 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 76 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 77 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 78 SCU_HW_STRAP_VGA_CLASS_CODE | \ 79 SCU_HW_STRAP_LPC_RESET_PIN | \ 80 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 81 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 82 SCU_HW_STRAP_SPI_WIDTH | \ 83 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 84 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 85 86 /* TODO: Find the actual hardware value */ 87 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 88 AST2500_HW_STRAP1_DEFAULTS | \ 89 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 90 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 91 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 92 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 93 SCU_HW_STRAP_SPI_WIDTH | \ 94 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 95 96 /* AST2500 evb hardware value: 0xF100C2E6 */ 97 #define AST2500_EVB_HW_STRAP1 (( \ 98 AST2500_HW_STRAP1_DEFAULTS | \ 99 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 100 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 101 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 102 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 103 SCU_HW_STRAP_MAC1_RGMII | \ 104 SCU_HW_STRAP_MAC0_RGMII) & \ 105 ~SCU_HW_STRAP_2ND_BOOT_WDT) 106 107 /* Romulus hardware value: 0xF10AD206 */ 108 #define ROMULUS_BMC_HW_STRAP1 ( \ 109 AST2500_HW_STRAP1_DEFAULTS | \ 110 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 111 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 112 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 113 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 114 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 115 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 116 117 /* Sonorapass hardware value: 0xF100D216 */ 118 #define SONORAPASS_BMC_HW_STRAP1 ( \ 119 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 120 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 121 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 122 SCU_AST2500_HW_STRAP_RESERVED28 | \ 123 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 124 SCU_HW_STRAP_VGA_CLASS_CODE | \ 125 SCU_HW_STRAP_LPC_RESET_PIN | \ 126 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 127 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 128 SCU_HW_STRAP_VGA_BIOS_ROM | \ 129 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 130 SCU_AST2500_HW_STRAP_RESERVED1) 131 132 #define G220A_BMC_HW_STRAP1 ( \ 133 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 134 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 135 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 136 SCU_AST2500_HW_STRAP_RESERVED28 | \ 137 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 138 SCU_HW_STRAP_2ND_BOOT_WDT | \ 139 SCU_HW_STRAP_VGA_CLASS_CODE | \ 140 SCU_HW_STRAP_LPC_RESET_PIN | \ 141 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 142 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 143 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 144 SCU_AST2500_HW_STRAP_RESERVED1) 145 146 /* FP5280G2 hardware value: 0XF100D286 */ 147 #define FP5280G2_BMC_HW_STRAP1 ( \ 148 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 149 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 150 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 151 SCU_AST2500_HW_STRAP_RESERVED28 | \ 152 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 153 SCU_HW_STRAP_VGA_CLASS_CODE | \ 154 SCU_HW_STRAP_LPC_RESET_PIN | \ 155 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 156 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 157 SCU_HW_STRAP_MAC1_RGMII | \ 158 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 159 SCU_AST2500_HW_STRAP_RESERVED1) 160 161 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 162 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 163 164 /* Quanta-Q71l hardware value */ 165 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 166 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 167 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 168 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 169 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 170 SCU_HW_STRAP_VGA_CLASS_CODE | \ 171 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 172 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 173 SCU_HW_STRAP_SPI_WIDTH | \ 174 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 175 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 176 177 /* AST2600 evb hardware value */ 178 #define AST2600_EVB_HW_STRAP1 0x000000C0 179 #define AST2600_EVB_HW_STRAP2 0x00000003 180 181 /* Tacoma hardware value */ 182 #define TACOMA_BMC_HW_STRAP1 0x00000000 183 #define TACOMA_BMC_HW_STRAP2 0x00000040 184 185 /* Rainier hardware value: (QEMU prototype) */ 186 #define RAINIER_BMC_HW_STRAP1 0x00422016 187 #define RAINIER_BMC_HW_STRAP2 0x80000848 188 189 /* Fuji hardware value */ 190 #define FUJI_BMC_HW_STRAP1 0x00000000 191 #define FUJI_BMC_HW_STRAP2 0x00000000 192 193 /* Bletchley hardware value */ 194 /* TODO: Leave same as EVB for now. */ 195 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 196 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 197 198 /* Qualcomm DC-SCM hardware value */ 199 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 200 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 201 202 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 203 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 204 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 205 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 206 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 207 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 208 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 209 210 static void aspeed_write_smpboot(ARMCPU *cpu, 211 const struct arm_boot_info *info) 212 { 213 AddressSpace *as = arm_boot_address_space(cpu, info); 214 static const ARMInsnFixup poll_mailbox_ready[] = { 215 /* 216 * r2 = per-cpu go sign value 217 * r1 = AST_SMP_MBOX_FIELD_ENTRY 218 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 219 */ 220 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 221 { 0xe21000ff }, /* ands r0, r0, #255 */ 222 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 223 { 0xe1822000 }, /* orr r2, r2, r0 */ 224 225 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 226 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 227 228 { 0xe320f002 }, /* wfe */ 229 { 0xe5904000 }, /* ldr r4, [r0] */ 230 { 0xe1520004 }, /* cmp r2, r4 */ 231 { 0x1afffffb }, /* bne <wfe> */ 232 { 0xe591f000 }, /* ldr pc, [r1] */ 233 { AST_SMP_MBOX_GOSIGN }, 234 { AST_SMP_MBOX_FIELD_ENTRY }, 235 { AST_SMP_MBOX_FIELD_GOSIGN }, 236 { 0, FIXUP_TERMINATOR } 237 }; 238 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 239 240 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 241 poll_mailbox_ready, fixupcontext); 242 } 243 244 static void aspeed_reset_secondary(ARMCPU *cpu, 245 const struct arm_boot_info *info) 246 { 247 AddressSpace *as = arm_boot_address_space(cpu, info); 248 CPUState *cs = CPU(cpu); 249 250 /* info->smp_bootreg_addr */ 251 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 252 MEMTXATTRS_UNSPECIFIED, NULL); 253 cpu_set_pc(cs, info->smp_loader_start); 254 } 255 256 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 257 Error **errp) 258 { 259 g_autofree void *storage = NULL; 260 int64_t size; 261 262 /* The block backend size should have already been 'validated' by 263 * the creation of the m25p80 object. 264 */ 265 size = blk_getlength(blk); 266 if (size <= 0) { 267 error_setg(errp, "failed to get flash size"); 268 return; 269 } 270 271 if (rom_size > size) { 272 rom_size = size; 273 } 274 275 storage = g_malloc0(rom_size); 276 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 277 error_setg(errp, "failed to read the initial flash content"); 278 return; 279 } 280 281 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 282 } 283 284 /* 285 * Create a ROM and copy the flash contents at the expected address 286 * (0x0). Boots faster than execute-in-place. 287 */ 288 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 289 uint64_t rom_size) 290 { 291 AspeedSoCState *soc = bmc->soc; 292 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); 293 294 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 295 &error_abort); 296 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 297 &bmc->boot_rom, 1); 298 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], 299 rom_size, &error_abort); 300 } 301 302 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 303 unsigned int count, int unit0) 304 { 305 int i; 306 307 if (!flashtype) { 308 return; 309 } 310 311 for (i = 0; i < count; ++i) { 312 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 313 DeviceState *dev; 314 315 dev = qdev_new(flashtype); 316 if (dinfo) { 317 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 318 } 319 qdev_prop_set_uint8(dev, "cs", i); 320 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 321 } 322 } 323 324 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 325 { 326 DeviceState *card; 327 328 if (!dinfo) { 329 return; 330 } 331 card = qdev_new(TYPE_SD_CARD); 332 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 333 &error_fatal); 334 qdev_realize_and_unref(card, 335 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 336 &error_fatal); 337 } 338 339 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 340 { 341 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 342 AspeedSoCState *s = bmc->soc; 343 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 344 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 345 346 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 347 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) { 348 if (uart == uart_chosen) { 349 continue; 350 } 351 aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); 352 } 353 } 354 355 static void aspeed_machine_init(MachineState *machine) 356 { 357 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 358 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 359 AspeedSoCClass *sc; 360 int i; 361 362 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 363 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 364 object_unref(OBJECT(bmc->soc)); 365 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 366 367 /* 368 * This will error out if the RAM size is not supported by the 369 * memory controller of the SoC. 370 */ 371 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 372 &error_fatal); 373 374 for (i = 0; i < sc->macs_num; i++) { 375 if ((amc->macs_mask & (1 << i)) && 376 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), 377 true, NULL)) { 378 break; /* No configs left; stop asking */ 379 } 380 } 381 382 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1, 383 &error_abort); 384 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 385 &error_abort); 386 object_property_set_link(OBJECT(bmc->soc), "memory", 387 OBJECT(get_system_memory()), &error_abort); 388 object_property_set_link(OBJECT(bmc->soc), "dram", 389 OBJECT(machine->ram), &error_abort); 390 if (machine->kernel_filename) { 391 /* 392 * When booting with a -kernel command line there is no u-boot 393 * that runs to unlock the SCU. In this case set the default to 394 * be unlocked as the kernel expects 395 */ 396 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 397 ASPEED_SCU_PROT_KEY, &error_abort); 398 } 399 connect_serial_hds_to_uarts(bmc); 400 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 401 402 if (defaults_enabled()) { 403 aspeed_board_init_flashes(&bmc->soc->fmc, 404 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 405 amc->num_cs, 0); 406 aspeed_board_init_flashes(&bmc->soc->spi[0], 407 bmc->spi_model ? bmc->spi_model : amc->spi_model, 408 1, amc->num_cs); 409 } 410 411 if (machine->kernel_filename && sc->num_cpus > 1) { 412 /* With no u-boot we must set up a boot stub for the secondary CPU */ 413 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 414 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 415 0x80, &error_abort); 416 memory_region_add_subregion(get_system_memory(), 417 AST_SMP_MAILBOX_BASE, smpboot); 418 419 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 420 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 421 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 422 } 423 424 aspeed_board_binfo.ram_size = machine->ram_size; 425 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 426 427 if (amc->i2c_init) { 428 amc->i2c_init(bmc); 429 } 430 431 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 432 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 433 drive_get(IF_SD, 0, i)); 434 } 435 436 if (bmc->soc->emmc.num_slots) { 437 sdhci_attach_drive(&bmc->soc->emmc.slots[0], 438 drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots)); 439 } 440 441 if (!bmc->mmio_exec) { 442 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 443 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 444 445 if (fmc0) { 446 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 447 aspeed_install_boot_rom(bmc, fmc0, rom_size); 448 } 449 } 450 451 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 452 } 453 454 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 455 { 456 AspeedSoCState *soc = bmc->soc; 457 DeviceState *dev; 458 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 459 460 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 461 * enough to provide basic RTC features. Alarms will be missing */ 462 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 463 464 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 465 eeprom_buf); 466 467 /* add a TMP423 temperature sensor */ 468 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 469 "tmp423", 0x4c)); 470 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 471 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 472 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 473 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 474 } 475 476 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 477 { 478 AspeedSoCState *soc = bmc->soc; 479 480 /* 481 * The quanta-q71l platform expects tmp75s which are compatible with 482 * tmp105s. 483 */ 484 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 485 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 486 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 487 488 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 489 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 490 /* TODO: Add Memory Riser i2c mux and eeproms. */ 491 492 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 493 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 494 495 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 496 497 /* i2c-7 */ 498 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 499 /* - i2c@0: pmbus@59 */ 500 /* - i2c@1: pmbus@58 */ 501 /* - i2c@2: pmbus@58 */ 502 /* - i2c@3: pmbus@59 */ 503 504 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 505 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 506 } 507 508 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 509 { 510 AspeedSoCState *soc = bmc->soc; 511 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 512 513 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 514 eeprom_buf); 515 516 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 517 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 518 TYPE_TMP105, 0x4d); 519 } 520 521 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 522 { 523 AspeedSoCState *soc = bmc->soc; 524 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 525 526 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 527 eeprom_buf); 528 529 /* LM75 is compatible with TMP105 driver */ 530 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 531 TYPE_TMP105, 0x4d); 532 } 533 534 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 535 { 536 AspeedSoCState *soc = bmc->soc; 537 538 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 539 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 540 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 541 /* TMP421 */ 542 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 543 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 544 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 545 546 } 547 548 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 549 { 550 AspeedSoCState *soc = bmc->soc; 551 552 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 553 * good enough */ 554 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 555 } 556 557 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 558 { 559 AspeedSoCState *soc = bmc->soc; 560 561 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 562 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 563 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 564 /* TMP421 */ 565 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 566 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 567 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 568 } 569 570 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 571 { 572 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 573 TYPE_PCA9552, addr); 574 } 575 576 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 577 { 578 AspeedSoCState *soc = bmc->soc; 579 580 /* bus 2 : */ 581 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 582 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 583 /* bus 2 : pca9546 @ 0x73 */ 584 585 /* bus 3 : pca9548 @ 0x70 */ 586 587 /* bus 4 : */ 588 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 589 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 590 eeprom4_54); 591 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 592 create_pca9552(soc, 4, 0x76); 593 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 594 create_pca9552(soc, 4, 0x77); 595 596 /* bus 6 : */ 597 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 598 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 599 /* bus 6 : pca9546 @ 0x73 */ 600 601 /* bus 8 : */ 602 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 603 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 604 eeprom8_56); 605 create_pca9552(soc, 8, 0x60); 606 create_pca9552(soc, 8, 0x61); 607 /* bus 8 : adc128d818 @ 0x1d */ 608 /* bus 8 : adc128d818 @ 0x1f */ 609 610 /* 611 * bus 13 : pca9548 @ 0x71 612 * - channel 3: 613 * - tmm421 @ 0x4c 614 * - tmp421 @ 0x4e 615 * - tmp421 @ 0x4f 616 */ 617 618 } 619 620 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 621 { 622 static const struct { 623 unsigned gpio_id; 624 LEDColor color; 625 const char *description; 626 bool gpio_polarity; 627 } pca1_leds[] = { 628 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 629 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 630 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 631 }; 632 AspeedSoCState *soc = bmc->soc; 633 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 634 DeviceState *dev; 635 LEDState *led; 636 637 /* Bus 3: TODO bmp280@77 */ 638 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 639 qdev_prop_set_string(dev, "description", "pca1"); 640 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 641 aspeed_i2c_get_bus(&soc->i2c, 3), 642 &error_fatal); 643 644 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 645 led = led_create_simple(OBJECT(bmc), 646 pca1_leds[i].gpio_polarity, 647 pca1_leds[i].color, 648 pca1_leds[i].description); 649 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 650 qdev_get_gpio_in(DEVICE(led), 0)); 651 } 652 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 653 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 654 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 655 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 656 657 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 658 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 659 0x4a); 660 661 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 662 * good enough */ 663 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 664 665 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 666 eeprom_buf); 667 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 668 qdev_prop_set_string(dev, "description", "pca0"); 669 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 670 aspeed_i2c_get_bus(&soc->i2c, 11), 671 &error_fatal); 672 /* Bus 11: TODO ucd90160@64 */ 673 } 674 675 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 676 { 677 AspeedSoCState *soc = bmc->soc; 678 DeviceState *dev; 679 680 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 681 "emc1413", 0x4c)); 682 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 683 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 684 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 685 686 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 687 "emc1413", 0x4c)); 688 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 689 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 690 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 691 692 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 693 "emc1413", 0x4c)); 694 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 695 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 696 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 697 698 static uint8_t eeprom_buf[2 * 1024] = { 699 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 700 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 701 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 702 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 703 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 704 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 705 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 706 }; 707 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 708 eeprom_buf); 709 } 710 711 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 712 { 713 AspeedSoCState *soc = bmc->soc; 714 I2CSlave *i2c_mux; 715 716 /* The at24c256 */ 717 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 718 719 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 720 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 721 0x48); 722 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 723 0x49); 724 725 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 726 "pca9546", 0x70); 727 /* It expects a TMP112 but a TMP105 is compatible */ 728 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 729 0x4a); 730 731 /* It expects a ds3232 but a ds1338 is good enough */ 732 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 733 734 /* It expects a pca9555 but a pca9552 is compatible */ 735 create_pca9552(soc, 8, 0x30); 736 } 737 738 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 739 { 740 AspeedSoCState *soc = bmc->soc; 741 I2CSlave *i2c_mux; 742 743 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 744 745 create_pca9552(soc, 3, 0x61); 746 747 /* The rainier expects a TMP275 but a TMP105 is compatible */ 748 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 749 0x48); 750 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 751 0x49); 752 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 753 0x4a); 754 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 755 "pca9546", 0x70); 756 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 757 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 758 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 759 create_pca9552(soc, 4, 0x60); 760 761 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 762 0x48); 763 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 764 0x49); 765 create_pca9552(soc, 5, 0x60); 766 create_pca9552(soc, 5, 0x61); 767 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 768 "pca9546", 0x70); 769 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 770 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 771 772 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 773 0x48); 774 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 775 0x4a); 776 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 777 0x4b); 778 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 779 "pca9546", 0x70); 780 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 781 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 782 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 783 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 784 785 create_pca9552(soc, 7, 0x30); 786 create_pca9552(soc, 7, 0x31); 787 create_pca9552(soc, 7, 0x32); 788 create_pca9552(soc, 7, 0x33); 789 create_pca9552(soc, 7, 0x60); 790 create_pca9552(soc, 7, 0x61); 791 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 792 /* Bus 7: TODO si7021-a20@20 */ 793 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 794 0x48); 795 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 796 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 797 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 798 799 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 800 0x48); 801 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 802 0x4a); 803 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 804 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 805 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 806 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 807 create_pca9552(soc, 8, 0x60); 808 create_pca9552(soc, 8, 0x61); 809 /* Bus 8: ucd90320@11 */ 810 /* Bus 8: ucd90320@b */ 811 /* Bus 8: ucd90320@c */ 812 813 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 814 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 815 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 816 817 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 818 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 819 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 820 821 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 822 0x48); 823 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 824 0x49); 825 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 826 "pca9546", 0x70); 827 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 828 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 829 create_pca9552(soc, 11, 0x60); 830 831 832 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 833 create_pca9552(soc, 13, 0x60); 834 835 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 836 create_pca9552(soc, 14, 0x60); 837 838 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 839 create_pca9552(soc, 15, 0x60); 840 } 841 842 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 843 I2CBus **channels) 844 { 845 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 846 for (int i = 0; i < 8; i++) { 847 channels[i] = pca954x_i2c_get_bus(mux, i); 848 } 849 } 850 851 #define TYPE_LM75 TYPE_TMP105 852 #define TYPE_TMP75 TYPE_TMP105 853 #define TYPE_TMP422 "tmp422" 854 855 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 856 { 857 AspeedSoCState *soc = bmc->soc; 858 I2CBus *i2c[144] = {}; 859 860 for (int i = 0; i < 16; i++) { 861 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 862 } 863 I2CBus *i2c180 = i2c[2]; 864 I2CBus *i2c480 = i2c[8]; 865 I2CBus *i2c600 = i2c[11]; 866 867 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 868 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 869 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 870 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 871 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 872 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 873 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 874 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 875 for (int i = 0; i < 8; i++) { 876 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 877 } 878 879 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 880 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 881 882 /* 883 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 884 * 24c02 size is 2Kbits or 256 bytes 885 */ 886 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 887 at24c_eeprom_init(i2c[20], 0x50, 256); 888 at24c_eeprom_init(i2c[22], 0x52, 256); 889 890 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 891 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 892 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 893 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 894 895 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 896 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 897 898 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 899 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 900 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 901 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 902 903 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 904 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 905 906 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 907 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 908 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 909 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 910 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 911 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 912 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 913 914 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 915 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 916 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 917 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 918 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 919 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 920 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 921 at24c_eeprom_init(i2c[28], 0x50, 256); 922 923 for (int i = 0; i < 8; i++) { 924 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 925 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 926 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 927 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 928 } 929 } 930 931 #define TYPE_TMP421 "tmp421" 932 933 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 934 { 935 AspeedSoCState *soc = bmc->soc; 936 I2CBus *i2c[13] = {}; 937 for (int i = 0; i < 13; i++) { 938 if ((i == 8) || (i == 11)) { 939 continue; 940 } 941 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 942 } 943 944 /* Bus 0 - 5 all have the same config. */ 945 for (int i = 0; i < 6; i++) { 946 /* Missing model: ti,ina230 @ 0x45 */ 947 /* Missing model: mps,mp5023 @ 0x40 */ 948 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 949 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 950 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 951 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 952 /* Missing model: fsc,fusb302 @ 0x22 */ 953 } 954 955 /* Bus 6 */ 956 at24c_eeprom_init(i2c[6], 0x56, 65536); 957 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 958 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 959 960 961 /* Bus 7 */ 962 at24c_eeprom_init(i2c[7], 0x54, 65536); 963 964 /* Bus 9 */ 965 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 966 967 /* Bus 10 */ 968 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 969 /* Missing model: ti,hdc1080 @ 0x40 */ 970 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 971 972 /* Bus 12 */ 973 /* Missing model: adi,adm1278 @ 0x11 */ 974 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 975 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 976 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 977 } 978 979 static void fby35_i2c_init(AspeedMachineState *bmc) 980 { 981 AspeedSoCState *soc = bmc->soc; 982 I2CBus *i2c[16]; 983 984 for (int i = 0; i < 16; i++) { 985 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 986 } 987 988 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 989 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 990 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 991 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 992 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 993 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 994 995 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 996 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 997 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 998 fby35_nic_fruid_len); 999 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 1000 fby35_bb_fruid_len); 1001 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 1002 fby35_bmc_fruid_len); 1003 1004 /* 1005 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 1006 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 1007 * each. 1008 */ 1009 } 1010 1011 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1012 { 1013 AspeedSoCState *soc = bmc->soc; 1014 1015 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1016 } 1017 1018 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1019 { 1020 AspeedSoCState *soc = bmc->soc; 1021 I2CSlave *therm_mux, *cpuvr_mux; 1022 1023 /* Create the generic DC-SCM hardware */ 1024 qcom_dc_scm_bmc_i2c_init(bmc); 1025 1026 /* Now create the Firework specific hardware */ 1027 1028 /* I2C7 CPUVR MUX */ 1029 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1030 "pca9546", 0x70); 1031 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1032 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1033 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1034 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1035 1036 /* I2C8 Thermal Diodes*/ 1037 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1038 "pca9548", 0x70); 1039 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1040 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1041 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1042 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1043 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1044 1045 /* I2C9 Fan Controller (MAX31785) */ 1046 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1047 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1048 } 1049 1050 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1051 { 1052 return ASPEED_MACHINE(obj)->mmio_exec; 1053 } 1054 1055 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1056 { 1057 ASPEED_MACHINE(obj)->mmio_exec = value; 1058 } 1059 1060 static void aspeed_machine_instance_init(Object *obj) 1061 { 1062 ASPEED_MACHINE(obj)->mmio_exec = false; 1063 } 1064 1065 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1066 { 1067 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1068 return g_strdup(bmc->fmc_model); 1069 } 1070 1071 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1072 { 1073 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1074 1075 g_free(bmc->fmc_model); 1076 bmc->fmc_model = g_strdup(value); 1077 } 1078 1079 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1080 { 1081 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1082 return g_strdup(bmc->spi_model); 1083 } 1084 1085 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1086 { 1087 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1088 1089 g_free(bmc->spi_model); 1090 bmc->spi_model = g_strdup(value); 1091 } 1092 1093 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1094 { 1095 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1096 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1097 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1098 1099 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); 1100 } 1101 1102 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1103 { 1104 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1105 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1106 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1107 int val; 1108 int uart_first = aspeed_uart_first(sc); 1109 int uart_last = aspeed_uart_last(sc); 1110 1111 if (sscanf(value, "uart%u", &val) != 1) { 1112 error_setg(errp, "Bad value for \"uart\" property"); 1113 return; 1114 } 1115 1116 /* The number of UART depends on the SoC */ 1117 if (val < uart_first || val > uart_last) { 1118 error_setg(errp, "\"uart\" should be in range [%d - %d]", 1119 uart_first, uart_last); 1120 return; 1121 } 1122 bmc->uart_chosen = val + ASPEED_DEV_UART0; 1123 } 1124 1125 static void aspeed_machine_class_props_init(ObjectClass *oc) 1126 { 1127 object_class_property_add_bool(oc, "execute-in-place", 1128 aspeed_get_mmio_exec, 1129 aspeed_set_mmio_exec); 1130 object_class_property_set_description(oc, "execute-in-place", 1131 "boot directly from CE0 flash device"); 1132 1133 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1134 aspeed_set_bmc_console); 1135 object_class_property_set_description(oc, "bmc-console", 1136 "Change the default UART to \"uartX\""); 1137 1138 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1139 aspeed_set_fmc_model); 1140 object_class_property_set_description(oc, "fmc-model", 1141 "Change the FMC Flash model"); 1142 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1143 aspeed_set_spi_model); 1144 object_class_property_set_description(oc, "spi-model", 1145 "Change the SPI Flash model"); 1146 } 1147 1148 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) 1149 { 1150 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); 1151 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1152 1153 mc->default_cpus = sc->num_cpus; 1154 mc->min_cpus = sc->num_cpus; 1155 mc->max_cpus = sc->num_cpus; 1156 mc->valid_cpu_types = sc->valid_cpu_types; 1157 } 1158 1159 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1160 { 1161 MachineClass *mc = MACHINE_CLASS(oc); 1162 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1163 1164 mc->init = aspeed_machine_init; 1165 mc->no_floppy = 1; 1166 mc->no_cdrom = 1; 1167 mc->no_parallel = 1; 1168 mc->default_ram_id = "ram"; 1169 amc->macs_mask = ASPEED_MAC0_ON; 1170 amc->uart_default = ASPEED_DEV_UART5; 1171 1172 aspeed_machine_class_props_init(oc); 1173 } 1174 1175 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1176 { 1177 MachineClass *mc = MACHINE_CLASS(oc); 1178 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1179 1180 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1181 amc->soc_name = "ast2400-a1"; 1182 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1183 amc->fmc_model = "n25q256a"; 1184 amc->spi_model = "mx25l25635f"; 1185 amc->num_cs = 1; 1186 amc->i2c_init = palmetto_bmc_i2c_init; 1187 mc->default_ram_size = 256 * MiB; 1188 aspeed_machine_class_init_cpus_defaults(mc); 1189 }; 1190 1191 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1192 { 1193 MachineClass *mc = MACHINE_CLASS(oc); 1194 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1195 1196 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1197 amc->soc_name = "ast2400-a1"; 1198 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1199 amc->fmc_model = "n25q256a"; 1200 amc->spi_model = "mx25l25635e"; 1201 amc->num_cs = 1; 1202 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1203 mc->default_ram_size = 128 * MiB; 1204 aspeed_machine_class_init_cpus_defaults(mc); 1205 } 1206 1207 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1208 void *data) 1209 { 1210 MachineClass *mc = MACHINE_CLASS(oc); 1211 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1212 1213 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1214 amc->soc_name = "ast2400-a1"; 1215 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1216 amc->fmc_model = "mx25l25635e"; 1217 amc->spi_model = "mx25l25635e"; 1218 amc->num_cs = 1; 1219 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1220 amc->i2c_init = palmetto_bmc_i2c_init; 1221 mc->default_ram_size = 256 * MiB; 1222 aspeed_machine_class_init_cpus_defaults(mc); 1223 } 1224 1225 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1226 void *data) 1227 { 1228 MachineClass *mc = MACHINE_CLASS(oc); 1229 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1230 1231 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1232 amc->soc_name = "ast2500-a1"; 1233 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1234 amc->fmc_model = "mx25l25635e"; 1235 amc->spi_model = "mx25l25635e"; 1236 amc->num_cs = 1; 1237 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1238 amc->i2c_init = palmetto_bmc_i2c_init; 1239 mc->default_ram_size = 512 * MiB; 1240 aspeed_machine_class_init_cpus_defaults(mc); 1241 } 1242 1243 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1244 { 1245 MachineClass *mc = MACHINE_CLASS(oc); 1246 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1247 1248 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1249 amc->soc_name = "ast2500-a1"; 1250 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1251 amc->fmc_model = "mx25l25635e"; 1252 amc->spi_model = "mx25l25635f"; 1253 amc->num_cs = 1; 1254 amc->i2c_init = ast2500_evb_i2c_init; 1255 mc->default_ram_size = 512 * MiB; 1256 aspeed_machine_class_init_cpus_defaults(mc); 1257 }; 1258 1259 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data) 1260 { 1261 MachineClass *mc = MACHINE_CLASS(oc); 1262 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1263 1264 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1265 amc->soc_name = "ast2500-a1"; 1266 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1267 amc->hw_strap2 = 0; 1268 amc->fmc_model = "n25q256a"; 1269 amc->spi_model = "mx25l25635e"; 1270 amc->num_cs = 2; 1271 amc->i2c_init = yosemitev2_bmc_i2c_init; 1272 mc->default_ram_size = 512 * MiB; 1273 aspeed_machine_class_init_cpus_defaults(mc); 1274 }; 1275 1276 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1277 { 1278 MachineClass *mc = MACHINE_CLASS(oc); 1279 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1280 1281 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1282 amc->soc_name = "ast2500-a1"; 1283 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1284 amc->fmc_model = "n25q256a"; 1285 amc->spi_model = "mx66l1g45g"; 1286 amc->num_cs = 2; 1287 amc->i2c_init = romulus_bmc_i2c_init; 1288 mc->default_ram_size = 512 * MiB; 1289 aspeed_machine_class_init_cpus_defaults(mc); 1290 }; 1291 1292 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data) 1293 { 1294 MachineClass *mc = MACHINE_CLASS(oc); 1295 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1296 1297 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1298 amc->soc_name = "ast2500-a1"; 1299 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1300 amc->hw_strap2 = 0; 1301 amc->fmc_model = "n25q256a"; 1302 amc->spi_model = "mx25l25635e"; 1303 amc->num_cs = 2; 1304 amc->i2c_init = tiogapass_bmc_i2c_init; 1305 mc->default_ram_size = 1 * GiB; 1306 aspeed_machine_class_init_cpus_defaults(mc); 1307 }; 1308 1309 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1310 { 1311 MachineClass *mc = MACHINE_CLASS(oc); 1312 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1313 1314 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1315 amc->soc_name = "ast2500-a1"; 1316 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1317 amc->fmc_model = "mx66l1g45g"; 1318 amc->spi_model = "mx66l1g45g"; 1319 amc->num_cs = 2; 1320 amc->i2c_init = sonorapass_bmc_i2c_init; 1321 mc->default_ram_size = 512 * MiB; 1322 aspeed_machine_class_init_cpus_defaults(mc); 1323 }; 1324 1325 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1326 { 1327 MachineClass *mc = MACHINE_CLASS(oc); 1328 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1329 1330 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1331 amc->soc_name = "ast2500-a1"; 1332 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1333 amc->fmc_model = "mx25l25635f"; 1334 amc->spi_model = "mx66l1g45g"; 1335 amc->num_cs = 2; 1336 amc->i2c_init = witherspoon_bmc_i2c_init; 1337 mc->default_ram_size = 512 * MiB; 1338 aspeed_machine_class_init_cpus_defaults(mc); 1339 }; 1340 1341 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1342 { 1343 MachineClass *mc = MACHINE_CLASS(oc); 1344 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1345 1346 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1347 amc->soc_name = "ast2600-a3"; 1348 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1349 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1350 amc->fmc_model = "mx66u51235f"; 1351 amc->spi_model = "mx66u51235f"; 1352 amc->num_cs = 1; 1353 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1354 ASPEED_MAC3_ON; 1355 amc->i2c_init = ast2600_evb_i2c_init; 1356 mc->default_ram_size = 1 * GiB; 1357 aspeed_machine_class_init_cpus_defaults(mc); 1358 }; 1359 1360 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1361 { 1362 MachineClass *mc = MACHINE_CLASS(oc); 1363 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1364 1365 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1366 amc->soc_name = "ast2600-a3"; 1367 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1368 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1369 amc->fmc_model = "mx66l1g45g"; 1370 amc->spi_model = "mx66l1g45g"; 1371 amc->num_cs = 2; 1372 amc->macs_mask = ASPEED_MAC2_ON; 1373 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1374 mc->default_ram_size = 1 * GiB; 1375 aspeed_machine_class_init_cpus_defaults(mc); 1376 }; 1377 1378 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1379 { 1380 MachineClass *mc = MACHINE_CLASS(oc); 1381 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1382 1383 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1384 amc->soc_name = "ast2500-a1"; 1385 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1386 amc->fmc_model = "n25q512a"; 1387 amc->spi_model = "mx25l25635e"; 1388 amc->num_cs = 2; 1389 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1390 amc->i2c_init = g220a_bmc_i2c_init; 1391 mc->default_ram_size = 1024 * MiB; 1392 aspeed_machine_class_init_cpus_defaults(mc); 1393 }; 1394 1395 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1396 { 1397 MachineClass *mc = MACHINE_CLASS(oc); 1398 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1399 1400 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1401 amc->soc_name = "ast2500-a1"; 1402 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1403 amc->fmc_model = "n25q512a"; 1404 amc->spi_model = "mx25l25635e"; 1405 amc->num_cs = 2; 1406 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1407 amc->i2c_init = fp5280g2_bmc_i2c_init; 1408 mc->default_ram_size = 512 * MiB; 1409 aspeed_machine_class_init_cpus_defaults(mc); 1410 }; 1411 1412 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1413 { 1414 MachineClass *mc = MACHINE_CLASS(oc); 1415 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1416 1417 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1418 amc->soc_name = "ast2600-a3"; 1419 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1420 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1421 amc->fmc_model = "mx66l1g45g"; 1422 amc->spi_model = "mx66l1g45g"; 1423 amc->num_cs = 2; 1424 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1425 amc->i2c_init = rainier_bmc_i2c_init; 1426 mc->default_ram_size = 1 * GiB; 1427 aspeed_machine_class_init_cpus_defaults(mc); 1428 }; 1429 1430 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1431 1432 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1433 { 1434 MachineClass *mc = MACHINE_CLASS(oc); 1435 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1436 1437 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1438 amc->soc_name = "ast2600-a3"; 1439 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1440 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1441 amc->fmc_model = "mx66l1g45g"; 1442 amc->spi_model = "mx66l1g45g"; 1443 amc->num_cs = 2; 1444 amc->macs_mask = ASPEED_MAC3_ON; 1445 amc->i2c_init = fuji_bmc_i2c_init; 1446 amc->uart_default = ASPEED_DEV_UART1; 1447 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1448 aspeed_machine_class_init_cpus_defaults(mc); 1449 }; 1450 1451 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1452 1453 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1454 { 1455 MachineClass *mc = MACHINE_CLASS(oc); 1456 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1457 1458 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1459 amc->soc_name = "ast2600-a3"; 1460 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1461 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1462 amc->fmc_model = "w25q01jvq"; 1463 amc->spi_model = NULL; 1464 amc->num_cs = 2; 1465 amc->macs_mask = ASPEED_MAC2_ON; 1466 amc->i2c_init = bletchley_bmc_i2c_init; 1467 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1468 aspeed_machine_class_init_cpus_defaults(mc); 1469 } 1470 1471 static void fby35_reset(MachineState *state, ShutdownCause reason) 1472 { 1473 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1474 AspeedGPIOState *gpio = &bmc->soc->gpio; 1475 1476 qemu_devices_reset(reason); 1477 1478 /* Board ID: 7 (Class-1, 4 slots) */ 1479 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1480 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1481 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1482 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1483 1484 /* Slot presence pins, inverse polarity. (False means present) */ 1485 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1486 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1487 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1488 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1489 1490 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1491 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1492 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1493 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1494 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1495 } 1496 1497 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) 1498 { 1499 MachineClass *mc = MACHINE_CLASS(oc); 1500 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1501 1502 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1503 mc->reset = fby35_reset; 1504 amc->fmc_model = "mx66l1g45g"; 1505 amc->num_cs = 2; 1506 amc->macs_mask = ASPEED_MAC3_ON; 1507 amc->i2c_init = fby35_i2c_init; 1508 /* FIXME: Replace this macro with something more general */ 1509 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1510 aspeed_machine_class_init_cpus_defaults(mc); 1511 } 1512 1513 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1514 /* Main SYSCLK frequency in Hz (200MHz) */ 1515 #define SYSCLK_FRQ 200000000ULL 1516 1517 static void aspeed_minibmc_machine_init(MachineState *machine) 1518 { 1519 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1520 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1521 Clock *sysclk; 1522 1523 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1524 clock_set_hz(sysclk, SYSCLK_FRQ); 1525 1526 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 1527 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 1528 object_unref(OBJECT(bmc->soc)); 1529 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); 1530 1531 object_property_set_link(OBJECT(bmc->soc), "memory", 1532 OBJECT(get_system_memory()), &error_abort); 1533 connect_serial_hds_to_uarts(bmc); 1534 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 1535 1536 aspeed_board_init_flashes(&bmc->soc->fmc, 1537 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1538 amc->num_cs, 1539 0); 1540 1541 aspeed_board_init_flashes(&bmc->soc->spi[0], 1542 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1543 amc->num_cs, amc->num_cs); 1544 1545 aspeed_board_init_flashes(&bmc->soc->spi[1], 1546 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1547 amc->num_cs, (amc->num_cs * 2)); 1548 1549 if (amc->i2c_init) { 1550 amc->i2c_init(bmc); 1551 } 1552 1553 armv7m_load_kernel(ARM_CPU(first_cpu), 1554 machine->kernel_filename, 1555 0, 1556 AST1030_INTERNAL_FLASH_SIZE); 1557 } 1558 1559 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1560 { 1561 AspeedSoCState *soc = bmc->soc; 1562 1563 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1564 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1565 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1566 1567 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1568 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1569 } 1570 1571 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1572 void *data) 1573 { 1574 MachineClass *mc = MACHINE_CLASS(oc); 1575 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1576 1577 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1578 amc->soc_name = "ast1030-a1"; 1579 amc->hw_strap1 = 0; 1580 amc->hw_strap2 = 0; 1581 mc->init = aspeed_minibmc_machine_init; 1582 amc->i2c_init = ast1030_evb_i2c_init; 1583 mc->default_ram_size = 0; 1584 amc->fmc_model = "sst25vf032b"; 1585 amc->spi_model = "sst25vf032b"; 1586 amc->num_cs = 2; 1587 amc->macs_mask = 0; 1588 aspeed_machine_class_init_cpus_defaults(mc); 1589 } 1590 1591 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1592 void *data) 1593 { 1594 MachineClass *mc = MACHINE_CLASS(oc); 1595 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1596 1597 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1598 amc->soc_name = "ast2600-a3"; 1599 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1600 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1601 amc->fmc_model = "n25q512a"; 1602 amc->spi_model = "n25q512a"; 1603 amc->num_cs = 2; 1604 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1605 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1606 mc->default_ram_size = 1 * GiB; 1607 aspeed_machine_class_init_cpus_defaults(mc); 1608 }; 1609 1610 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1611 void *data) 1612 { 1613 MachineClass *mc = MACHINE_CLASS(oc); 1614 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1615 1616 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1617 amc->soc_name = "ast2600-a3"; 1618 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1619 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1620 amc->fmc_model = "n25q512a"; 1621 amc->spi_model = "n25q512a"; 1622 amc->num_cs = 2; 1623 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1624 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1625 mc->default_ram_size = 1 * GiB; 1626 aspeed_machine_class_init_cpus_defaults(mc); 1627 }; 1628 1629 static const TypeInfo aspeed_machine_types[] = { 1630 { 1631 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1632 .parent = TYPE_ASPEED_MACHINE, 1633 .class_init = aspeed_machine_palmetto_class_init, 1634 }, { 1635 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1636 .parent = TYPE_ASPEED_MACHINE, 1637 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1638 }, { 1639 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 1640 .parent = TYPE_ASPEED_MACHINE, 1641 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 1642 }, { 1643 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1644 .parent = TYPE_ASPEED_MACHINE, 1645 .class_init = aspeed_machine_ast2500_evb_class_init, 1646 }, { 1647 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1648 .parent = TYPE_ASPEED_MACHINE, 1649 .class_init = aspeed_machine_romulus_class_init, 1650 }, { 1651 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1652 .parent = TYPE_ASPEED_MACHINE, 1653 .class_init = aspeed_machine_sonorapass_class_init, 1654 }, { 1655 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1656 .parent = TYPE_ASPEED_MACHINE, 1657 .class_init = aspeed_machine_witherspoon_class_init, 1658 }, { 1659 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1660 .parent = TYPE_ASPEED_MACHINE, 1661 .class_init = aspeed_machine_ast2600_evb_class_init, 1662 }, { 1663 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 1664 .parent = TYPE_ASPEED_MACHINE, 1665 .class_init = aspeed_machine_yosemitev2_class_init, 1666 }, { 1667 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1668 .parent = TYPE_ASPEED_MACHINE, 1669 .class_init = aspeed_machine_tacoma_class_init, 1670 }, { 1671 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 1672 .parent = TYPE_ASPEED_MACHINE, 1673 .class_init = aspeed_machine_tiogapass_class_init, 1674 }, { 1675 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1676 .parent = TYPE_ASPEED_MACHINE, 1677 .class_init = aspeed_machine_g220a_class_init, 1678 }, { 1679 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 1680 .parent = TYPE_ASPEED_MACHINE, 1681 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 1682 }, { 1683 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 1684 .parent = TYPE_ASPEED_MACHINE, 1685 .class_init = aspeed_machine_qcom_firework_class_init, 1686 }, { 1687 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1688 .parent = TYPE_ASPEED_MACHINE, 1689 .class_init = aspeed_machine_fp5280g2_class_init, 1690 }, { 1691 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1692 .parent = TYPE_ASPEED_MACHINE, 1693 .class_init = aspeed_machine_quanta_q71l_class_init, 1694 }, { 1695 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1696 .parent = TYPE_ASPEED_MACHINE, 1697 .class_init = aspeed_machine_rainier_class_init, 1698 }, { 1699 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1700 .parent = TYPE_ASPEED_MACHINE, 1701 .class_init = aspeed_machine_fuji_class_init, 1702 }, { 1703 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1704 .parent = TYPE_ASPEED_MACHINE, 1705 .class_init = aspeed_machine_bletchley_class_init, 1706 }, { 1707 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1708 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1709 .class_init = aspeed_machine_fby35_class_init, 1710 }, { 1711 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1712 .parent = TYPE_ASPEED_MACHINE, 1713 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1714 }, { 1715 .name = TYPE_ASPEED_MACHINE, 1716 .parent = TYPE_MACHINE, 1717 .instance_size = sizeof(AspeedMachineState), 1718 .instance_init = aspeed_machine_instance_init, 1719 .class_size = sizeof(AspeedMachineClass), 1720 .class_init = aspeed_machine_class_init, 1721 .abstract = true, 1722 } 1723 }; 1724 1725 DEFINE_TYPES(aspeed_machine_types) 1726