1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "cpu.h" 15 #include "exec/address-spaces.h" 16 #include "hw/arm/boot.h" 17 #include "hw/arm/aspeed.h" 18 #include "hw/arm/aspeed_soc.h" 19 #include "hw/boards.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/misc/pca9552.h" 22 #include "hw/misc/tmp105.h" 23 #include "hw/misc/led.h" 24 #include "hw/qdev-properties.h" 25 #include "qemu/log.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/sysemu.h" 28 #include "hw/loader.h" 29 #include "qemu/error-report.h" 30 #include "qemu/units.h" 31 32 static struct arm_boot_info aspeed_board_binfo = { 33 .board_id = -1, /* device-tree-only board */ 34 }; 35 36 struct AspeedMachineState { 37 /* Private */ 38 MachineState parent_obj; 39 /* Public */ 40 41 AspeedSoCState soc; 42 MemoryRegion ram_container; 43 MemoryRegion max_ram; 44 bool mmio_exec; 45 char *fmc_model; 46 char *spi_model; 47 }; 48 49 /* Palmetto hardware value: 0x120CE416 */ 50 #define PALMETTO_BMC_HW_STRAP1 ( \ 51 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 52 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 53 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 54 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 55 SCU_HW_STRAP_VGA_CLASS_CODE | \ 56 SCU_HW_STRAP_LPC_RESET_PIN | \ 57 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 58 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 59 SCU_HW_STRAP_SPI_WIDTH | \ 60 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 61 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 62 63 /* TODO: Find the actual hardware value */ 64 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 65 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 66 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 67 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 68 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 69 SCU_HW_STRAP_VGA_CLASS_CODE | \ 70 SCU_HW_STRAP_LPC_RESET_PIN | \ 71 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 72 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 73 SCU_HW_STRAP_SPI_WIDTH | \ 74 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 75 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 76 77 /* AST2500 evb hardware value: 0xF100C2E6 */ 78 #define AST2500_EVB_HW_STRAP1 (( \ 79 AST2500_HW_STRAP1_DEFAULTS | \ 80 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 81 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 82 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 83 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 84 SCU_HW_STRAP_MAC1_RGMII | \ 85 SCU_HW_STRAP_MAC0_RGMII) & \ 86 ~SCU_HW_STRAP_2ND_BOOT_WDT) 87 88 /* Romulus hardware value: 0xF10AD206 */ 89 #define ROMULUS_BMC_HW_STRAP1 ( \ 90 AST2500_HW_STRAP1_DEFAULTS | \ 91 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 92 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 93 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 94 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 95 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 96 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 97 98 /* Sonorapass hardware value: 0xF100D216 */ 99 #define SONORAPASS_BMC_HW_STRAP1 ( \ 100 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 101 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 102 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 103 SCU_AST2500_HW_STRAP_RESERVED28 | \ 104 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 105 SCU_HW_STRAP_VGA_CLASS_CODE | \ 106 SCU_HW_STRAP_LPC_RESET_PIN | \ 107 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 108 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 109 SCU_HW_STRAP_VGA_BIOS_ROM | \ 110 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 111 SCU_AST2500_HW_STRAP_RESERVED1) 112 113 /* Swift hardware value: 0xF11AD206 */ 114 #define SWIFT_BMC_HW_STRAP1 ( \ 115 AST2500_HW_STRAP1_DEFAULTS | \ 116 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 117 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 118 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 119 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 120 SCU_H_PLL_BYPASS_EN | \ 121 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 122 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 123 124 #define G220A_BMC_HW_STRAP1 ( \ 125 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 126 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 127 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 128 SCU_AST2500_HW_STRAP_RESERVED28 | \ 129 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 130 SCU_HW_STRAP_2ND_BOOT_WDT | \ 131 SCU_HW_STRAP_VGA_CLASS_CODE | \ 132 SCU_HW_STRAP_LPC_RESET_PIN | \ 133 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 134 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 135 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 136 SCU_AST2500_HW_STRAP_RESERVED1) 137 138 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 139 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 140 141 /* AST2600 evb hardware value */ 142 #define AST2600_EVB_HW_STRAP1 0x000000C0 143 #define AST2600_EVB_HW_STRAP2 0x00000003 144 145 /* Tacoma hardware value */ 146 #define TACOMA_BMC_HW_STRAP1 0x00000000 147 #define TACOMA_BMC_HW_STRAP2 0x00000040 148 149 /* 150 * The max ram region is for firmwares that scan the address space 151 * with load/store to guess how much RAM the SoC has. 152 */ 153 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 154 { 155 return 0; 156 } 157 158 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 159 unsigned size) 160 { 161 /* Discard writes */ 162 } 163 164 static const MemoryRegionOps max_ram_ops = { 165 .read = max_ram_read, 166 .write = max_ram_write, 167 .endianness = DEVICE_NATIVE_ENDIAN, 168 }; 169 170 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 171 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 172 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 173 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 174 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 175 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 176 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 177 178 static void aspeed_write_smpboot(ARMCPU *cpu, 179 const struct arm_boot_info *info) 180 { 181 static const uint32_t poll_mailbox_ready[] = { 182 /* 183 * r2 = per-cpu go sign value 184 * r1 = AST_SMP_MBOX_FIELD_ENTRY 185 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 186 */ 187 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 188 0xe21000ff, /* ands r0, r0, #255 */ 189 0xe59f201c, /* ldr r2, [pc, #28] */ 190 0xe1822000, /* orr r2, r2, r0 */ 191 192 0xe59f1018, /* ldr r1, [pc, #24] */ 193 0xe59f0018, /* ldr r0, [pc, #24] */ 194 195 0xe320f002, /* wfe */ 196 0xe5904000, /* ldr r4, [r0] */ 197 0xe1520004, /* cmp r2, r4 */ 198 0x1afffffb, /* bne <wfe> */ 199 0xe591f000, /* ldr pc, [r1] */ 200 AST_SMP_MBOX_GOSIGN, 201 AST_SMP_MBOX_FIELD_ENTRY, 202 AST_SMP_MBOX_FIELD_GOSIGN, 203 }; 204 205 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 206 sizeof(poll_mailbox_ready), 207 info->smp_loader_start); 208 } 209 210 static void aspeed_reset_secondary(ARMCPU *cpu, 211 const struct arm_boot_info *info) 212 { 213 AddressSpace *as = arm_boot_address_space(cpu, info); 214 CPUState *cs = CPU(cpu); 215 216 /* info->smp_bootreg_addr */ 217 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 218 MEMTXATTRS_UNSPECIFIED, NULL); 219 cpu_set_pc(cs, info->smp_loader_start); 220 } 221 222 #define FIRMWARE_ADDR 0x0 223 224 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 225 Error **errp) 226 { 227 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 228 uint8_t *storage; 229 int64_t size; 230 231 /* The block backend size should have already been 'validated' by 232 * the creation of the m25p80 object. 233 */ 234 size = blk_getlength(blk); 235 if (size <= 0) { 236 error_setg(errp, "failed to get flash size"); 237 return; 238 } 239 240 if (rom_size > size) { 241 rom_size = size; 242 } 243 244 storage = g_new0(uint8_t, rom_size); 245 if (blk_pread(blk, 0, storage, rom_size) < 0) { 246 error_setg(errp, "failed to read the initial flash content"); 247 return; 248 } 249 250 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 251 g_free(storage); 252 } 253 254 static void aspeed_board_init_flashes(AspeedSMCState *s, 255 const char *flashtype) 256 { 257 int i ; 258 259 for (i = 0; i < s->num_cs; ++i) { 260 AspeedSMCFlash *fl = &s->flashes[i]; 261 DriveInfo *dinfo = drive_get_next(IF_MTD); 262 qemu_irq cs_line; 263 264 fl->flash = qdev_new(flashtype); 265 if (dinfo) { 266 qdev_prop_set_drive(fl->flash, "drive", 267 blk_by_legacy_dinfo(dinfo)); 268 } 269 qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal); 270 271 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); 272 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 273 } 274 } 275 276 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 277 { 278 DeviceState *card; 279 280 if (!dinfo) { 281 return; 282 } 283 card = qdev_new(TYPE_SD_CARD); 284 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 285 &error_fatal); 286 qdev_realize_and_unref(card, 287 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 288 &error_fatal); 289 } 290 291 static void aspeed_machine_init(MachineState *machine) 292 { 293 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 294 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 295 AspeedSoCClass *sc; 296 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 297 ram_addr_t max_ram_size; 298 int i; 299 NICInfo *nd = &nd_table[0]; 300 301 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 302 4 * GiB); 303 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 304 305 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 306 307 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 308 309 /* 310 * This will error out if isize is not supported by memory controller. 311 */ 312 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size, 313 &error_fatal); 314 315 for (i = 0; i < sc->macs_num; i++) { 316 if ((amc->macs_mask & (1 << i)) && nd->used) { 317 qemu_check_nic_model(nd, TYPE_FTGMAC100); 318 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 319 nd++; 320 } 321 } 322 323 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 324 &error_abort); 325 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 326 &error_abort); 327 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs, 328 &error_abort); 329 object_property_set_link(OBJECT(&bmc->soc), "dram", 330 OBJECT(&bmc->ram_container), &error_abort); 331 if (machine->kernel_filename) { 332 /* 333 * When booting with a -kernel command line there is no u-boot 334 * that runs to unlock the SCU. In this case set the default to 335 * be unlocked as the kernel expects 336 */ 337 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 338 ASPEED_SCU_PROT_KEY, &error_abort); 339 } 340 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 341 342 memory_region_add_subregion(get_system_memory(), 343 sc->memmap[ASPEED_DEV_SDRAM], 344 &bmc->ram_container); 345 346 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 347 &error_abort); 348 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 349 "max_ram", max_ram_size - machine->ram_size); 350 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram); 351 352 aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ? 353 bmc->fmc_model : amc->fmc_model); 354 aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ? 355 bmc->spi_model : amc->spi_model); 356 357 /* Install first FMC flash content as a boot rom. */ 358 if (drive0) { 359 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 360 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 361 362 /* 363 * create a ROM region using the default mapping window size of 364 * the flash module. The window size is 64MB for the AST2400 365 * SoC and 128MB for the AST2500 SoC, which is twice as big as 366 * needed by the flash modules of the Aspeed machines. 367 */ 368 if (ASPEED_MACHINE(machine)->mmio_exec) { 369 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", 370 &fl->mmio, 0, fl->size); 371 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 372 boot_rom); 373 } else { 374 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", 375 fl->size, &error_abort); 376 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 377 boot_rom); 378 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); 379 } 380 } 381 382 if (machine->kernel_filename && sc->num_cpus > 1) { 383 /* With no u-boot we must set up a boot stub for the secondary CPU */ 384 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 385 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 386 0x80, &error_abort); 387 memory_region_add_subregion(get_system_memory(), 388 AST_SMP_MAILBOX_BASE, smpboot); 389 390 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 391 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 392 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 393 } 394 395 aspeed_board_binfo.ram_size = machine->ram_size; 396 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 397 aspeed_board_binfo.nb_cpus = sc->num_cpus; 398 399 if (amc->i2c_init) { 400 amc->i2c_init(bmc); 401 } 402 403 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 404 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); 405 } 406 407 if (bmc->soc.emmc.num_slots) { 408 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); 409 } 410 411 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 412 } 413 414 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 415 { 416 AspeedSoCState *soc = &bmc->soc; 417 DeviceState *dev; 418 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 419 420 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 421 * enough to provide basic RTC features. Alarms will be missing */ 422 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 423 424 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 425 eeprom_buf); 426 427 /* add a TMP423 temperature sensor */ 428 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 429 "tmp423", 0x4c)); 430 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 431 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 432 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 433 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 434 } 435 436 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 437 { 438 AspeedSoCState *soc = &bmc->soc; 439 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 440 441 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 442 eeprom_buf); 443 444 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 445 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 446 TYPE_TMP105, 0x4d); 447 448 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 449 * plugged on the I2C bus header */ 450 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 451 } 452 453 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 454 { 455 /* Start with some devices on our I2C busses */ 456 ast2500_evb_i2c_init(bmc); 457 } 458 459 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 460 { 461 AspeedSoCState *soc = &bmc->soc; 462 463 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 464 * good enough */ 465 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 466 } 467 468 static void swift_bmc_i2c_init(AspeedMachineState *bmc) 469 { 470 AspeedSoCState *soc = &bmc->soc; 471 472 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60); 473 474 /* The swift board expects a TMP275 but a TMP105 is compatible */ 475 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48); 476 /* The swift board expects a pca9551 but a pca9552 is compatible */ 477 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60); 478 479 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ 480 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32); 481 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 482 483 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 484 /* The swift board expects a pca9539 but a pca9552 is compatible */ 485 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74); 486 487 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 488 /* The swift board expects a pca9539 but a pca9552 is compatible */ 489 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552", 490 0x74); 491 492 /* The swift board expects a TMP275 but a TMP105 is compatible */ 493 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48); 494 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a); 495 } 496 497 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 498 { 499 AspeedSoCState *soc = &bmc->soc; 500 501 /* bus 2 : */ 502 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 503 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 504 /* bus 2 : pca9546 @ 0x73 */ 505 506 /* bus 3 : pca9548 @ 0x70 */ 507 508 /* bus 4 : */ 509 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 510 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 511 eeprom4_54); 512 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 513 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76); 514 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 515 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77); 516 517 /* bus 6 : */ 518 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 519 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 520 /* bus 6 : pca9546 @ 0x73 */ 521 522 /* bus 8 : */ 523 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 524 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 525 eeprom8_56); 526 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 527 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); 528 /* bus 8 : adc128d818 @ 0x1d */ 529 /* bus 8 : adc128d818 @ 0x1f */ 530 531 /* 532 * bus 13 : pca9548 @ 0x71 533 * - channel 3: 534 * - tmm421 @ 0x4c 535 * - tmp421 @ 0x4e 536 * - tmp421 @ 0x4f 537 */ 538 539 } 540 541 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 542 { 543 static const struct { 544 unsigned gpio_id; 545 LEDColor color; 546 const char *description; 547 bool gpio_polarity; 548 } pca1_leds[] = { 549 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 550 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 551 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 552 }; 553 AspeedSoCState *soc = &bmc->soc; 554 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 555 DeviceState *dev; 556 LEDState *led; 557 558 /* Bus 3: TODO bmp280@77 */ 559 /* Bus 3: TODO max31785@52 */ 560 /* Bus 3: TODO dps310@76 */ 561 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 562 qdev_prop_set_string(dev, "description", "pca1"); 563 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 564 aspeed_i2c_get_bus(&soc->i2c, 3), 565 &error_fatal); 566 567 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 568 led = led_create_simple(OBJECT(bmc), 569 pca1_leds[i].gpio_polarity, 570 pca1_leds[i].color, 571 pca1_leds[i].description); 572 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 573 qdev_get_gpio_in(DEVICE(led), 0)); 574 } 575 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 576 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 577 578 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 579 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 580 0x4a); 581 582 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 583 * good enough */ 584 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 585 586 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 587 eeprom_buf); 588 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 589 qdev_prop_set_string(dev, "description", "pca0"); 590 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 591 aspeed_i2c_get_bus(&soc->i2c, 11), 592 &error_fatal); 593 /* Bus 11: TODO ucd90160@64 */ 594 } 595 596 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 597 { 598 AspeedSoCState *soc = &bmc->soc; 599 DeviceState *dev; 600 601 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 602 "emc1413", 0x4c)); 603 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 604 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 605 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 606 607 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 608 "emc1413", 0x4c)); 609 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 610 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 611 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 612 613 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 614 "emc1413", 0x4c)); 615 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 616 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 617 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 618 619 static uint8_t eeprom_buf[2 * 1024] = { 620 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 621 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 622 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 623 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 624 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 625 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 626 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 627 }; 628 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 629 eeprom_buf); 630 } 631 632 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 633 { 634 return ASPEED_MACHINE(obj)->mmio_exec; 635 } 636 637 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 638 { 639 ASPEED_MACHINE(obj)->mmio_exec = value; 640 } 641 642 static void aspeed_machine_instance_init(Object *obj) 643 { 644 ASPEED_MACHINE(obj)->mmio_exec = false; 645 } 646 647 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 648 { 649 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 650 return g_strdup(bmc->fmc_model); 651 } 652 653 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 654 { 655 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 656 657 g_free(bmc->fmc_model); 658 bmc->fmc_model = g_strdup(value); 659 } 660 661 static char *aspeed_get_spi_model(Object *obj, Error **errp) 662 { 663 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 664 return g_strdup(bmc->spi_model); 665 } 666 667 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 668 { 669 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 670 671 g_free(bmc->spi_model); 672 bmc->spi_model = g_strdup(value); 673 } 674 675 static void aspeed_machine_class_props_init(ObjectClass *oc) 676 { 677 object_class_property_add_bool(oc, "execute-in-place", 678 aspeed_get_mmio_exec, 679 aspeed_set_mmio_exec); 680 object_class_property_set_description(oc, "execute-in-place", 681 "boot directly from CE0 flash device"); 682 683 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 684 aspeed_set_fmc_model); 685 object_class_property_set_description(oc, "fmc-model", 686 "Change the FMC Flash model"); 687 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 688 aspeed_set_spi_model); 689 object_class_property_set_description(oc, "spi-model", 690 "Change the SPI Flash model"); 691 } 692 693 static int aspeed_soc_num_cpus(const char *soc_name) 694 { 695 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 696 return sc->num_cpus; 697 } 698 699 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 700 { 701 MachineClass *mc = MACHINE_CLASS(oc); 702 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 703 704 mc->init = aspeed_machine_init; 705 mc->no_floppy = 1; 706 mc->no_cdrom = 1; 707 mc->no_parallel = 1; 708 mc->default_ram_id = "ram"; 709 amc->macs_mask = ASPEED_MAC0_ON; 710 711 aspeed_machine_class_props_init(oc); 712 } 713 714 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 715 { 716 MachineClass *mc = MACHINE_CLASS(oc); 717 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 718 719 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 720 amc->soc_name = "ast2400-a1"; 721 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 722 amc->fmc_model = "n25q256a"; 723 amc->spi_model = "mx25l25635e"; 724 amc->num_cs = 1; 725 amc->i2c_init = palmetto_bmc_i2c_init; 726 mc->default_ram_size = 256 * MiB; 727 mc->default_cpus = mc->min_cpus = mc->max_cpus = 728 aspeed_soc_num_cpus(amc->soc_name); 729 }; 730 731 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 732 void *data) 733 { 734 MachineClass *mc = MACHINE_CLASS(oc); 735 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 736 737 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 738 amc->soc_name = "ast2400-a1"; 739 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 740 amc->fmc_model = "mx25l25635e"; 741 amc->spi_model = "mx25l25635e"; 742 amc->num_cs = 1; 743 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 744 amc->i2c_init = palmetto_bmc_i2c_init; 745 mc->default_ram_size = 256 * MiB; 746 } 747 748 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 749 { 750 MachineClass *mc = MACHINE_CLASS(oc); 751 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 752 753 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 754 amc->soc_name = "ast2500-a1"; 755 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 756 amc->fmc_model = "w25q256"; 757 amc->spi_model = "mx25l25635e"; 758 amc->num_cs = 1; 759 amc->i2c_init = ast2500_evb_i2c_init; 760 mc->default_ram_size = 512 * MiB; 761 mc->default_cpus = mc->min_cpus = mc->max_cpus = 762 aspeed_soc_num_cpus(amc->soc_name); 763 }; 764 765 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 766 { 767 MachineClass *mc = MACHINE_CLASS(oc); 768 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 769 770 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 771 amc->soc_name = "ast2500-a1"; 772 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 773 amc->fmc_model = "n25q256a"; 774 amc->spi_model = "mx66l1g45g"; 775 amc->num_cs = 2; 776 amc->i2c_init = romulus_bmc_i2c_init; 777 mc->default_ram_size = 512 * MiB; 778 mc->default_cpus = mc->min_cpus = mc->max_cpus = 779 aspeed_soc_num_cpus(amc->soc_name); 780 }; 781 782 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 783 { 784 MachineClass *mc = MACHINE_CLASS(oc); 785 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 786 787 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 788 amc->soc_name = "ast2500-a1"; 789 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 790 amc->fmc_model = "mx66l1g45g"; 791 amc->spi_model = "mx66l1g45g"; 792 amc->num_cs = 2; 793 amc->i2c_init = sonorapass_bmc_i2c_init; 794 mc->default_ram_size = 512 * MiB; 795 mc->default_cpus = mc->min_cpus = mc->max_cpus = 796 aspeed_soc_num_cpus(amc->soc_name); 797 }; 798 799 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) 800 { 801 MachineClass *mc = MACHINE_CLASS(oc); 802 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 803 804 mc->desc = "OpenPOWER Swift BMC (ARM1176)"; 805 amc->soc_name = "ast2500-a1"; 806 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1; 807 amc->fmc_model = "mx66l1g45g"; 808 amc->spi_model = "mx66l1g45g"; 809 amc->num_cs = 2; 810 amc->i2c_init = swift_bmc_i2c_init; 811 mc->default_ram_size = 512 * MiB; 812 mc->default_cpus = mc->min_cpus = mc->max_cpus = 813 aspeed_soc_num_cpus(amc->soc_name); 814 }; 815 816 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 817 { 818 MachineClass *mc = MACHINE_CLASS(oc); 819 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 820 821 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 822 amc->soc_name = "ast2500-a1"; 823 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 824 amc->fmc_model = "mx25l25635e"; 825 amc->spi_model = "mx66l1g45g"; 826 amc->num_cs = 2; 827 amc->i2c_init = witherspoon_bmc_i2c_init; 828 mc->default_ram_size = 512 * MiB; 829 mc->default_cpus = mc->min_cpus = mc->max_cpus = 830 aspeed_soc_num_cpus(amc->soc_name); 831 }; 832 833 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 834 { 835 MachineClass *mc = MACHINE_CLASS(oc); 836 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 837 838 mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; 839 amc->soc_name = "ast2600-a1"; 840 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 841 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 842 amc->fmc_model = "w25q512jv"; 843 amc->spi_model = "mx66u51235f"; 844 amc->num_cs = 1; 845 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON; 846 amc->i2c_init = ast2600_evb_i2c_init; 847 mc->default_ram_size = 1 * GiB; 848 mc->default_cpus = mc->min_cpus = mc->max_cpus = 849 aspeed_soc_num_cpus(amc->soc_name); 850 }; 851 852 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 853 { 854 MachineClass *mc = MACHINE_CLASS(oc); 855 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 856 857 mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)"; 858 amc->soc_name = "ast2600-a1"; 859 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 860 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 861 amc->fmc_model = "mx66l1g45g"; 862 amc->spi_model = "mx66l1g45g"; 863 amc->num_cs = 2; 864 amc->macs_mask = ASPEED_MAC2_ON; 865 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 866 mc->default_ram_size = 1 * GiB; 867 mc->default_cpus = mc->min_cpus = mc->max_cpus = 868 aspeed_soc_num_cpus(amc->soc_name); 869 }; 870 871 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 872 { 873 MachineClass *mc = MACHINE_CLASS(oc); 874 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 875 876 mc->desc = "Bytedance G220A BMC (ARM1176)"; 877 amc->soc_name = "ast2500-a1"; 878 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 879 amc->fmc_model = "n25q512a"; 880 amc->spi_model = "mx25l25635e"; 881 amc->num_cs = 2; 882 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON; 883 amc->i2c_init = g220a_bmc_i2c_init; 884 mc->default_ram_size = 1024 * MiB; 885 mc->default_cpus = mc->min_cpus = mc->max_cpus = 886 aspeed_soc_num_cpus(amc->soc_name); 887 }; 888 889 static const TypeInfo aspeed_machine_types[] = { 890 { 891 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 892 .parent = TYPE_ASPEED_MACHINE, 893 .class_init = aspeed_machine_palmetto_class_init, 894 }, { 895 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 896 .parent = TYPE_ASPEED_MACHINE, 897 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 898 }, { 899 .name = MACHINE_TYPE_NAME("ast2500-evb"), 900 .parent = TYPE_ASPEED_MACHINE, 901 .class_init = aspeed_machine_ast2500_evb_class_init, 902 }, { 903 .name = MACHINE_TYPE_NAME("romulus-bmc"), 904 .parent = TYPE_ASPEED_MACHINE, 905 .class_init = aspeed_machine_romulus_class_init, 906 }, { 907 .name = MACHINE_TYPE_NAME("swift-bmc"), 908 .parent = TYPE_ASPEED_MACHINE, 909 .class_init = aspeed_machine_swift_class_init, 910 }, { 911 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 912 .parent = TYPE_ASPEED_MACHINE, 913 .class_init = aspeed_machine_sonorapass_class_init, 914 }, { 915 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 916 .parent = TYPE_ASPEED_MACHINE, 917 .class_init = aspeed_machine_witherspoon_class_init, 918 }, { 919 .name = MACHINE_TYPE_NAME("ast2600-evb"), 920 .parent = TYPE_ASPEED_MACHINE, 921 .class_init = aspeed_machine_ast2600_evb_class_init, 922 }, { 923 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 924 .parent = TYPE_ASPEED_MACHINE, 925 .class_init = aspeed_machine_tacoma_class_init, 926 }, { 927 .name = MACHINE_TYPE_NAME("g220a-bmc"), 928 .parent = TYPE_ASPEED_MACHINE, 929 .class_init = aspeed_machine_g220a_class_init, 930 }, { 931 .name = TYPE_ASPEED_MACHINE, 932 .parent = TYPE_MACHINE, 933 .instance_size = sizeof(AspeedMachineState), 934 .instance_init = aspeed_machine_instance_init, 935 .class_size = sizeof(AspeedMachineClass), 936 .class_init = aspeed_machine_class_init, 937 .abstract = true, 938 } 939 }; 940 941 DEFINE_TYPES(aspeed_machine_types) 942