xref: /openbmc/qemu/hw/arm/aspeed.c (revision 3d9569b8)
1 /*
2  * OpenPOWER Palmetto BMC
3  *
4  * Andrew Jeffery <andrew@aj.id.au>
5  *
6  * Copyright 2016 IBM Corp.
7  *
8  * This code is licensed under the GPL version 2 or later.  See
9  * the COPYING file in the top-level directory.
10  */
11 
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "cpu.h"
15 #include "exec/address-spaces.h"
16 #include "hw/arm/boot.h"
17 #include "hw/arm/aspeed.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/boards.h"
20 #include "hw/i2c/smbus_eeprom.h"
21 #include "hw/misc/pca9552.h"
22 #include "hw/misc/tmp105.h"
23 #include "qemu/log.h"
24 #include "sysemu/block-backend.h"
25 #include "hw/loader.h"
26 #include "qemu/error-report.h"
27 #include "qemu/units.h"
28 
29 static struct arm_boot_info aspeed_board_binfo = {
30     .board_id = -1, /* device-tree-only board */
31     .nb_cpus = 1,
32 };
33 
34 struct AspeedBoardState {
35     AspeedSoCState soc;
36     MemoryRegion ram;
37     MemoryRegion max_ram;
38 };
39 
40 /* Palmetto hardware value: 0x120CE416 */
41 #define PALMETTO_BMC_HW_STRAP1 (                                        \
42         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) |               \
43         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
44         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
45         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
46         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
47         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
48         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
49         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
50         SCU_HW_STRAP_SPI_WIDTH |                                        \
51         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
52         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
53 
54 /* AST2500 evb hardware value: 0xF100C2E6 */
55 #define AST2500_EVB_HW_STRAP1 ((                                        \
56         AST2500_HW_STRAP1_DEFAULTS |                                    \
57         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
58         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
59         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
60         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
61         SCU_HW_STRAP_MAC1_RGMII |                                       \
62         SCU_HW_STRAP_MAC0_RGMII) &                                      \
63         ~SCU_HW_STRAP_2ND_BOOT_WDT)
64 
65 /* Romulus hardware value: 0xF10AD206 */
66 #define ROMULUS_BMC_HW_STRAP1 (                                         \
67         AST2500_HW_STRAP1_DEFAULTS |                                    \
68         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
69         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
70         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
71         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
72         SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \
73         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
74 
75 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
76 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
77 
78 /*
79  * The max ram region is for firmwares that scan the address space
80  * with load/store to guess how much RAM the SoC has.
81  */
82 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
83 {
84     return 0;
85 }
86 
87 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
88                            unsigned size)
89 {
90     /* Discard writes */
91 }
92 
93 static const MemoryRegionOps max_ram_ops = {
94     .read = max_ram_read,
95     .write = max_ram_write,
96     .endianness = DEVICE_NATIVE_ENDIAN,
97 };
98 
99 #define FIRMWARE_ADDR 0x0
100 
101 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
102                            Error **errp)
103 {
104     BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
105     uint8_t *storage;
106     int64_t size;
107 
108     /* The block backend size should have already been 'validated' by
109      * the creation of the m25p80 object.
110      */
111     size = blk_getlength(blk);
112     if (size <= 0) {
113         error_setg(errp, "failed to get flash size");
114         return;
115     }
116 
117     if (rom_size > size) {
118         rom_size = size;
119     }
120 
121     storage = g_new0(uint8_t, rom_size);
122     if (blk_pread(blk, 0, storage, rom_size) < 0) {
123         error_setg(errp, "failed to read the initial flash content");
124         return;
125     }
126 
127     rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
128     g_free(storage);
129 }
130 
131 static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
132                                       Error **errp)
133 {
134     int i ;
135 
136     for (i = 0; i < s->num_cs; ++i) {
137         AspeedSMCFlash *fl = &s->flashes[i];
138         DriveInfo *dinfo = drive_get_next(IF_MTD);
139         qemu_irq cs_line;
140 
141         fl->flash = ssi_create_slave_no_init(s->spi, flashtype);
142         if (dinfo) {
143             qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo),
144                                 errp);
145         }
146         qdev_init_nofail(fl->flash);
147 
148         cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
149         sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
150     }
151 }
152 
153 static void aspeed_board_init(MachineState *machine,
154                               const AspeedBoardConfig *cfg)
155 {
156     AspeedBoardState *bmc;
157     AspeedSoCClass *sc;
158     DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
159     ram_addr_t max_ram_size;
160 
161     bmc = g_new0(AspeedBoardState, 1);
162     object_initialize_child(OBJECT(machine), "soc", &bmc->soc,
163                             (sizeof(bmc->soc)), cfg->soc_name, &error_abort,
164                             NULL);
165 
166     sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
167 
168     object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size",
169                              &error_abort);
170     object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1",
171                             &error_abort);
172     object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs",
173                             &error_abort);
174     if (machine->kernel_filename) {
175         /*
176          * When booting with a -kernel command line there is no u-boot
177          * that runs to unlock the SCU. In this case set the default to
178          * be unlocked as the kernel expects
179          */
180         object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY,
181                                 "hw-prot-key", &error_abort);
182     }
183     object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
184                              &error_abort);
185 
186     /*
187      * Allocate RAM after the memory controller has checked the size
188      * was valid. If not, a default value is used.
189      */
190     ram_size = object_property_get_uint(OBJECT(&bmc->soc), "ram-size",
191                                         &error_abort);
192 
193     memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
194     memory_region_add_subregion(get_system_memory(), sc->info->sdram_base,
195                                 &bmc->ram);
196     object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
197                                    &error_abort);
198 
199     max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
200                                             &error_abort);
201     memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
202                           "max_ram", max_ram_size  - ram_size);
203     memory_region_add_subregion(get_system_memory(),
204                                 sc->info->sdram_base + ram_size,
205                                 &bmc->max_ram);
206 
207     aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
208     aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);
209 
210     /* Install first FMC flash content as a boot rom. */
211     if (drive0) {
212         AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
213         MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
214 
215         /*
216          * create a ROM region using the default mapping window size of
217          * the flash module. The window size is 64MB for the AST2400
218          * SoC and 128MB for the AST2500 SoC, which is twice as big as
219          * needed by the flash modules of the Aspeed machines.
220          */
221         memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
222                                fl->size, &error_abort);
223         memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
224                                     boot_rom);
225         write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
226     }
227 
228     aspeed_board_binfo.kernel_filename = machine->kernel_filename;
229     aspeed_board_binfo.initrd_filename = machine->initrd_filename;
230     aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline;
231     aspeed_board_binfo.ram_size = ram_size;
232     aspeed_board_binfo.loader_start = sc->info->sdram_base;
233 
234     if (cfg->i2c_init) {
235         cfg->i2c_init(bmc);
236     }
237 
238     arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo);
239 }
240 
241 static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
242 {
243     AspeedSoCState *soc = &bmc->soc;
244     DeviceState *dev;
245     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
246 
247     /* The palmetto platform expects a ds3231 RTC but a ds1338 is
248      * enough to provide basic RTC features. Alarms will be missing */
249     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
250 
251     smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), 0x50,
252                           eeprom_buf);
253 
254     /* add a TMP423 temperature sensor */
255     dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2),
256                            "tmp423", 0x4c);
257     object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort);
258     object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort);
259     object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort);
260     object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort);
261 }
262 
263 static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
264 {
265     AspeedSoCState *soc = &bmc->soc;
266     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
267 
268     smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), 0x50,
269                           eeprom_buf);
270 
271     /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
272     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7),
273                      TYPE_TMP105, 0x4d);
274 
275     /* The AST2500 EVB does not have an RTC. Let's pretend that one is
276      * plugged on the I2C bus header */
277     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
278 }
279 
280 static void romulus_bmc_i2c_init(AspeedBoardState *bmc)
281 {
282     AspeedSoCState *soc = &bmc->soc;
283 
284     /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
285      * good enough */
286     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
287 }
288 
289 static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
290 {
291     AspeedSoCState *soc = &bmc->soc;
292     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
293 
294     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA9552,
295                      0x60);
296 
297     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c);
298     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c);
299 
300     /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
301     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), TYPE_TMP105,
302                      0x4a);
303 
304     /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
305      * good enough */
306     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
307 
308     smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51,
309                           eeprom_buf);
310     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA9552,
311                      0x60);
312 }
313 
314 static void aspeed_machine_init(MachineState *machine)
315 {
316     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
317 
318     aspeed_board_init(machine, amc->board);
319 }
320 
321 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
322 {
323     MachineClass *mc = MACHINE_CLASS(oc);
324     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
325     const AspeedBoardConfig *board = data;
326 
327     mc->desc = board->desc;
328     mc->init = aspeed_machine_init;
329     mc->max_cpus = 1;
330     mc->no_sdcard = 1;
331     mc->no_floppy = 1;
332     mc->no_cdrom = 1;
333     mc->no_parallel = 1;
334     if (board->ram) {
335         mc->default_ram_size = board->ram;
336     }
337     amc->board = board;
338 }
339 
340 static const TypeInfo aspeed_machine_type = {
341     .name = TYPE_ASPEED_MACHINE,
342     .parent = TYPE_MACHINE,
343     .instance_size = sizeof(AspeedMachine),
344     .class_size = sizeof(AspeedMachineClass),
345     .abstract = true,
346 };
347 
348 static const AspeedBoardConfig aspeed_boards[] = {
349     {
350         .name      = MACHINE_TYPE_NAME("palmetto-bmc"),
351         .desc      = "OpenPOWER Palmetto BMC (ARM926EJ-S)",
352         .soc_name  = "ast2400-a1",
353         .hw_strap1 = PALMETTO_BMC_HW_STRAP1,
354         .fmc_model = "n25q256a",
355         .spi_model = "mx25l25635e",
356         .num_cs    = 1,
357         .i2c_init  = palmetto_bmc_i2c_init,
358         .ram       = 256 * MiB,
359     }, {
360         .name      = MACHINE_TYPE_NAME("ast2500-evb"),
361         .desc      = "Aspeed AST2500 EVB (ARM1176)",
362         .soc_name  = "ast2500-a1",
363         .hw_strap1 = AST2500_EVB_HW_STRAP1,
364         .fmc_model = "w25q256",
365         .spi_model = "mx25l25635e",
366         .num_cs    = 1,
367         .i2c_init  = ast2500_evb_i2c_init,
368         .ram       = 512 * MiB,
369     }, {
370         .name      = MACHINE_TYPE_NAME("romulus-bmc"),
371         .desc      = "OpenPOWER Romulus BMC (ARM1176)",
372         .soc_name  = "ast2500-a1",
373         .hw_strap1 = ROMULUS_BMC_HW_STRAP1,
374         .fmc_model = "n25q256a",
375         .spi_model = "mx66l1g45g",
376         .num_cs    = 2,
377         .i2c_init  = romulus_bmc_i2c_init,
378         .ram       = 512 * MiB,
379     }, {
380         .name      = MACHINE_TYPE_NAME("witherspoon-bmc"),
381         .desc      = "OpenPOWER Witherspoon BMC (ARM1176)",
382         .soc_name  = "ast2500-a1",
383         .hw_strap1 = WITHERSPOON_BMC_HW_STRAP1,
384         .fmc_model = "mx25l25635e",
385         .spi_model = "mx66l1g45g",
386         .num_cs    = 2,
387         .i2c_init  = witherspoon_bmc_i2c_init,
388         .ram       = 512 * MiB,
389     },
390 };
391 
392 static void aspeed_machine_types(void)
393 {
394     int i;
395 
396     type_register_static(&aspeed_machine_type);
397     for (i = 0; i < ARRAY_SIZE(aspeed_boards); ++i) {
398         TypeInfo ti = {
399             .name       = aspeed_boards[i].name,
400             .parent     = TYPE_ASPEED_MACHINE,
401             .class_init = aspeed_machine_class_init,
402             .class_data = (void *)&aspeed_boards[i],
403         };
404         type_register(&ti);
405     }
406 }
407 
408 type_init(aspeed_machine_types)
409