1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/i2c/i2c_mux_pca954x.h" 19 #include "hw/i2c/smbus_eeprom.h" 20 #include "hw/misc/pca9552.h" 21 #include "hw/nvram/eeprom_at24c.h" 22 #include "hw/sensor/tmp105.h" 23 #include "hw/misc/led.h" 24 #include "hw/qdev-properties.h" 25 #include "sysemu/block-backend.h" 26 #include "sysemu/reset.h" 27 #include "hw/loader.h" 28 #include "qemu/error-report.h" 29 #include "qemu/units.h" 30 #include "hw/qdev-clock.h" 31 #include "sysemu/sysemu.h" 32 33 static struct arm_boot_info aspeed_board_binfo = { 34 .board_id = -1, /* device-tree-only board */ 35 }; 36 37 struct AspeedMachineState { 38 /* Private */ 39 MachineState parent_obj; 40 /* Public */ 41 42 AspeedSoCState soc; 43 bool mmio_exec; 44 char *fmc_model; 45 char *spi_model; 46 }; 47 48 /* Palmetto hardware value: 0x120CE416 */ 49 #define PALMETTO_BMC_HW_STRAP1 ( \ 50 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 51 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 52 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 53 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 54 SCU_HW_STRAP_VGA_CLASS_CODE | \ 55 SCU_HW_STRAP_LPC_RESET_PIN | \ 56 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 57 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 58 SCU_HW_STRAP_SPI_WIDTH | \ 59 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 60 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 61 62 /* TODO: Find the actual hardware value */ 63 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 64 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 65 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 66 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 67 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 68 SCU_HW_STRAP_VGA_CLASS_CODE | \ 69 SCU_HW_STRAP_LPC_RESET_PIN | \ 70 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 71 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 72 SCU_HW_STRAP_SPI_WIDTH | \ 73 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 74 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 75 76 /* TODO: Find the actual hardware value */ 77 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 78 AST2500_HW_STRAP1_DEFAULTS | \ 79 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 80 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 81 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 82 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 83 SCU_HW_STRAP_SPI_WIDTH | \ 84 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 85 86 /* AST2500 evb hardware value: 0xF100C2E6 */ 87 #define AST2500_EVB_HW_STRAP1 (( \ 88 AST2500_HW_STRAP1_DEFAULTS | \ 89 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 90 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 91 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 92 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 93 SCU_HW_STRAP_MAC1_RGMII | \ 94 SCU_HW_STRAP_MAC0_RGMII) & \ 95 ~SCU_HW_STRAP_2ND_BOOT_WDT) 96 97 /* Romulus hardware value: 0xF10AD206 */ 98 #define ROMULUS_BMC_HW_STRAP1 ( \ 99 AST2500_HW_STRAP1_DEFAULTS | \ 100 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 101 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 102 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 103 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 104 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 105 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 106 107 /* Sonorapass hardware value: 0xF100D216 */ 108 #define SONORAPASS_BMC_HW_STRAP1 ( \ 109 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 110 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 111 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 112 SCU_AST2500_HW_STRAP_RESERVED28 | \ 113 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 114 SCU_HW_STRAP_VGA_CLASS_CODE | \ 115 SCU_HW_STRAP_LPC_RESET_PIN | \ 116 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 117 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 118 SCU_HW_STRAP_VGA_BIOS_ROM | \ 119 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 120 SCU_AST2500_HW_STRAP_RESERVED1) 121 122 #define G220A_BMC_HW_STRAP1 ( \ 123 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 124 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 125 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 126 SCU_AST2500_HW_STRAP_RESERVED28 | \ 127 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 128 SCU_HW_STRAP_2ND_BOOT_WDT | \ 129 SCU_HW_STRAP_VGA_CLASS_CODE | \ 130 SCU_HW_STRAP_LPC_RESET_PIN | \ 131 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 132 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 133 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 134 SCU_AST2500_HW_STRAP_RESERVED1) 135 136 /* FP5280G2 hardware value: 0XF100D286 */ 137 #define FP5280G2_BMC_HW_STRAP1 ( \ 138 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 139 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 140 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 141 SCU_AST2500_HW_STRAP_RESERVED28 | \ 142 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 143 SCU_HW_STRAP_VGA_CLASS_CODE | \ 144 SCU_HW_STRAP_LPC_RESET_PIN | \ 145 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 146 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 147 SCU_HW_STRAP_MAC1_RGMII | \ 148 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 149 SCU_AST2500_HW_STRAP_RESERVED1) 150 151 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 152 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 153 154 /* Quanta-Q71l hardware value */ 155 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 156 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 157 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 158 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 159 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 160 SCU_HW_STRAP_VGA_CLASS_CODE | \ 161 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 162 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 163 SCU_HW_STRAP_SPI_WIDTH | \ 164 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 165 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 166 167 /* AST2600 evb hardware value */ 168 #define AST2600_EVB_HW_STRAP1 0x000000C0 169 #define AST2600_EVB_HW_STRAP2 0x00000003 170 171 /* Tacoma hardware value */ 172 #define TACOMA_BMC_HW_STRAP1 0x00000000 173 #define TACOMA_BMC_HW_STRAP2 0x00000040 174 175 /* Rainier hardware value: (QEMU prototype) */ 176 #define RAINIER_BMC_HW_STRAP1 0x00422016 177 #define RAINIER_BMC_HW_STRAP2 0x80000848 178 179 /* Fuji hardware value */ 180 #define FUJI_BMC_HW_STRAP1 0x00000000 181 #define FUJI_BMC_HW_STRAP2 0x00000000 182 183 /* Bletchley hardware value */ 184 /* TODO: Leave same as EVB for now. */ 185 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 186 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 187 188 /* Qualcomm DC-SCM hardware value */ 189 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 190 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 191 192 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 193 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 194 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 195 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 196 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 197 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 198 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 199 200 static void aspeed_write_smpboot(ARMCPU *cpu, 201 const struct arm_boot_info *info) 202 { 203 static const uint32_t poll_mailbox_ready[] = { 204 /* 205 * r2 = per-cpu go sign value 206 * r1 = AST_SMP_MBOX_FIELD_ENTRY 207 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 208 */ 209 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 210 0xe21000ff, /* ands r0, r0, #255 */ 211 0xe59f201c, /* ldr r2, [pc, #28] */ 212 0xe1822000, /* orr r2, r2, r0 */ 213 214 0xe59f1018, /* ldr r1, [pc, #24] */ 215 0xe59f0018, /* ldr r0, [pc, #24] */ 216 217 0xe320f002, /* wfe */ 218 0xe5904000, /* ldr r4, [r0] */ 219 0xe1520004, /* cmp r2, r4 */ 220 0x1afffffb, /* bne <wfe> */ 221 0xe591f000, /* ldr pc, [r1] */ 222 AST_SMP_MBOX_GOSIGN, 223 AST_SMP_MBOX_FIELD_ENTRY, 224 AST_SMP_MBOX_FIELD_GOSIGN, 225 }; 226 227 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 228 sizeof(poll_mailbox_ready), 229 info->smp_loader_start); 230 } 231 232 static void aspeed_reset_secondary(ARMCPU *cpu, 233 const struct arm_boot_info *info) 234 { 235 AddressSpace *as = arm_boot_address_space(cpu, info); 236 CPUState *cs = CPU(cpu); 237 238 /* info->smp_bootreg_addr */ 239 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 240 MEMTXATTRS_UNSPECIFIED, NULL); 241 cpu_set_pc(cs, info->smp_loader_start); 242 } 243 244 #define FIRMWARE_ADDR 0x0 245 246 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 247 Error **errp) 248 { 249 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 250 g_autofree void *storage = NULL; 251 int64_t size; 252 253 /* The block backend size should have already been 'validated' by 254 * the creation of the m25p80 object. 255 */ 256 size = blk_getlength(blk); 257 if (size <= 0) { 258 error_setg(errp, "failed to get flash size"); 259 return; 260 } 261 262 if (rom_size > size) { 263 rom_size = size; 264 } 265 266 storage = g_malloc0(rom_size); 267 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 268 error_setg(errp, "failed to read the initial flash content"); 269 return; 270 } 271 272 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 273 } 274 275 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 276 unsigned int count, int unit0) 277 { 278 int i; 279 280 if (!flashtype) { 281 return; 282 } 283 284 for (i = 0; i < count; ++i) { 285 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 286 qemu_irq cs_line; 287 DeviceState *dev; 288 289 dev = qdev_new(flashtype); 290 if (dinfo) { 291 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 292 } 293 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 294 295 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); 296 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 297 } 298 } 299 300 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 301 { 302 DeviceState *card; 303 304 if (!dinfo) { 305 return; 306 } 307 card = qdev_new(TYPE_SD_CARD); 308 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 309 &error_fatal); 310 qdev_realize_and_unref(card, 311 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 312 &error_fatal); 313 } 314 315 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 316 { 317 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 318 AspeedSoCState *s = &bmc->soc; 319 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 320 321 aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0)); 322 for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) { 323 if (uart == amc->uart_default) { 324 continue; 325 } 326 aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); 327 } 328 } 329 330 static void aspeed_machine_init(MachineState *machine) 331 { 332 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 333 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 334 AspeedSoCClass *sc; 335 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 336 int i; 337 NICInfo *nd = &nd_table[0]; 338 339 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 340 341 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 342 343 /* 344 * This will error out if the RAM size is not supported by the 345 * memory controller of the SoC. 346 */ 347 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size, 348 &error_fatal); 349 350 for (i = 0; i < sc->macs_num; i++) { 351 if ((amc->macs_mask & (1 << i)) && nd->used) { 352 qemu_check_nic_model(nd, TYPE_FTGMAC100); 353 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 354 nd++; 355 } 356 } 357 358 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 359 &error_abort); 360 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 361 &error_abort); 362 object_property_set_link(OBJECT(&bmc->soc), "memory", 363 OBJECT(get_system_memory()), &error_abort); 364 object_property_set_link(OBJECT(&bmc->soc), "dram", 365 OBJECT(machine->ram), &error_abort); 366 if (machine->kernel_filename) { 367 /* 368 * When booting with a -kernel command line there is no u-boot 369 * that runs to unlock the SCU. In this case set the default to 370 * be unlocked as the kernel expects 371 */ 372 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 373 ASPEED_SCU_PROT_KEY, &error_abort); 374 } 375 connect_serial_hds_to_uarts(bmc); 376 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 377 378 aspeed_board_init_flashes(&bmc->soc.fmc, 379 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 380 amc->num_cs, 0); 381 aspeed_board_init_flashes(&bmc->soc.spi[0], 382 bmc->spi_model ? bmc->spi_model : amc->spi_model, 383 1, amc->num_cs); 384 385 /* Install first FMC flash content as a boot rom. */ 386 if (drive0) { 387 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 388 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 389 uint64_t size = memory_region_size(&fl->mmio); 390 391 /* 392 * create a ROM region using the default mapping window size of 393 * the flash module. The window size is 64MB for the AST2400 394 * SoC and 128MB for the AST2500 SoC, which is twice as big as 395 * needed by the flash modules of the Aspeed machines. 396 */ 397 if (ASPEED_MACHINE(machine)->mmio_exec) { 398 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", 399 &fl->mmio, 0, size); 400 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 401 boot_rom); 402 } else { 403 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", 404 size, &error_abort); 405 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 406 boot_rom); 407 write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort); 408 } 409 } 410 411 if (machine->kernel_filename && sc->num_cpus > 1) { 412 /* With no u-boot we must set up a boot stub for the secondary CPU */ 413 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 414 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 415 0x80, &error_abort); 416 memory_region_add_subregion(get_system_memory(), 417 AST_SMP_MAILBOX_BASE, smpboot); 418 419 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 420 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 421 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 422 } 423 424 aspeed_board_binfo.ram_size = machine->ram_size; 425 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 426 427 if (amc->i2c_init) { 428 amc->i2c_init(bmc); 429 } 430 431 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 432 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], 433 drive_get(IF_SD, 0, i)); 434 } 435 436 if (bmc->soc.emmc.num_slots) { 437 sdhci_attach_drive(&bmc->soc.emmc.slots[0], 438 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots)); 439 } 440 441 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 442 } 443 444 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 445 { 446 AspeedSoCState *soc = &bmc->soc; 447 DeviceState *dev; 448 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 449 450 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 451 * enough to provide basic RTC features. Alarms will be missing */ 452 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 453 454 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 455 eeprom_buf); 456 457 /* add a TMP423 temperature sensor */ 458 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 459 "tmp423", 0x4c)); 460 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 461 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 462 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 463 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 464 } 465 466 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 467 { 468 AspeedSoCState *soc = &bmc->soc; 469 470 /* 471 * The quanta-q71l platform expects tmp75s which are compatible with 472 * tmp105s. 473 */ 474 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 475 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 476 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 477 478 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 479 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 480 /* TODO: Add Memory Riser i2c mux and eeproms. */ 481 482 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 483 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 484 485 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 486 487 /* i2c-7 */ 488 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 489 /* - i2c@0: pmbus@59 */ 490 /* - i2c@1: pmbus@58 */ 491 /* - i2c@2: pmbus@58 */ 492 /* - i2c@3: pmbus@59 */ 493 494 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 495 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 496 } 497 498 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 499 { 500 AspeedSoCState *soc = &bmc->soc; 501 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 502 503 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 504 eeprom_buf); 505 506 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 507 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 508 TYPE_TMP105, 0x4d); 509 } 510 511 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 512 { 513 AspeedSoCState *soc = &bmc->soc; 514 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 515 516 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 517 eeprom_buf); 518 519 /* LM75 is compatible with TMP105 driver */ 520 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 521 TYPE_TMP105, 0x4d); 522 } 523 524 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 525 { 526 AspeedSoCState *soc = &bmc->soc; 527 528 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 529 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 530 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 531 } 532 533 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 534 { 535 AspeedSoCState *soc = &bmc->soc; 536 537 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 538 * good enough */ 539 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 540 } 541 542 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 543 { 544 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 545 TYPE_PCA9552, addr); 546 } 547 548 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 549 { 550 AspeedSoCState *soc = &bmc->soc; 551 552 /* bus 2 : */ 553 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 554 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 555 /* bus 2 : pca9546 @ 0x73 */ 556 557 /* bus 3 : pca9548 @ 0x70 */ 558 559 /* bus 4 : */ 560 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 561 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 562 eeprom4_54); 563 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 564 create_pca9552(soc, 4, 0x76); 565 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 566 create_pca9552(soc, 4, 0x77); 567 568 /* bus 6 : */ 569 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 570 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 571 /* bus 6 : pca9546 @ 0x73 */ 572 573 /* bus 8 : */ 574 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 575 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 576 eeprom8_56); 577 create_pca9552(soc, 8, 0x60); 578 create_pca9552(soc, 8, 0x61); 579 /* bus 8 : adc128d818 @ 0x1d */ 580 /* bus 8 : adc128d818 @ 0x1f */ 581 582 /* 583 * bus 13 : pca9548 @ 0x71 584 * - channel 3: 585 * - tmm421 @ 0x4c 586 * - tmp421 @ 0x4e 587 * - tmp421 @ 0x4f 588 */ 589 590 } 591 592 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 593 { 594 static const struct { 595 unsigned gpio_id; 596 LEDColor color; 597 const char *description; 598 bool gpio_polarity; 599 } pca1_leds[] = { 600 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 601 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 602 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 603 }; 604 AspeedSoCState *soc = &bmc->soc; 605 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 606 DeviceState *dev; 607 LEDState *led; 608 609 /* Bus 3: TODO bmp280@77 */ 610 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 611 qdev_prop_set_string(dev, "description", "pca1"); 612 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 613 aspeed_i2c_get_bus(&soc->i2c, 3), 614 &error_fatal); 615 616 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 617 led = led_create_simple(OBJECT(bmc), 618 pca1_leds[i].gpio_polarity, 619 pca1_leds[i].color, 620 pca1_leds[i].description); 621 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 622 qdev_get_gpio_in(DEVICE(led), 0)); 623 } 624 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 625 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 626 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 627 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 628 629 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 630 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 631 0x4a); 632 633 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 634 * good enough */ 635 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 636 637 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 638 eeprom_buf); 639 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 640 qdev_prop_set_string(dev, "description", "pca0"); 641 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 642 aspeed_i2c_get_bus(&soc->i2c, 11), 643 &error_fatal); 644 /* Bus 11: TODO ucd90160@64 */ 645 } 646 647 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 648 { 649 AspeedSoCState *soc = &bmc->soc; 650 DeviceState *dev; 651 652 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 653 "emc1413", 0x4c)); 654 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 655 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 656 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 657 658 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 659 "emc1413", 0x4c)); 660 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 661 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 662 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 663 664 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 665 "emc1413", 0x4c)); 666 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 667 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 668 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 669 670 static uint8_t eeprom_buf[2 * 1024] = { 671 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 672 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 673 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 674 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 675 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 676 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 677 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 678 }; 679 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 680 eeprom_buf); 681 } 682 683 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 684 { 685 AspeedSoCState *soc = &bmc->soc; 686 I2CSlave *i2c_mux; 687 688 /* The at24c256 */ 689 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 690 691 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 692 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 693 0x48); 694 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 695 0x49); 696 697 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 698 "pca9546", 0x70); 699 /* It expects a TMP112 but a TMP105 is compatible */ 700 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 701 0x4a); 702 703 /* It expects a ds3232 but a ds1338 is good enough */ 704 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 705 706 /* It expects a pca9555 but a pca9552 is compatible */ 707 create_pca9552(soc, 8, 0x30); 708 } 709 710 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 711 { 712 AspeedSoCState *soc = &bmc->soc; 713 I2CSlave *i2c_mux; 714 715 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 716 717 create_pca9552(soc, 3, 0x61); 718 719 /* The rainier expects a TMP275 but a TMP105 is compatible */ 720 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 721 0x48); 722 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 723 0x49); 724 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 725 0x4a); 726 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 727 "pca9546", 0x70); 728 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 729 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 730 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 731 create_pca9552(soc, 4, 0x60); 732 733 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 734 0x48); 735 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 736 0x49); 737 create_pca9552(soc, 5, 0x60); 738 create_pca9552(soc, 5, 0x61); 739 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 740 "pca9546", 0x70); 741 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 742 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 743 744 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 745 0x48); 746 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 747 0x4a); 748 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 749 0x4b); 750 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 751 "pca9546", 0x70); 752 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 753 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 754 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 755 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 756 757 create_pca9552(soc, 7, 0x30); 758 create_pca9552(soc, 7, 0x31); 759 create_pca9552(soc, 7, 0x32); 760 create_pca9552(soc, 7, 0x33); 761 create_pca9552(soc, 7, 0x60); 762 create_pca9552(soc, 7, 0x61); 763 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 764 /* Bus 7: TODO si7021-a20@20 */ 765 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 766 0x48); 767 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 768 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 769 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 770 771 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 772 0x48); 773 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 774 0x4a); 775 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB); 776 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB); 777 create_pca9552(soc, 8, 0x60); 778 create_pca9552(soc, 8, 0x61); 779 /* Bus 8: ucd90320@11 */ 780 /* Bus 8: ucd90320@b */ 781 /* Bus 8: ucd90320@c */ 782 783 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 784 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 785 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 786 787 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 788 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 789 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 790 791 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 792 0x48); 793 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 794 0x49); 795 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 796 "pca9546", 0x70); 797 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 798 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 799 create_pca9552(soc, 11, 0x60); 800 801 802 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 803 create_pca9552(soc, 13, 0x60); 804 805 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 806 create_pca9552(soc, 14, 0x60); 807 808 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 809 create_pca9552(soc, 15, 0x60); 810 } 811 812 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 813 I2CBus **channels) 814 { 815 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 816 for (int i = 0; i < 8; i++) { 817 channels[i] = pca954x_i2c_get_bus(mux, i); 818 } 819 } 820 821 #define TYPE_LM75 TYPE_TMP105 822 #define TYPE_TMP75 TYPE_TMP105 823 #define TYPE_TMP422 "tmp422" 824 825 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 826 { 827 AspeedSoCState *soc = &bmc->soc; 828 I2CBus *i2c[144] = {}; 829 830 for (int i = 0; i < 16; i++) { 831 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 832 } 833 I2CBus *i2c180 = i2c[2]; 834 I2CBus *i2c480 = i2c[8]; 835 I2CBus *i2c600 = i2c[11]; 836 837 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 838 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 839 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 840 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 841 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 842 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 843 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 844 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 845 for (int i = 0; i < 8; i++) { 846 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 847 } 848 849 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 850 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 851 852 at24c_eeprom_init(i2c[19], 0x52, 64 * KiB); 853 at24c_eeprom_init(i2c[20], 0x50, 2 * KiB); 854 at24c_eeprom_init(i2c[22], 0x52, 2 * KiB); 855 856 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 857 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 858 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 859 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 860 861 at24c_eeprom_init(i2c[8], 0x51, 64 * KiB); 862 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 863 864 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 865 at24c_eeprom_init(i2c[50], 0x52, 64 * KiB); 866 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 867 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 868 869 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 870 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 871 872 at24c_eeprom_init(i2c[65], 0x53, 64 * KiB); 873 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 874 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 875 at24c_eeprom_init(i2c[68], 0x52, 64 * KiB); 876 at24c_eeprom_init(i2c[69], 0x52, 64 * KiB); 877 at24c_eeprom_init(i2c[70], 0x52, 64 * KiB); 878 at24c_eeprom_init(i2c[71], 0x52, 64 * KiB); 879 880 at24c_eeprom_init(i2c[73], 0x53, 64 * KiB); 881 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 882 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 883 at24c_eeprom_init(i2c[76], 0x52, 64 * KiB); 884 at24c_eeprom_init(i2c[77], 0x52, 64 * KiB); 885 at24c_eeprom_init(i2c[78], 0x52, 64 * KiB); 886 at24c_eeprom_init(i2c[79], 0x52, 64 * KiB); 887 at24c_eeprom_init(i2c[28], 0x50, 2 * KiB); 888 889 for (int i = 0; i < 8; i++) { 890 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 891 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 892 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 893 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 894 } 895 } 896 897 #define TYPE_TMP421 "tmp421" 898 899 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 900 { 901 AspeedSoCState *soc = &bmc->soc; 902 I2CBus *i2c[13] = {}; 903 for (int i = 0; i < 13; i++) { 904 if ((i == 8) || (i == 11)) { 905 continue; 906 } 907 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 908 } 909 910 /* Bus 0 - 5 all have the same config. */ 911 for (int i = 0; i < 6; i++) { 912 /* Missing model: ti,ina230 @ 0x45 */ 913 /* Missing model: mps,mp5023 @ 0x40 */ 914 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 915 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 916 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 917 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 918 /* Missing model: fsc,fusb302 @ 0x22 */ 919 } 920 921 /* Bus 6 */ 922 at24c_eeprom_init(i2c[6], 0x56, 65536); 923 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 924 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 925 926 927 /* Bus 7 */ 928 at24c_eeprom_init(i2c[7], 0x54, 65536); 929 930 /* Bus 9 */ 931 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 932 933 /* Bus 10 */ 934 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 935 /* Missing model: ti,hdc1080 @ 0x40 */ 936 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 937 938 /* Bus 12 */ 939 /* Missing model: adi,adm1278 @ 0x11 */ 940 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 941 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 942 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 943 } 944 945 static void fby35_i2c_init(AspeedMachineState *bmc) 946 { 947 AspeedSoCState *soc = &bmc->soc; 948 I2CBus *i2c[16]; 949 950 for (int i = 0; i < 16; i++) { 951 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 952 } 953 954 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 955 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 956 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 957 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 958 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 959 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 960 961 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 962 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 963 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 964 fby35_nic_fruid_len); 965 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 966 fby35_bb_fruid_len); 967 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 968 fby35_bmc_fruid_len); 969 970 /* 971 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 972 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 973 * each. 974 */ 975 } 976 977 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 978 { 979 AspeedSoCState *soc = &bmc->soc; 980 981 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 982 } 983 984 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 985 { 986 AspeedSoCState *soc = &bmc->soc; 987 I2CSlave *therm_mux, *cpuvr_mux; 988 989 /* Create the generic DC-SCM hardware */ 990 qcom_dc_scm_bmc_i2c_init(bmc); 991 992 /* Now create the Firework specific hardware */ 993 994 /* I2C7 CPUVR MUX */ 995 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 996 "pca9546", 0x70); 997 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 998 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 999 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1000 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1001 1002 /* I2C8 Thermal Diodes*/ 1003 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1004 "pca9548", 0x70); 1005 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1006 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1007 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1008 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1009 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1010 1011 /* I2C9 Fan Controller (MAX31785) */ 1012 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1013 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1014 } 1015 1016 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1017 { 1018 return ASPEED_MACHINE(obj)->mmio_exec; 1019 } 1020 1021 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1022 { 1023 ASPEED_MACHINE(obj)->mmio_exec = value; 1024 } 1025 1026 static void aspeed_machine_instance_init(Object *obj) 1027 { 1028 ASPEED_MACHINE(obj)->mmio_exec = false; 1029 } 1030 1031 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1032 { 1033 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1034 return g_strdup(bmc->fmc_model); 1035 } 1036 1037 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1038 { 1039 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1040 1041 g_free(bmc->fmc_model); 1042 bmc->fmc_model = g_strdup(value); 1043 } 1044 1045 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1046 { 1047 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1048 return g_strdup(bmc->spi_model); 1049 } 1050 1051 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1052 { 1053 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1054 1055 g_free(bmc->spi_model); 1056 bmc->spi_model = g_strdup(value); 1057 } 1058 1059 static void aspeed_machine_class_props_init(ObjectClass *oc) 1060 { 1061 object_class_property_add_bool(oc, "execute-in-place", 1062 aspeed_get_mmio_exec, 1063 aspeed_set_mmio_exec); 1064 object_class_property_set_description(oc, "execute-in-place", 1065 "boot directly from CE0 flash device"); 1066 1067 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1068 aspeed_set_fmc_model); 1069 object_class_property_set_description(oc, "fmc-model", 1070 "Change the FMC Flash model"); 1071 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1072 aspeed_set_spi_model); 1073 object_class_property_set_description(oc, "spi-model", 1074 "Change the SPI Flash model"); 1075 } 1076 1077 static int aspeed_soc_num_cpus(const char *soc_name) 1078 { 1079 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 1080 return sc->num_cpus; 1081 } 1082 1083 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1084 { 1085 MachineClass *mc = MACHINE_CLASS(oc); 1086 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1087 1088 mc->init = aspeed_machine_init; 1089 mc->no_floppy = 1; 1090 mc->no_cdrom = 1; 1091 mc->no_parallel = 1; 1092 mc->default_ram_id = "ram"; 1093 amc->macs_mask = ASPEED_MAC0_ON; 1094 amc->uart_default = ASPEED_DEV_UART5; 1095 1096 aspeed_machine_class_props_init(oc); 1097 } 1098 1099 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1100 { 1101 MachineClass *mc = MACHINE_CLASS(oc); 1102 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1103 1104 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1105 amc->soc_name = "ast2400-a1"; 1106 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1107 amc->fmc_model = "n25q256a"; 1108 amc->spi_model = "mx25l25635f"; 1109 amc->num_cs = 1; 1110 amc->i2c_init = palmetto_bmc_i2c_init; 1111 mc->default_ram_size = 256 * MiB; 1112 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1113 aspeed_soc_num_cpus(amc->soc_name); 1114 }; 1115 1116 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1117 { 1118 MachineClass *mc = MACHINE_CLASS(oc); 1119 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1120 1121 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1122 amc->soc_name = "ast2400-a1"; 1123 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1124 amc->fmc_model = "n25q256a"; 1125 amc->spi_model = "mx25l25635e"; 1126 amc->num_cs = 1; 1127 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1128 mc->default_ram_size = 128 * MiB; 1129 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1130 aspeed_soc_num_cpus(amc->soc_name); 1131 } 1132 1133 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1134 void *data) 1135 { 1136 MachineClass *mc = MACHINE_CLASS(oc); 1137 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1138 1139 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1140 amc->soc_name = "ast2400-a1"; 1141 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1142 amc->fmc_model = "mx25l25635e"; 1143 amc->spi_model = "mx25l25635e"; 1144 amc->num_cs = 1; 1145 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1146 amc->i2c_init = palmetto_bmc_i2c_init; 1147 mc->default_ram_size = 256 * MiB; 1148 } 1149 1150 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1151 void *data) 1152 { 1153 MachineClass *mc = MACHINE_CLASS(oc); 1154 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1155 1156 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1157 amc->soc_name = "ast2500-a1"; 1158 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1159 amc->fmc_model = "mx25l25635e"; 1160 amc->spi_model = "mx25l25635e"; 1161 amc->num_cs = 1; 1162 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1163 amc->i2c_init = palmetto_bmc_i2c_init; 1164 mc->default_ram_size = 512 * MiB; 1165 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1166 aspeed_soc_num_cpus(amc->soc_name); 1167 } 1168 1169 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1170 { 1171 MachineClass *mc = MACHINE_CLASS(oc); 1172 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1173 1174 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1175 amc->soc_name = "ast2500-a1"; 1176 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1177 amc->fmc_model = "mx25l25635e"; 1178 amc->spi_model = "mx25l25635f"; 1179 amc->num_cs = 1; 1180 amc->i2c_init = ast2500_evb_i2c_init; 1181 mc->default_ram_size = 512 * MiB; 1182 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1183 aspeed_soc_num_cpus(amc->soc_name); 1184 }; 1185 1186 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data) 1187 { 1188 MachineClass *mc = MACHINE_CLASS(oc); 1189 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1190 1191 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1192 amc->soc_name = "ast2500-a1"; 1193 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1194 amc->hw_strap2 = 0; 1195 amc->fmc_model = "n25q256a"; 1196 amc->spi_model = "mx25l25635e"; 1197 amc->num_cs = 2; 1198 amc->i2c_init = yosemitev2_bmc_i2c_init; 1199 mc->default_ram_size = 512 * MiB; 1200 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1201 aspeed_soc_num_cpus(amc->soc_name); 1202 }; 1203 1204 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1205 { 1206 MachineClass *mc = MACHINE_CLASS(oc); 1207 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1208 1209 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1210 amc->soc_name = "ast2500-a1"; 1211 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1212 amc->fmc_model = "n25q256a"; 1213 amc->spi_model = "mx66l1g45g"; 1214 amc->num_cs = 2; 1215 amc->i2c_init = romulus_bmc_i2c_init; 1216 mc->default_ram_size = 512 * MiB; 1217 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1218 aspeed_soc_num_cpus(amc->soc_name); 1219 }; 1220 1221 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1222 { 1223 MachineClass *mc = MACHINE_CLASS(oc); 1224 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1225 1226 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1227 amc->soc_name = "ast2500-a1"; 1228 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1229 amc->fmc_model = "mx66l1g45g"; 1230 amc->spi_model = "mx66l1g45g"; 1231 amc->num_cs = 2; 1232 amc->i2c_init = sonorapass_bmc_i2c_init; 1233 mc->default_ram_size = 512 * MiB; 1234 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1235 aspeed_soc_num_cpus(amc->soc_name); 1236 }; 1237 1238 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1239 { 1240 MachineClass *mc = MACHINE_CLASS(oc); 1241 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1242 1243 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1244 amc->soc_name = "ast2500-a1"; 1245 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1246 amc->fmc_model = "mx25l25635f"; 1247 amc->spi_model = "mx66l1g45g"; 1248 amc->num_cs = 2; 1249 amc->i2c_init = witherspoon_bmc_i2c_init; 1250 mc->default_ram_size = 512 * MiB; 1251 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1252 aspeed_soc_num_cpus(amc->soc_name); 1253 }; 1254 1255 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1256 { 1257 MachineClass *mc = MACHINE_CLASS(oc); 1258 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1259 1260 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1261 amc->soc_name = "ast2600-a3"; 1262 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1263 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1264 amc->fmc_model = "mx66u51235f"; 1265 amc->spi_model = "mx66u51235f"; 1266 amc->num_cs = 1; 1267 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1268 ASPEED_MAC3_ON; 1269 amc->i2c_init = ast2600_evb_i2c_init; 1270 mc->default_ram_size = 1 * GiB; 1271 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1272 aspeed_soc_num_cpus(amc->soc_name); 1273 }; 1274 1275 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1276 { 1277 MachineClass *mc = MACHINE_CLASS(oc); 1278 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1279 1280 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1281 amc->soc_name = "ast2600-a3"; 1282 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1283 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1284 amc->fmc_model = "mx66l1g45g"; 1285 amc->spi_model = "mx66l1g45g"; 1286 amc->num_cs = 2; 1287 amc->macs_mask = ASPEED_MAC2_ON; 1288 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1289 mc->default_ram_size = 1 * GiB; 1290 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1291 aspeed_soc_num_cpus(amc->soc_name); 1292 }; 1293 1294 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1295 { 1296 MachineClass *mc = MACHINE_CLASS(oc); 1297 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1298 1299 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1300 amc->soc_name = "ast2500-a1"; 1301 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1302 amc->fmc_model = "n25q512a"; 1303 amc->spi_model = "mx25l25635e"; 1304 amc->num_cs = 2; 1305 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1306 amc->i2c_init = g220a_bmc_i2c_init; 1307 mc->default_ram_size = 1024 * MiB; 1308 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1309 aspeed_soc_num_cpus(amc->soc_name); 1310 }; 1311 1312 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1313 { 1314 MachineClass *mc = MACHINE_CLASS(oc); 1315 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1316 1317 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1318 amc->soc_name = "ast2500-a1"; 1319 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1320 amc->fmc_model = "n25q512a"; 1321 amc->spi_model = "mx25l25635e"; 1322 amc->num_cs = 2; 1323 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1324 amc->i2c_init = fp5280g2_bmc_i2c_init; 1325 mc->default_ram_size = 512 * MiB; 1326 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1327 aspeed_soc_num_cpus(amc->soc_name); 1328 }; 1329 1330 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1331 { 1332 MachineClass *mc = MACHINE_CLASS(oc); 1333 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1334 1335 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1336 amc->soc_name = "ast2600-a3"; 1337 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1338 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1339 amc->fmc_model = "mx66l1g45g"; 1340 amc->spi_model = "mx66l1g45g"; 1341 amc->num_cs = 2; 1342 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1343 amc->i2c_init = rainier_bmc_i2c_init; 1344 mc->default_ram_size = 1 * GiB; 1345 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1346 aspeed_soc_num_cpus(amc->soc_name); 1347 }; 1348 1349 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 1350 #if HOST_LONG_BITS == 32 1351 #define FUJI_BMC_RAM_SIZE (1 * GiB) 1352 #else 1353 #define FUJI_BMC_RAM_SIZE (2 * GiB) 1354 #endif 1355 1356 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1357 { 1358 MachineClass *mc = MACHINE_CLASS(oc); 1359 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1360 1361 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1362 amc->soc_name = "ast2600-a3"; 1363 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1364 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1365 amc->fmc_model = "mx66l1g45g"; 1366 amc->spi_model = "mx66l1g45g"; 1367 amc->num_cs = 2; 1368 amc->macs_mask = ASPEED_MAC3_ON; 1369 amc->i2c_init = fuji_bmc_i2c_init; 1370 amc->uart_default = ASPEED_DEV_UART1; 1371 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1372 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1373 aspeed_soc_num_cpus(amc->soc_name); 1374 }; 1375 1376 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 1377 #if HOST_LONG_BITS == 32 1378 #define BLETCHLEY_BMC_RAM_SIZE (1 * GiB) 1379 #else 1380 #define BLETCHLEY_BMC_RAM_SIZE (2 * GiB) 1381 #endif 1382 1383 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1384 { 1385 MachineClass *mc = MACHINE_CLASS(oc); 1386 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1387 1388 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1389 amc->soc_name = "ast2600-a3"; 1390 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1391 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1392 amc->fmc_model = "w25q01jvq"; 1393 amc->spi_model = NULL; 1394 amc->num_cs = 2; 1395 amc->macs_mask = ASPEED_MAC2_ON; 1396 amc->i2c_init = bletchley_bmc_i2c_init; 1397 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1398 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1399 aspeed_soc_num_cpus(amc->soc_name); 1400 } 1401 1402 static void fby35_reset(MachineState *state, ShutdownCause reason) 1403 { 1404 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1405 AspeedGPIOState *gpio = &bmc->soc.gpio; 1406 1407 qemu_devices_reset(reason); 1408 1409 /* Board ID: 7 (Class-1, 4 slots) */ 1410 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1411 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1412 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1413 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1414 1415 /* Slot presence pins, inverse polarity. (False means present) */ 1416 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1417 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1418 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1419 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1420 1421 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1422 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1423 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1424 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1425 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1426 } 1427 1428 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) 1429 { 1430 MachineClass *mc = MACHINE_CLASS(oc); 1431 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1432 1433 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1434 mc->reset = fby35_reset; 1435 amc->fmc_model = "mx66l1g45g"; 1436 amc->num_cs = 2; 1437 amc->macs_mask = ASPEED_MAC3_ON; 1438 amc->i2c_init = fby35_i2c_init; 1439 /* FIXME: Replace this macro with something more general */ 1440 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1441 } 1442 1443 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1444 /* Main SYSCLK frequency in Hz (200MHz) */ 1445 #define SYSCLK_FRQ 200000000ULL 1446 1447 static void aspeed_minibmc_machine_init(MachineState *machine) 1448 { 1449 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1450 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1451 Clock *sysclk; 1452 1453 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1454 clock_set_hz(sysclk, SYSCLK_FRQ); 1455 1456 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 1457 qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk); 1458 1459 object_property_set_link(OBJECT(&bmc->soc), "memory", 1460 OBJECT(get_system_memory()), &error_abort); 1461 connect_serial_hds_to_uarts(bmc); 1462 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 1463 1464 aspeed_board_init_flashes(&bmc->soc.fmc, 1465 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1466 amc->num_cs, 1467 0); 1468 1469 aspeed_board_init_flashes(&bmc->soc.spi[0], 1470 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1471 amc->num_cs, amc->num_cs); 1472 1473 aspeed_board_init_flashes(&bmc->soc.spi[1], 1474 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1475 amc->num_cs, (amc->num_cs * 2)); 1476 1477 if (amc->i2c_init) { 1478 amc->i2c_init(bmc); 1479 } 1480 1481 armv7m_load_kernel(ARM_CPU(first_cpu), 1482 machine->kernel_filename, 1483 0, 1484 AST1030_INTERNAL_FLASH_SIZE); 1485 } 1486 1487 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1488 { 1489 AspeedSoCState *soc = &bmc->soc; 1490 1491 /* U10 24C08 connects to SDA/SCL Groupt 1 by default */ 1492 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1493 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1494 1495 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1496 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1497 } 1498 1499 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1500 void *data) 1501 { 1502 MachineClass *mc = MACHINE_CLASS(oc); 1503 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1504 1505 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1506 amc->soc_name = "ast1030-a1"; 1507 amc->hw_strap1 = 0; 1508 amc->hw_strap2 = 0; 1509 mc->init = aspeed_minibmc_machine_init; 1510 amc->i2c_init = ast1030_evb_i2c_init; 1511 mc->default_ram_size = 0; 1512 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1; 1513 amc->fmc_model = "sst25vf032b"; 1514 amc->spi_model = "sst25vf032b"; 1515 amc->num_cs = 2; 1516 amc->macs_mask = 0; 1517 } 1518 1519 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1520 void *data) 1521 { 1522 MachineClass *mc = MACHINE_CLASS(oc); 1523 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1524 1525 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1526 amc->soc_name = "ast2600-a3"; 1527 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1528 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1529 amc->fmc_model = "n25q512a"; 1530 amc->spi_model = "n25q512a"; 1531 amc->num_cs = 2; 1532 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1533 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1534 mc->default_ram_size = 1 * GiB; 1535 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1536 aspeed_soc_num_cpus(amc->soc_name); 1537 }; 1538 1539 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1540 void *data) 1541 { 1542 MachineClass *mc = MACHINE_CLASS(oc); 1543 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1544 1545 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1546 amc->soc_name = "ast2600-a3"; 1547 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1548 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1549 amc->fmc_model = "n25q512a"; 1550 amc->spi_model = "n25q512a"; 1551 amc->num_cs = 2; 1552 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1553 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1554 mc->default_ram_size = 1 * GiB; 1555 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1556 aspeed_soc_num_cpus(amc->soc_name); 1557 }; 1558 1559 static const TypeInfo aspeed_machine_types[] = { 1560 { 1561 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1562 .parent = TYPE_ASPEED_MACHINE, 1563 .class_init = aspeed_machine_palmetto_class_init, 1564 }, { 1565 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1566 .parent = TYPE_ASPEED_MACHINE, 1567 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1568 }, { 1569 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 1570 .parent = TYPE_ASPEED_MACHINE, 1571 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 1572 }, { 1573 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1574 .parent = TYPE_ASPEED_MACHINE, 1575 .class_init = aspeed_machine_ast2500_evb_class_init, 1576 }, { 1577 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1578 .parent = TYPE_ASPEED_MACHINE, 1579 .class_init = aspeed_machine_romulus_class_init, 1580 }, { 1581 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1582 .parent = TYPE_ASPEED_MACHINE, 1583 .class_init = aspeed_machine_sonorapass_class_init, 1584 }, { 1585 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1586 .parent = TYPE_ASPEED_MACHINE, 1587 .class_init = aspeed_machine_witherspoon_class_init, 1588 }, { 1589 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1590 .parent = TYPE_ASPEED_MACHINE, 1591 .class_init = aspeed_machine_ast2600_evb_class_init, 1592 }, { 1593 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 1594 .parent = TYPE_ASPEED_MACHINE, 1595 .class_init = aspeed_machine_yosemitev2_class_init, 1596 }, { 1597 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1598 .parent = TYPE_ASPEED_MACHINE, 1599 .class_init = aspeed_machine_tacoma_class_init, 1600 }, { 1601 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1602 .parent = TYPE_ASPEED_MACHINE, 1603 .class_init = aspeed_machine_g220a_class_init, 1604 }, { 1605 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 1606 .parent = TYPE_ASPEED_MACHINE, 1607 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 1608 }, { 1609 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 1610 .parent = TYPE_ASPEED_MACHINE, 1611 .class_init = aspeed_machine_qcom_firework_class_init, 1612 }, { 1613 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1614 .parent = TYPE_ASPEED_MACHINE, 1615 .class_init = aspeed_machine_fp5280g2_class_init, 1616 }, { 1617 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1618 .parent = TYPE_ASPEED_MACHINE, 1619 .class_init = aspeed_machine_quanta_q71l_class_init, 1620 }, { 1621 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1622 .parent = TYPE_ASPEED_MACHINE, 1623 .class_init = aspeed_machine_rainier_class_init, 1624 }, { 1625 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1626 .parent = TYPE_ASPEED_MACHINE, 1627 .class_init = aspeed_machine_fuji_class_init, 1628 }, { 1629 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1630 .parent = TYPE_ASPEED_MACHINE, 1631 .class_init = aspeed_machine_bletchley_class_init, 1632 }, { 1633 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1634 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1635 .class_init = aspeed_machine_fby35_class_init, 1636 }, { 1637 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1638 .parent = TYPE_ASPEED_MACHINE, 1639 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1640 }, { 1641 .name = TYPE_ASPEED_MACHINE, 1642 .parent = TYPE_MACHINE, 1643 .instance_size = sizeof(AspeedMachineState), 1644 .instance_init = aspeed_machine_instance_init, 1645 .class_size = sizeof(AspeedMachineClass), 1646 .class_init = aspeed_machine_class_init, 1647 .abstract = true, 1648 } 1649 }; 1650 1651 DEFINE_TYPES(aspeed_machine_types) 1652