1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/i2c/i2c_mux_pca954x.h" 18 #include "hw/i2c/smbus_eeprom.h" 19 #include "hw/misc/pca9552.h" 20 #include "hw/sensor/tmp105.h" 21 #include "hw/misc/led.h" 22 #include "hw/qdev-properties.h" 23 #include "sysemu/block-backend.h" 24 #include "hw/loader.h" 25 #include "qemu/error-report.h" 26 #include "qemu/units.h" 27 28 static struct arm_boot_info aspeed_board_binfo = { 29 .board_id = -1, /* device-tree-only board */ 30 }; 31 32 struct AspeedMachineState { 33 /* Private */ 34 MachineState parent_obj; 35 /* Public */ 36 37 AspeedSoCState soc; 38 MemoryRegion ram_container; 39 MemoryRegion max_ram; 40 bool mmio_exec; 41 char *fmc_model; 42 char *spi_model; 43 }; 44 45 /* Palmetto hardware value: 0x120CE416 */ 46 #define PALMETTO_BMC_HW_STRAP1 ( \ 47 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 48 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 49 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 50 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 51 SCU_HW_STRAP_VGA_CLASS_CODE | \ 52 SCU_HW_STRAP_LPC_RESET_PIN | \ 53 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 54 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 55 SCU_HW_STRAP_SPI_WIDTH | \ 56 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 57 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 58 59 /* TODO: Find the actual hardware value */ 60 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 63 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 65 SCU_HW_STRAP_VGA_CLASS_CODE | \ 66 SCU_HW_STRAP_LPC_RESET_PIN | \ 67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 69 SCU_HW_STRAP_SPI_WIDTH | \ 70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 72 73 /* AST2500 evb hardware value: 0xF100C2E6 */ 74 #define AST2500_EVB_HW_STRAP1 (( \ 75 AST2500_HW_STRAP1_DEFAULTS | \ 76 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 77 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 78 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 79 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 80 SCU_HW_STRAP_MAC1_RGMII | \ 81 SCU_HW_STRAP_MAC0_RGMII) & \ 82 ~SCU_HW_STRAP_2ND_BOOT_WDT) 83 84 /* Romulus hardware value: 0xF10AD206 */ 85 #define ROMULUS_BMC_HW_STRAP1 ( \ 86 AST2500_HW_STRAP1_DEFAULTS | \ 87 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 88 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 89 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 90 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 91 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 92 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 93 94 /* Sonorapass hardware value: 0xF100D216 */ 95 #define SONORAPASS_BMC_HW_STRAP1 ( \ 96 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 97 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 98 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 99 SCU_AST2500_HW_STRAP_RESERVED28 | \ 100 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 101 SCU_HW_STRAP_VGA_CLASS_CODE | \ 102 SCU_HW_STRAP_LPC_RESET_PIN | \ 103 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 104 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 105 SCU_HW_STRAP_VGA_BIOS_ROM | \ 106 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 107 SCU_AST2500_HW_STRAP_RESERVED1) 108 109 /* Swift hardware value: 0xF11AD206 */ 110 #define SWIFT_BMC_HW_STRAP1 ( \ 111 AST2500_HW_STRAP1_DEFAULTS | \ 112 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 113 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 114 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 115 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 116 SCU_H_PLL_BYPASS_EN | \ 117 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 119 120 #define G220A_BMC_HW_STRAP1 ( \ 121 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 122 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 123 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 124 SCU_AST2500_HW_STRAP_RESERVED28 | \ 125 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 126 SCU_HW_STRAP_2ND_BOOT_WDT | \ 127 SCU_HW_STRAP_VGA_CLASS_CODE | \ 128 SCU_HW_STRAP_LPC_RESET_PIN | \ 129 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 130 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 131 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 132 SCU_AST2500_HW_STRAP_RESERVED1) 133 134 /* FP5280G2 hardware value: 0XF100D286 */ 135 #define FP5280G2_BMC_HW_STRAP1 ( \ 136 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 137 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 138 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 139 SCU_AST2500_HW_STRAP_RESERVED28 | \ 140 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 141 SCU_HW_STRAP_VGA_CLASS_CODE | \ 142 SCU_HW_STRAP_LPC_RESET_PIN | \ 143 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 144 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 145 SCU_HW_STRAP_MAC1_RGMII | \ 146 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 147 SCU_AST2500_HW_STRAP_RESERVED1) 148 149 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 150 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 151 152 /* Quanta-Q71l hardware value */ 153 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 154 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 155 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 156 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 157 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 158 SCU_HW_STRAP_VGA_CLASS_CODE | \ 159 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 160 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 161 SCU_HW_STRAP_SPI_WIDTH | \ 162 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 163 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 164 165 /* AST2600 evb hardware value */ 166 #define AST2600_EVB_HW_STRAP1 0x000000C0 167 #define AST2600_EVB_HW_STRAP2 0x00000003 168 169 /* Tacoma hardware value */ 170 #define TACOMA_BMC_HW_STRAP1 0x00000000 171 #define TACOMA_BMC_HW_STRAP2 0x00000040 172 173 /* Rainier hardware value: (QEMU prototype) */ 174 #define RAINIER_BMC_HW_STRAP1 0x00000000 175 #define RAINIER_BMC_HW_STRAP2 0x00000000 176 177 /* Fuji hardware value */ 178 #define FUJI_BMC_HW_STRAP1 0x00000000 179 #define FUJI_BMC_HW_STRAP2 0x00000000 180 181 /* 182 * The max ram region is for firmwares that scan the address space 183 * with load/store to guess how much RAM the SoC has. 184 */ 185 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 186 { 187 return 0; 188 } 189 190 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 191 unsigned size) 192 { 193 /* Discard writes */ 194 } 195 196 static const MemoryRegionOps max_ram_ops = { 197 .read = max_ram_read, 198 .write = max_ram_write, 199 .endianness = DEVICE_NATIVE_ENDIAN, 200 }; 201 202 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 203 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 204 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 205 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 206 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 207 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 208 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 209 210 static void aspeed_write_smpboot(ARMCPU *cpu, 211 const struct arm_boot_info *info) 212 { 213 static const uint32_t poll_mailbox_ready[] = { 214 /* 215 * r2 = per-cpu go sign value 216 * r1 = AST_SMP_MBOX_FIELD_ENTRY 217 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 218 */ 219 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 220 0xe21000ff, /* ands r0, r0, #255 */ 221 0xe59f201c, /* ldr r2, [pc, #28] */ 222 0xe1822000, /* orr r2, r2, r0 */ 223 224 0xe59f1018, /* ldr r1, [pc, #24] */ 225 0xe59f0018, /* ldr r0, [pc, #24] */ 226 227 0xe320f002, /* wfe */ 228 0xe5904000, /* ldr r4, [r0] */ 229 0xe1520004, /* cmp r2, r4 */ 230 0x1afffffb, /* bne <wfe> */ 231 0xe591f000, /* ldr pc, [r1] */ 232 AST_SMP_MBOX_GOSIGN, 233 AST_SMP_MBOX_FIELD_ENTRY, 234 AST_SMP_MBOX_FIELD_GOSIGN, 235 }; 236 237 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 238 sizeof(poll_mailbox_ready), 239 info->smp_loader_start); 240 } 241 242 static void aspeed_reset_secondary(ARMCPU *cpu, 243 const struct arm_boot_info *info) 244 { 245 AddressSpace *as = arm_boot_address_space(cpu, info); 246 CPUState *cs = CPU(cpu); 247 248 /* info->smp_bootreg_addr */ 249 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 250 MEMTXATTRS_UNSPECIFIED, NULL); 251 cpu_set_pc(cs, info->smp_loader_start); 252 } 253 254 #define FIRMWARE_ADDR 0x0 255 256 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 257 Error **errp) 258 { 259 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 260 uint8_t *storage; 261 int64_t size; 262 263 /* The block backend size should have already been 'validated' by 264 * the creation of the m25p80 object. 265 */ 266 size = blk_getlength(blk); 267 if (size <= 0) { 268 error_setg(errp, "failed to get flash size"); 269 return; 270 } 271 272 if (rom_size > size) { 273 rom_size = size; 274 } 275 276 storage = g_new0(uint8_t, rom_size); 277 if (blk_pread(blk, 0, storage, rom_size) < 0) { 278 error_setg(errp, "failed to read the initial flash content"); 279 return; 280 } 281 282 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 283 g_free(storage); 284 } 285 286 static void aspeed_board_init_flashes(AspeedSMCState *s, 287 const char *flashtype, 288 int unit0) 289 { 290 int i ; 291 292 for (i = 0; i < s->num_cs; ++i) { 293 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 294 qemu_irq cs_line; 295 DeviceState *dev; 296 297 dev = qdev_new(flashtype); 298 if (dinfo) { 299 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 300 } 301 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 302 303 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); 304 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 305 } 306 } 307 308 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 309 { 310 DeviceState *card; 311 312 if (!dinfo) { 313 return; 314 } 315 card = qdev_new(TYPE_SD_CARD); 316 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 317 &error_fatal); 318 qdev_realize_and_unref(card, 319 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 320 &error_fatal); 321 } 322 323 static void aspeed_machine_init(MachineState *machine) 324 { 325 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 326 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 327 AspeedSoCClass *sc; 328 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 329 ram_addr_t max_ram_size; 330 int i; 331 NICInfo *nd = &nd_table[0]; 332 333 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 334 4 * GiB); 335 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 336 337 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 338 339 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 340 341 /* 342 * This will error out if isize is not supported by memory controller. 343 */ 344 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size, 345 &error_fatal); 346 347 for (i = 0; i < sc->macs_num; i++) { 348 if ((amc->macs_mask & (1 << i)) && nd->used) { 349 qemu_check_nic_model(nd, TYPE_FTGMAC100); 350 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 351 nd++; 352 } 353 } 354 355 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 356 &error_abort); 357 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 358 &error_abort); 359 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs, 360 &error_abort); 361 object_property_set_link(OBJECT(&bmc->soc), "dram", 362 OBJECT(machine->ram), &error_abort); 363 if (machine->kernel_filename) { 364 /* 365 * When booting with a -kernel command line there is no u-boot 366 * that runs to unlock the SCU. In this case set the default to 367 * be unlocked as the kernel expects 368 */ 369 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 370 ASPEED_SCU_PROT_KEY, &error_abort); 371 } 372 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", 373 amc->uart_default); 374 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 375 376 memory_region_add_subregion(get_system_memory(), 377 sc->memmap[ASPEED_DEV_SDRAM], 378 &bmc->ram_container); 379 380 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 381 &error_abort); 382 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 383 "max_ram", max_ram_size - machine->ram_size); 384 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram); 385 386 aspeed_board_init_flashes(&bmc->soc.fmc, 387 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 388 0); 389 aspeed_board_init_flashes(&bmc->soc.spi[0], 390 bmc->spi_model ? bmc->spi_model : amc->spi_model, 391 bmc->soc.fmc.num_cs); 392 393 /* Install first FMC flash content as a boot rom. */ 394 if (drive0) { 395 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 396 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 397 uint64_t size = memory_region_size(&fl->mmio); 398 399 /* 400 * create a ROM region using the default mapping window size of 401 * the flash module. The window size is 64MB for the AST2400 402 * SoC and 128MB for the AST2500 SoC, which is twice as big as 403 * needed by the flash modules of the Aspeed machines. 404 */ 405 if (ASPEED_MACHINE(machine)->mmio_exec) { 406 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", 407 &fl->mmio, 0, size); 408 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 409 boot_rom); 410 } else { 411 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", 412 size, &error_abort); 413 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 414 boot_rom); 415 write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort); 416 } 417 } 418 419 if (machine->kernel_filename && sc->num_cpus > 1) { 420 /* With no u-boot we must set up a boot stub for the secondary CPU */ 421 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 422 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 423 0x80, &error_abort); 424 memory_region_add_subregion(get_system_memory(), 425 AST_SMP_MAILBOX_BASE, smpboot); 426 427 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 428 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 429 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 430 } 431 432 aspeed_board_binfo.ram_size = machine->ram_size; 433 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 434 aspeed_board_binfo.nb_cpus = sc->num_cpus; 435 436 if (amc->i2c_init) { 437 amc->i2c_init(bmc); 438 } 439 440 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 441 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], 442 drive_get(IF_SD, 0, i)); 443 } 444 445 if (bmc->soc.emmc.num_slots) { 446 sdhci_attach_drive(&bmc->soc.emmc.slots[0], 447 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots)); 448 } 449 450 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 451 } 452 453 static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize) 454 { 455 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 456 DeviceState *dev = DEVICE(i2c_dev); 457 458 qdev_prop_set_uint32(dev, "rom-size", rsize); 459 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); 460 } 461 462 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 463 { 464 AspeedSoCState *soc = &bmc->soc; 465 DeviceState *dev; 466 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 467 468 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 469 * enough to provide basic RTC features. Alarms will be missing */ 470 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 471 472 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 473 eeprom_buf); 474 475 /* add a TMP423 temperature sensor */ 476 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 477 "tmp423", 0x4c)); 478 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 479 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 480 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 481 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 482 } 483 484 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 485 { 486 AspeedSoCState *soc = &bmc->soc; 487 488 /* 489 * The quanta-q71l platform expects tmp75s which are compatible with 490 * tmp105s. 491 */ 492 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 493 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 494 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 495 496 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 497 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 498 /* TODO: Add Memory Riser i2c mux and eeproms. */ 499 500 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 501 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 502 503 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 504 505 /* i2c-7 */ 506 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 507 /* - i2c@0: pmbus@59 */ 508 /* - i2c@1: pmbus@58 */ 509 /* - i2c@2: pmbus@58 */ 510 /* - i2c@3: pmbus@59 */ 511 512 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 513 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 514 } 515 516 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 517 { 518 AspeedSoCState *soc = &bmc->soc; 519 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 520 521 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 522 eeprom_buf); 523 524 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 525 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 526 TYPE_TMP105, 0x4d); 527 528 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 529 * plugged on the I2C bus header */ 530 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 531 } 532 533 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 534 { 535 /* Start with some devices on our I2C busses */ 536 ast2500_evb_i2c_init(bmc); 537 } 538 539 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 540 { 541 AspeedSoCState *soc = &bmc->soc; 542 543 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 544 * good enough */ 545 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 546 } 547 548 static void swift_bmc_i2c_init(AspeedMachineState *bmc) 549 { 550 AspeedSoCState *soc = &bmc->soc; 551 552 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60); 553 554 /* The swift board expects a TMP275 but a TMP105 is compatible */ 555 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48); 556 /* The swift board expects a pca9551 but a pca9552 is compatible */ 557 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60); 558 559 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ 560 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32); 561 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 562 563 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 564 /* The swift board expects a pca9539 but a pca9552 is compatible */ 565 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74); 566 567 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 568 /* The swift board expects a pca9539 but a pca9552 is compatible */ 569 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552", 570 0x74); 571 572 /* The swift board expects a TMP275 but a TMP105 is compatible */ 573 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48); 574 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a); 575 } 576 577 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 578 { 579 AspeedSoCState *soc = &bmc->soc; 580 581 /* bus 2 : */ 582 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 583 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 584 /* bus 2 : pca9546 @ 0x73 */ 585 586 /* bus 3 : pca9548 @ 0x70 */ 587 588 /* bus 4 : */ 589 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 590 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 591 eeprom4_54); 592 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 593 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76); 594 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 595 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77); 596 597 /* bus 6 : */ 598 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 599 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 600 /* bus 6 : pca9546 @ 0x73 */ 601 602 /* bus 8 : */ 603 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 604 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 605 eeprom8_56); 606 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 607 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); 608 /* bus 8 : adc128d818 @ 0x1d */ 609 /* bus 8 : adc128d818 @ 0x1f */ 610 611 /* 612 * bus 13 : pca9548 @ 0x71 613 * - channel 3: 614 * - tmm421 @ 0x4c 615 * - tmp421 @ 0x4e 616 * - tmp421 @ 0x4f 617 */ 618 619 } 620 621 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 622 { 623 static const struct { 624 unsigned gpio_id; 625 LEDColor color; 626 const char *description; 627 bool gpio_polarity; 628 } pca1_leds[] = { 629 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 630 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 631 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 632 }; 633 AspeedSoCState *soc = &bmc->soc; 634 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 635 DeviceState *dev; 636 LEDState *led; 637 638 /* Bus 3: TODO bmp280@77 */ 639 /* Bus 3: TODO max31785@52 */ 640 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 641 qdev_prop_set_string(dev, "description", "pca1"); 642 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 643 aspeed_i2c_get_bus(&soc->i2c, 3), 644 &error_fatal); 645 646 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 647 led = led_create_simple(OBJECT(bmc), 648 pca1_leds[i].gpio_polarity, 649 pca1_leds[i].color, 650 pca1_leds[i].description); 651 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 652 qdev_get_gpio_in(DEVICE(led), 0)); 653 } 654 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 655 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 656 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 657 658 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 659 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 660 0x4a); 661 662 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 663 * good enough */ 664 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 665 666 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 667 eeprom_buf); 668 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 669 qdev_prop_set_string(dev, "description", "pca0"); 670 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 671 aspeed_i2c_get_bus(&soc->i2c, 11), 672 &error_fatal); 673 /* Bus 11: TODO ucd90160@64 */ 674 } 675 676 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 677 { 678 AspeedSoCState *soc = &bmc->soc; 679 DeviceState *dev; 680 681 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 682 "emc1413", 0x4c)); 683 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 684 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 685 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 686 687 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 688 "emc1413", 0x4c)); 689 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 690 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 691 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 692 693 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 694 "emc1413", 0x4c)); 695 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 696 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 697 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 698 699 static uint8_t eeprom_buf[2 * 1024] = { 700 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 701 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 702 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 703 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 704 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 705 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 706 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 707 }; 708 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 709 eeprom_buf); 710 } 711 712 static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize) 713 { 714 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 715 DeviceState *dev = DEVICE(i2c_dev); 716 717 qdev_prop_set_uint32(dev, "rom-size", rsize); 718 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); 719 } 720 721 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 722 { 723 AspeedSoCState *soc = &bmc->soc; 724 I2CSlave *i2c_mux; 725 726 /* The at24c256 */ 727 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 728 729 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 730 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 731 0x48); 732 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 733 0x49); 734 735 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 736 "pca9546", 0x70); 737 /* It expects a TMP112 but a TMP105 is compatible */ 738 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 739 0x4a); 740 741 /* It expects a ds3232 but a ds1338 is good enough */ 742 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 743 744 /* It expects a pca9555 but a pca9552 is compatible */ 745 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_PCA9552, 746 0x20); 747 } 748 749 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 750 { 751 AspeedSoCState *soc = &bmc->soc; 752 I2CSlave *i2c_mux; 753 754 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 755 756 /* The rainier expects a TMP275 but a TMP105 is compatible */ 757 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 758 0x48); 759 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 760 0x49); 761 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 762 0x4a); 763 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 764 "pca9546", 0x70); 765 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 766 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 767 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 768 769 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 770 0x48); 771 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 772 0x49); 773 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 774 "pca9546", 0x70); 775 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 776 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 777 778 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 779 0x48); 780 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 781 0x4a); 782 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 783 0x4b); 784 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 785 "pca9546", 0x70); 786 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 787 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 788 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 789 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 790 791 /* Bus 7: TODO max31785@52 */ 792 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61); 793 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 794 /* Bus 7: TODO si7021-a20@20 */ 795 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 796 0x48); 797 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 798 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 799 800 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 801 0x48); 802 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 803 0x4a); 804 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB); 805 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB); 806 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); 807 /* Bus 8: ucd90320@11 */ 808 /* Bus 8: ucd90320@b */ 809 /* Bus 8: ucd90320@c */ 810 811 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 812 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 813 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 814 815 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 816 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 817 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 818 819 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 820 0x48); 821 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 822 0x49); 823 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 824 "pca9546", 0x70); 825 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 826 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 827 828 829 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 830 831 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 832 833 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 834 } 835 836 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 837 I2CBus **channels) 838 { 839 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 840 for (int i = 0; i < 8; i++) { 841 channels[i] = pca954x_i2c_get_bus(mux, i); 842 } 843 } 844 845 #define TYPE_LM75 TYPE_TMP105 846 #define TYPE_TMP75 TYPE_TMP105 847 #define TYPE_TMP422 "tmp422" 848 849 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 850 { 851 AspeedSoCState *soc = &bmc->soc; 852 I2CBus *i2c[144] = {}; 853 854 for (int i = 0; i < 16; i++) { 855 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 856 } 857 I2CBus *i2c180 = i2c[2]; 858 I2CBus *i2c480 = i2c[8]; 859 I2CBus *i2c600 = i2c[11]; 860 861 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 862 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 863 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 864 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 865 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 866 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 867 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 868 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 869 for (int i = 0; i < 8; i++) { 870 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 871 } 872 873 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 874 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 875 876 aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB); 877 aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB); 878 aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB); 879 880 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 881 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 882 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 883 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 884 885 aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB); 886 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 887 888 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 889 aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB); 890 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 891 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 892 893 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 894 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 895 896 aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB); 897 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 898 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 899 aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB); 900 aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB); 901 aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB); 902 aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB); 903 904 aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB); 905 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 906 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 907 aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB); 908 aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB); 909 aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB); 910 aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB); 911 aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB); 912 913 for (int i = 0; i < 8; i++) { 914 aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 915 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 916 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 917 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 918 } 919 } 920 921 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 922 { 923 return ASPEED_MACHINE(obj)->mmio_exec; 924 } 925 926 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 927 { 928 ASPEED_MACHINE(obj)->mmio_exec = value; 929 } 930 931 static void aspeed_machine_instance_init(Object *obj) 932 { 933 ASPEED_MACHINE(obj)->mmio_exec = false; 934 } 935 936 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 937 { 938 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 939 return g_strdup(bmc->fmc_model); 940 } 941 942 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 943 { 944 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 945 946 g_free(bmc->fmc_model); 947 bmc->fmc_model = g_strdup(value); 948 } 949 950 static char *aspeed_get_spi_model(Object *obj, Error **errp) 951 { 952 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 953 return g_strdup(bmc->spi_model); 954 } 955 956 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 957 { 958 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 959 960 g_free(bmc->spi_model); 961 bmc->spi_model = g_strdup(value); 962 } 963 964 static void aspeed_machine_class_props_init(ObjectClass *oc) 965 { 966 object_class_property_add_bool(oc, "execute-in-place", 967 aspeed_get_mmio_exec, 968 aspeed_set_mmio_exec); 969 object_class_property_set_description(oc, "execute-in-place", 970 "boot directly from CE0 flash device"); 971 972 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 973 aspeed_set_fmc_model); 974 object_class_property_set_description(oc, "fmc-model", 975 "Change the FMC Flash model"); 976 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 977 aspeed_set_spi_model); 978 object_class_property_set_description(oc, "spi-model", 979 "Change the SPI Flash model"); 980 } 981 982 static int aspeed_soc_num_cpus(const char *soc_name) 983 { 984 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 985 return sc->num_cpus; 986 } 987 988 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 989 { 990 MachineClass *mc = MACHINE_CLASS(oc); 991 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 992 993 mc->init = aspeed_machine_init; 994 mc->no_floppy = 1; 995 mc->no_cdrom = 1; 996 mc->no_parallel = 1; 997 mc->default_ram_id = "ram"; 998 amc->macs_mask = ASPEED_MAC0_ON; 999 amc->uart_default = ASPEED_DEV_UART5; 1000 1001 aspeed_machine_class_props_init(oc); 1002 } 1003 1004 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1005 { 1006 MachineClass *mc = MACHINE_CLASS(oc); 1007 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1008 1009 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1010 amc->soc_name = "ast2400-a1"; 1011 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1012 amc->fmc_model = "n25q256a"; 1013 amc->spi_model = "mx25l25635e"; 1014 amc->num_cs = 1; 1015 amc->i2c_init = palmetto_bmc_i2c_init; 1016 mc->default_ram_size = 256 * MiB; 1017 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1018 aspeed_soc_num_cpus(amc->soc_name); 1019 }; 1020 1021 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1022 { 1023 MachineClass *mc = MACHINE_CLASS(oc); 1024 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1025 1026 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1027 amc->soc_name = "ast2400-a1"; 1028 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1029 amc->fmc_model = "n25q256a"; 1030 amc->spi_model = "mx25l25635e"; 1031 amc->num_cs = 1; 1032 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1033 mc->default_ram_size = 128 * MiB; 1034 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1035 aspeed_soc_num_cpus(amc->soc_name); 1036 } 1037 1038 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1039 void *data) 1040 { 1041 MachineClass *mc = MACHINE_CLASS(oc); 1042 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1043 1044 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1045 amc->soc_name = "ast2400-a1"; 1046 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1047 amc->fmc_model = "mx25l25635e"; 1048 amc->spi_model = "mx25l25635e"; 1049 amc->num_cs = 1; 1050 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1051 amc->i2c_init = palmetto_bmc_i2c_init; 1052 mc->default_ram_size = 256 * MiB; 1053 } 1054 1055 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1056 { 1057 MachineClass *mc = MACHINE_CLASS(oc); 1058 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1059 1060 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1061 amc->soc_name = "ast2500-a1"; 1062 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1063 amc->fmc_model = "w25q256"; 1064 amc->spi_model = "mx25l25635e"; 1065 amc->num_cs = 1; 1066 amc->i2c_init = ast2500_evb_i2c_init; 1067 mc->default_ram_size = 512 * MiB; 1068 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1069 aspeed_soc_num_cpus(amc->soc_name); 1070 }; 1071 1072 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1073 { 1074 MachineClass *mc = MACHINE_CLASS(oc); 1075 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1076 1077 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1078 amc->soc_name = "ast2500-a1"; 1079 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1080 amc->fmc_model = "n25q256a"; 1081 amc->spi_model = "mx66l1g45g"; 1082 amc->num_cs = 2; 1083 amc->i2c_init = romulus_bmc_i2c_init; 1084 mc->default_ram_size = 512 * MiB; 1085 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1086 aspeed_soc_num_cpus(amc->soc_name); 1087 }; 1088 1089 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1090 { 1091 MachineClass *mc = MACHINE_CLASS(oc); 1092 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1093 1094 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1095 amc->soc_name = "ast2500-a1"; 1096 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1097 amc->fmc_model = "mx66l1g45g"; 1098 amc->spi_model = "mx66l1g45g"; 1099 amc->num_cs = 2; 1100 amc->i2c_init = sonorapass_bmc_i2c_init; 1101 mc->default_ram_size = 512 * MiB; 1102 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1103 aspeed_soc_num_cpus(amc->soc_name); 1104 }; 1105 1106 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) 1107 { 1108 MachineClass *mc = MACHINE_CLASS(oc); 1109 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1110 1111 mc->desc = "OpenPOWER Swift BMC (ARM1176)"; 1112 amc->soc_name = "ast2500-a1"; 1113 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1; 1114 amc->fmc_model = "mx66l1g45g"; 1115 amc->spi_model = "mx66l1g45g"; 1116 amc->num_cs = 2; 1117 amc->i2c_init = swift_bmc_i2c_init; 1118 mc->default_ram_size = 512 * MiB; 1119 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1120 aspeed_soc_num_cpus(amc->soc_name); 1121 1122 mc->deprecation_reason = "redundant system. Please use a similar " 1123 "OpenPOWER BMC, Witherspoon or Romulus."; 1124 }; 1125 1126 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1127 { 1128 MachineClass *mc = MACHINE_CLASS(oc); 1129 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1130 1131 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1132 amc->soc_name = "ast2500-a1"; 1133 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1134 amc->fmc_model = "mx25l25635e"; 1135 amc->spi_model = "mx66l1g45g"; 1136 amc->num_cs = 2; 1137 amc->i2c_init = witherspoon_bmc_i2c_init; 1138 mc->default_ram_size = 512 * MiB; 1139 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1140 aspeed_soc_num_cpus(amc->soc_name); 1141 }; 1142 1143 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1144 { 1145 MachineClass *mc = MACHINE_CLASS(oc); 1146 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1147 1148 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1149 amc->soc_name = "ast2600-a3"; 1150 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1151 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1152 amc->fmc_model = "w25q512jv"; 1153 amc->spi_model = "mx66u51235f"; 1154 amc->num_cs = 1; 1155 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1156 ASPEED_MAC3_ON; 1157 amc->i2c_init = ast2600_evb_i2c_init; 1158 mc->default_ram_size = 1 * GiB; 1159 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1160 aspeed_soc_num_cpus(amc->soc_name); 1161 }; 1162 1163 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1164 { 1165 MachineClass *mc = MACHINE_CLASS(oc); 1166 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1167 1168 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1169 amc->soc_name = "ast2600-a3"; 1170 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1171 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1172 amc->fmc_model = "mx66l1g45g"; 1173 amc->spi_model = "mx66l1g45g"; 1174 amc->num_cs = 2; 1175 amc->macs_mask = ASPEED_MAC2_ON; 1176 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1177 mc->default_ram_size = 1 * GiB; 1178 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1179 aspeed_soc_num_cpus(amc->soc_name); 1180 }; 1181 1182 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1183 { 1184 MachineClass *mc = MACHINE_CLASS(oc); 1185 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1186 1187 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1188 amc->soc_name = "ast2500-a1"; 1189 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1190 amc->fmc_model = "n25q512a"; 1191 amc->spi_model = "mx25l25635e"; 1192 amc->num_cs = 2; 1193 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1194 amc->i2c_init = g220a_bmc_i2c_init; 1195 mc->default_ram_size = 1024 * MiB; 1196 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1197 aspeed_soc_num_cpus(amc->soc_name); 1198 }; 1199 1200 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1201 { 1202 MachineClass *mc = MACHINE_CLASS(oc); 1203 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1204 1205 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1206 amc->soc_name = "ast2500-a1"; 1207 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1208 amc->fmc_model = "n25q512a"; 1209 amc->spi_model = "mx25l25635e"; 1210 amc->num_cs = 2; 1211 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1212 amc->i2c_init = fp5280g2_bmc_i2c_init; 1213 mc->default_ram_size = 512 * MiB; 1214 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1215 aspeed_soc_num_cpus(amc->soc_name); 1216 }; 1217 1218 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1219 { 1220 MachineClass *mc = MACHINE_CLASS(oc); 1221 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1222 1223 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1224 amc->soc_name = "ast2600-a3"; 1225 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1226 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1227 amc->fmc_model = "mx66l1g45g"; 1228 amc->spi_model = "mx66l1g45g"; 1229 amc->num_cs = 2; 1230 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1231 amc->i2c_init = rainier_bmc_i2c_init; 1232 mc->default_ram_size = 1 * GiB; 1233 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1234 aspeed_soc_num_cpus(amc->soc_name); 1235 }; 1236 1237 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 1238 #if HOST_LONG_BITS == 32 1239 #define FUJI_BMC_RAM_SIZE (1 * GiB) 1240 #else 1241 #define FUJI_BMC_RAM_SIZE (2 * GiB) 1242 #endif 1243 1244 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1245 { 1246 MachineClass *mc = MACHINE_CLASS(oc); 1247 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1248 1249 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1250 amc->soc_name = "ast2600-a3"; 1251 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1252 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1253 amc->fmc_model = "mx66l1g45g"; 1254 amc->spi_model = "mx66l1g45g"; 1255 amc->num_cs = 2; 1256 amc->macs_mask = ASPEED_MAC3_ON; 1257 amc->i2c_init = fuji_bmc_i2c_init; 1258 amc->uart_default = ASPEED_DEV_UART1; 1259 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1260 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1261 aspeed_soc_num_cpus(amc->soc_name); 1262 }; 1263 1264 static const TypeInfo aspeed_machine_types[] = { 1265 { 1266 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1267 .parent = TYPE_ASPEED_MACHINE, 1268 .class_init = aspeed_machine_palmetto_class_init, 1269 }, { 1270 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1271 .parent = TYPE_ASPEED_MACHINE, 1272 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1273 }, { 1274 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1275 .parent = TYPE_ASPEED_MACHINE, 1276 .class_init = aspeed_machine_ast2500_evb_class_init, 1277 }, { 1278 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1279 .parent = TYPE_ASPEED_MACHINE, 1280 .class_init = aspeed_machine_romulus_class_init, 1281 }, { 1282 .name = MACHINE_TYPE_NAME("swift-bmc"), 1283 .parent = TYPE_ASPEED_MACHINE, 1284 .class_init = aspeed_machine_swift_class_init, 1285 }, { 1286 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1287 .parent = TYPE_ASPEED_MACHINE, 1288 .class_init = aspeed_machine_sonorapass_class_init, 1289 }, { 1290 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1291 .parent = TYPE_ASPEED_MACHINE, 1292 .class_init = aspeed_machine_witherspoon_class_init, 1293 }, { 1294 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1295 .parent = TYPE_ASPEED_MACHINE, 1296 .class_init = aspeed_machine_ast2600_evb_class_init, 1297 }, { 1298 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1299 .parent = TYPE_ASPEED_MACHINE, 1300 .class_init = aspeed_machine_tacoma_class_init, 1301 }, { 1302 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1303 .parent = TYPE_ASPEED_MACHINE, 1304 .class_init = aspeed_machine_g220a_class_init, 1305 }, { 1306 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1307 .parent = TYPE_ASPEED_MACHINE, 1308 .class_init = aspeed_machine_fp5280g2_class_init, 1309 }, { 1310 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1311 .parent = TYPE_ASPEED_MACHINE, 1312 .class_init = aspeed_machine_quanta_q71l_class_init, 1313 }, { 1314 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1315 .parent = TYPE_ASPEED_MACHINE, 1316 .class_init = aspeed_machine_rainier_class_init, 1317 }, { 1318 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1319 .parent = TYPE_ASPEED_MACHINE, 1320 .class_init = aspeed_machine_fuji_class_init, 1321 }, { 1322 .name = TYPE_ASPEED_MACHINE, 1323 .parent = TYPE_MACHINE, 1324 .instance_size = sizeof(AspeedMachineState), 1325 .instance_init = aspeed_machine_instance_init, 1326 .class_size = sizeof(AspeedMachineClass), 1327 .class_init = aspeed_machine_class_init, 1328 .abstract = true, 1329 } 1330 }; 1331 1332 DEFINE_TYPES(aspeed_machine_types) 1333