1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "cpu.h" 15 #include "exec/address-spaces.h" 16 #include "hw/arm/boot.h" 17 #include "hw/arm/aspeed.h" 18 #include "hw/arm/aspeed_soc.h" 19 #include "hw/boards.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/misc/pca9552.h" 22 #include "hw/misc/tmp105.h" 23 #include "hw/qdev-properties.h" 24 #include "qemu/log.h" 25 #include "sysemu/block-backend.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/loader.h" 28 #include "qemu/error-report.h" 29 #include "qemu/units.h" 30 31 static struct arm_boot_info aspeed_board_binfo = { 32 .board_id = -1, /* device-tree-only board */ 33 }; 34 35 struct AspeedBoardState { 36 AspeedSoCState soc; 37 MemoryRegion ram_container; 38 MemoryRegion max_ram; 39 }; 40 41 /* Palmetto hardware value: 0x120CE416 */ 42 #define PALMETTO_BMC_HW_STRAP1 ( \ 43 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 44 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 45 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 46 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 47 SCU_HW_STRAP_VGA_CLASS_CODE | \ 48 SCU_HW_STRAP_LPC_RESET_PIN | \ 49 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 50 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 51 SCU_HW_STRAP_SPI_WIDTH | \ 52 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 53 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 54 55 /* AST2500 evb hardware value: 0xF100C2E6 */ 56 #define AST2500_EVB_HW_STRAP1 (( \ 57 AST2500_HW_STRAP1_DEFAULTS | \ 58 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 59 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 60 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 61 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 62 SCU_HW_STRAP_MAC1_RGMII | \ 63 SCU_HW_STRAP_MAC0_RGMII) & \ 64 ~SCU_HW_STRAP_2ND_BOOT_WDT) 65 66 /* Romulus hardware value: 0xF10AD206 */ 67 #define ROMULUS_BMC_HW_STRAP1 ( \ 68 AST2500_HW_STRAP1_DEFAULTS | \ 69 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 70 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 71 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 72 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 73 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 74 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 75 76 /* Sonorapass hardware value: 0xF100D216 */ 77 #define SONORAPASS_BMC_HW_STRAP1 ( \ 78 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 79 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 80 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 81 SCU_AST2500_HW_STRAP_RESERVED28 | \ 82 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 83 SCU_HW_STRAP_VGA_CLASS_CODE | \ 84 SCU_HW_STRAP_LPC_RESET_PIN | \ 85 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 86 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 87 SCU_HW_STRAP_VGA_BIOS_ROM | \ 88 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 89 SCU_AST2500_HW_STRAP_RESERVED1) 90 91 /* Swift hardware value: 0xF11AD206 */ 92 #define SWIFT_BMC_HW_STRAP1 ( \ 93 AST2500_HW_STRAP1_DEFAULTS | \ 94 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 95 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 96 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 97 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 98 SCU_H_PLL_BYPASS_EN | \ 99 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 100 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 101 102 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 103 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 104 105 /* AST2600 evb hardware value */ 106 #define AST2600_EVB_HW_STRAP1 0x000000C0 107 #define AST2600_EVB_HW_STRAP2 0x00000003 108 109 /* Tacoma hardware value */ 110 #define TACOMA_BMC_HW_STRAP1 0x00000000 111 #define TACOMA_BMC_HW_STRAP2 0x00000040 112 113 /* 114 * The max ram region is for firmwares that scan the address space 115 * with load/store to guess how much RAM the SoC has. 116 */ 117 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 118 { 119 return 0; 120 } 121 122 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 123 unsigned size) 124 { 125 /* Discard writes */ 126 } 127 128 static const MemoryRegionOps max_ram_ops = { 129 .read = max_ram_read, 130 .write = max_ram_write, 131 .endianness = DEVICE_NATIVE_ENDIAN, 132 }; 133 134 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 135 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 136 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 137 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 138 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 139 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 140 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 141 142 static void aspeed_write_smpboot(ARMCPU *cpu, 143 const struct arm_boot_info *info) 144 { 145 static const uint32_t poll_mailbox_ready[] = { 146 /* 147 * r2 = per-cpu go sign value 148 * r1 = AST_SMP_MBOX_FIELD_ENTRY 149 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 150 */ 151 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 152 0xe21000ff, /* ands r0, r0, #255 */ 153 0xe59f201c, /* ldr r2, [pc, #28] */ 154 0xe1822000, /* orr r2, r2, r0 */ 155 156 0xe59f1018, /* ldr r1, [pc, #24] */ 157 0xe59f0018, /* ldr r0, [pc, #24] */ 158 159 0xe320f002, /* wfe */ 160 0xe5904000, /* ldr r4, [r0] */ 161 0xe1520004, /* cmp r2, r4 */ 162 0x1afffffb, /* bne <wfe> */ 163 0xe591f000, /* ldr pc, [r1] */ 164 AST_SMP_MBOX_GOSIGN, 165 AST_SMP_MBOX_FIELD_ENTRY, 166 AST_SMP_MBOX_FIELD_GOSIGN, 167 }; 168 169 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 170 sizeof(poll_mailbox_ready), 171 info->smp_loader_start); 172 } 173 174 static void aspeed_reset_secondary(ARMCPU *cpu, 175 const struct arm_boot_info *info) 176 { 177 AddressSpace *as = arm_boot_address_space(cpu, info); 178 CPUState *cs = CPU(cpu); 179 180 /* info->smp_bootreg_addr */ 181 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 182 MEMTXATTRS_UNSPECIFIED, NULL); 183 cpu_set_pc(cs, info->smp_loader_start); 184 } 185 186 #define FIRMWARE_ADDR 0x0 187 188 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 189 Error **errp) 190 { 191 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 192 uint8_t *storage; 193 int64_t size; 194 195 /* The block backend size should have already been 'validated' by 196 * the creation of the m25p80 object. 197 */ 198 size = blk_getlength(blk); 199 if (size <= 0) { 200 error_setg(errp, "failed to get flash size"); 201 return; 202 } 203 204 if (rom_size > size) { 205 rom_size = size; 206 } 207 208 storage = g_new0(uint8_t, rom_size); 209 if (blk_pread(blk, 0, storage, rom_size) < 0) { 210 error_setg(errp, "failed to read the initial flash content"); 211 return; 212 } 213 214 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 215 g_free(storage); 216 } 217 218 static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 219 Error **errp) 220 { 221 int i ; 222 223 for (i = 0; i < s->num_cs; ++i) { 224 AspeedSMCFlash *fl = &s->flashes[i]; 225 DriveInfo *dinfo = drive_get_next(IF_MTD); 226 qemu_irq cs_line; 227 228 fl->flash = ssi_create_slave_no_init(s->spi, flashtype); 229 if (dinfo) { 230 qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo), 231 errp); 232 } 233 qdev_init_nofail(fl->flash); 234 235 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); 236 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 237 } 238 } 239 240 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 241 { 242 DeviceState *card; 243 244 card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 245 TYPE_SD_CARD); 246 if (dinfo) { 247 qdev_prop_set_drive(card, "drive", blk_by_legacy_dinfo(dinfo), 248 &error_fatal); 249 } 250 object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); 251 } 252 253 static void aspeed_machine_init(MachineState *machine) 254 { 255 AspeedBoardState *bmc; 256 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 257 AspeedSoCClass *sc; 258 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 259 ram_addr_t max_ram_size; 260 int i; 261 262 bmc = g_new0(AspeedBoardState, 1); 263 264 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 265 UINT32_MAX); 266 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 267 268 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, 269 (sizeof(bmc->soc)), amc->soc_name, &error_abort, 270 NULL); 271 272 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 273 274 /* 275 * This will error out if isize is not supported by memory controller. 276 */ 277 object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size", 278 &error_fatal); 279 280 object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap1, "hw-strap1", 281 &error_abort); 282 object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap2, "hw-strap2", 283 &error_abort); 284 object_property_set_int(OBJECT(&bmc->soc), amc->num_cs, "num-cs", 285 &error_abort); 286 object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus", 287 &error_abort); 288 object_property_set_link(OBJECT(&bmc->soc), OBJECT(&bmc->ram_container), 289 "dram", &error_abort); 290 if (machine->kernel_filename) { 291 /* 292 * When booting with a -kernel command line there is no u-boot 293 * that runs to unlock the SCU. In this case set the default to 294 * be unlocked as the kernel expects 295 */ 296 object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY, 297 "hw-prot-key", &error_abort); 298 } 299 object_property_set_bool(OBJECT(&bmc->soc), true, "realized", 300 &error_abort); 301 302 memory_region_add_subregion(get_system_memory(), 303 sc->memmap[ASPEED_SDRAM], 304 &bmc->ram_container); 305 306 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 307 &error_abort); 308 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 309 "max_ram", max_ram_size - ram_size); 310 memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram); 311 312 aspeed_board_init_flashes(&bmc->soc.fmc, amc->fmc_model, &error_abort); 313 aspeed_board_init_flashes(&bmc->soc.spi[0], amc->spi_model, &error_abort); 314 315 /* Install first FMC flash content as a boot rom. */ 316 if (drive0) { 317 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 318 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 319 320 /* 321 * create a ROM region using the default mapping window size of 322 * the flash module. The window size is 64MB for the AST2400 323 * SoC and 128MB for the AST2500 SoC, which is twice as big as 324 * needed by the flash modules of the Aspeed machines. 325 */ 326 if (ASPEED_MACHINE(machine)->mmio_exec) { 327 memory_region_init_alias(boot_rom, OBJECT(bmc), "aspeed.boot_rom", 328 &fl->mmio, 0, fl->size); 329 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 330 boot_rom); 331 } else { 332 memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", 333 fl->size, &error_abort); 334 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 335 boot_rom); 336 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); 337 } 338 } 339 340 if (machine->kernel_filename && bmc->soc.num_cpus > 1) { 341 /* With no u-boot we must set up a boot stub for the secondary CPU */ 342 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 343 memory_region_init_ram(smpboot, OBJECT(bmc), "aspeed.smpboot", 344 0x80, &error_abort); 345 memory_region_add_subregion(get_system_memory(), 346 AST_SMP_MAILBOX_BASE, smpboot); 347 348 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 349 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 350 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 351 } 352 353 aspeed_board_binfo.ram_size = ram_size; 354 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM]; 355 aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus; 356 357 if (amc->i2c_init) { 358 amc->i2c_init(bmc); 359 } 360 361 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 362 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); 363 } 364 365 if (bmc->soc.emmc.num_slots) { 366 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); 367 } 368 369 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 370 } 371 372 static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) 373 { 374 AspeedSoCState *soc = &bmc->soc; 375 DeviceState *dev; 376 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 377 378 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 379 * enough to provide basic RTC features. Alarms will be missing */ 380 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68); 381 382 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), 0x50, 383 eeprom_buf); 384 385 /* add a TMP423 temperature sensor */ 386 dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), 387 "tmp423", 0x4c); 388 object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort); 389 object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort); 390 object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort); 391 object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); 392 } 393 394 static void ast2500_evb_i2c_init(AspeedBoardState *bmc) 395 { 396 AspeedSoCState *soc = &bmc->soc; 397 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 398 399 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), 0x50, 400 eeprom_buf); 401 402 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 403 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), 404 TYPE_TMP105, 0x4d); 405 406 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 407 * plugged on the I2C bus header */ 408 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 409 } 410 411 static void ast2600_evb_i2c_init(AspeedBoardState *bmc) 412 { 413 /* Start with some devices on our I2C busses */ 414 ast2500_evb_i2c_init(bmc); 415 } 416 417 static void romulus_bmc_i2c_init(AspeedBoardState *bmc) 418 { 419 AspeedSoCState *soc = &bmc->soc; 420 421 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 422 * good enough */ 423 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 424 } 425 426 static void swift_bmc_i2c_init(AspeedBoardState *bmc) 427 { 428 AspeedSoCState *soc = &bmc->soc; 429 430 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", 0x60); 431 432 /* The swift board expects a TMP275 but a TMP105 is compatible */ 433 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x48); 434 /* The swift board expects a pca9551 but a pca9552 is compatible */ 435 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "pca9552", 0x60); 436 437 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ 438 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "ds1338", 0x32); 439 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60); 440 441 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp423", 0x4c); 442 /* The swift board expects a pca9539 but a pca9552 is compatible */ 443 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "pca9552", 0x74); 444 445 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "tmp423", 0x4c); 446 /* The swift board expects a pca9539 but a pca9552 is compatible */ 447 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "pca9552", 448 0x74); 449 450 /* The swift board expects a TMP275 but a TMP105 is compatible */ 451 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x48); 452 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x4a); 453 } 454 455 static void sonorapass_bmc_i2c_init(AspeedBoardState *bmc) 456 { 457 AspeedSoCState *soc = &bmc->soc; 458 459 /* bus 2 : */ 460 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), "tmp105", 0x48); 461 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), "tmp105", 0x49); 462 /* bus 2 : pca9546 @ 0x73 */ 463 464 /* bus 3 : pca9548 @ 0x70 */ 465 466 /* bus 4 : */ 467 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 468 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), 0x54, 469 eeprom4_54); 470 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 471 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "pca9552", 0x76); 472 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 473 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "pca9552", 0x77); 474 475 /* bus 6 : */ 476 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 6), "tmp105", 0x48); 477 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 6), "tmp105", 0x49); 478 /* bus 6 : pca9546 @ 0x73 */ 479 480 /* bus 8 : */ 481 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 482 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), 0x56, 483 eeprom8_56); 484 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60); 485 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x61); 486 /* bus 8 : adc128d818 @ 0x1d */ 487 /* bus 8 : adc128d818 @ 0x1f */ 488 489 /* 490 * bus 13 : pca9548 @ 0x71 491 * - channel 3: 492 * - tmm421 @ 0x4c 493 * - tmp421 @ 0x4e 494 * - tmp421 @ 0x4f 495 */ 496 497 } 498 499 static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) 500 { 501 AspeedSoCState *soc = &bmc->soc; 502 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 503 504 /* Bus 3: TODO bmp280@77 */ 505 /* Bus 3: TODO max31785@52 */ 506 /* Bus 3: TODO dps310@76 */ 507 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA9552, 508 0x60); 509 510 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c); 511 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c); 512 513 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 514 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), TYPE_TMP105, 515 0x4a); 516 517 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 518 * good enough */ 519 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 520 521 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51, 522 eeprom_buf); 523 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA9552, 524 0x60); 525 /* Bus 11: TODO ucd90160@64 */ 526 } 527 528 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 529 { 530 return ASPEED_MACHINE(obj)->mmio_exec; 531 } 532 533 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 534 { 535 ASPEED_MACHINE(obj)->mmio_exec = value; 536 } 537 538 static void aspeed_machine_instance_init(Object *obj) 539 { 540 ASPEED_MACHINE(obj)->mmio_exec = false; 541 } 542 543 static void aspeed_machine_class_props_init(ObjectClass *oc) 544 { 545 object_class_property_add_bool(oc, "execute-in-place", 546 aspeed_get_mmio_exec, 547 aspeed_set_mmio_exec); 548 object_class_property_set_description(oc, "execute-in-place", 549 "boot directly from CE0 flash device"); 550 } 551 552 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 553 { 554 MachineClass *mc = MACHINE_CLASS(oc); 555 556 mc->init = aspeed_machine_init; 557 mc->max_cpus = ASPEED_CPUS_NUM; 558 mc->no_floppy = 1; 559 mc->no_cdrom = 1; 560 mc->no_parallel = 1; 561 mc->default_ram_id = "ram"; 562 563 aspeed_machine_class_props_init(oc); 564 } 565 566 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 567 { 568 MachineClass *mc = MACHINE_CLASS(oc); 569 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 570 571 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 572 amc->soc_name = "ast2400-a1"; 573 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 574 amc->fmc_model = "n25q256a"; 575 amc->spi_model = "mx25l25635e"; 576 amc->num_cs = 1; 577 amc->i2c_init = palmetto_bmc_i2c_init; 578 mc->default_ram_size = 256 * MiB; 579 }; 580 581 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 582 { 583 MachineClass *mc = MACHINE_CLASS(oc); 584 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 585 586 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 587 amc->soc_name = "ast2500-a1"; 588 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 589 amc->fmc_model = "w25q256"; 590 amc->spi_model = "mx25l25635e"; 591 amc->num_cs = 1; 592 amc->i2c_init = ast2500_evb_i2c_init; 593 mc->default_ram_size = 512 * MiB; 594 }; 595 596 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 597 { 598 MachineClass *mc = MACHINE_CLASS(oc); 599 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 600 601 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 602 amc->soc_name = "ast2500-a1"; 603 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 604 amc->fmc_model = "n25q256a"; 605 amc->spi_model = "mx66l1g45g"; 606 amc->num_cs = 2; 607 amc->i2c_init = romulus_bmc_i2c_init; 608 mc->default_ram_size = 512 * MiB; 609 }; 610 611 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 612 { 613 MachineClass *mc = MACHINE_CLASS(oc); 614 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 615 616 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 617 amc->soc_name = "ast2500-a1"; 618 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 619 amc->fmc_model = "mx66l1g45g"; 620 amc->spi_model = "mx66l1g45g"; 621 amc->num_cs = 2; 622 amc->i2c_init = sonorapass_bmc_i2c_init; 623 mc->default_ram_size = 512 * MiB; 624 }; 625 626 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) 627 { 628 MachineClass *mc = MACHINE_CLASS(oc); 629 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 630 631 mc->desc = "OpenPOWER Swift BMC (ARM1176)"; 632 amc->soc_name = "ast2500-a1"; 633 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1; 634 amc->fmc_model = "mx66l1g45g"; 635 amc->spi_model = "mx66l1g45g"; 636 amc->num_cs = 2; 637 amc->i2c_init = swift_bmc_i2c_init; 638 mc->default_ram_size = 512 * MiB; 639 }; 640 641 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 642 { 643 MachineClass *mc = MACHINE_CLASS(oc); 644 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 645 646 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 647 amc->soc_name = "ast2500-a1"; 648 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 649 amc->fmc_model = "mx25l25635e"; 650 amc->spi_model = "mx66l1g45g"; 651 amc->num_cs = 2; 652 amc->i2c_init = witherspoon_bmc_i2c_init; 653 mc->default_ram_size = 512 * MiB; 654 }; 655 656 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 657 { 658 MachineClass *mc = MACHINE_CLASS(oc); 659 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 660 661 mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; 662 amc->soc_name = "ast2600-a1"; 663 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 664 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 665 amc->fmc_model = "w25q512jv"; 666 amc->spi_model = "mx66u51235f"; 667 amc->num_cs = 1; 668 amc->i2c_init = ast2600_evb_i2c_init; 669 mc->default_ram_size = 1 * GiB; 670 }; 671 672 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 673 { 674 MachineClass *mc = MACHINE_CLASS(oc); 675 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 676 677 mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)"; 678 amc->soc_name = "ast2600-a1"; 679 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 680 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 681 amc->fmc_model = "mx66l1g45g"; 682 amc->spi_model = "mx66l1g45g"; 683 amc->num_cs = 2; 684 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 685 mc->default_ram_size = 1 * GiB; 686 }; 687 688 static const TypeInfo aspeed_machine_types[] = { 689 { 690 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 691 .parent = TYPE_ASPEED_MACHINE, 692 .class_init = aspeed_machine_palmetto_class_init, 693 }, { 694 .name = MACHINE_TYPE_NAME("ast2500-evb"), 695 .parent = TYPE_ASPEED_MACHINE, 696 .class_init = aspeed_machine_ast2500_evb_class_init, 697 }, { 698 .name = MACHINE_TYPE_NAME("romulus-bmc"), 699 .parent = TYPE_ASPEED_MACHINE, 700 .class_init = aspeed_machine_romulus_class_init, 701 }, { 702 .name = MACHINE_TYPE_NAME("swift-bmc"), 703 .parent = TYPE_ASPEED_MACHINE, 704 .class_init = aspeed_machine_swift_class_init, 705 }, { 706 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 707 .parent = TYPE_ASPEED_MACHINE, 708 .class_init = aspeed_machine_sonorapass_class_init, 709 }, { 710 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 711 .parent = TYPE_ASPEED_MACHINE, 712 .class_init = aspeed_machine_witherspoon_class_init, 713 }, { 714 .name = MACHINE_TYPE_NAME("ast2600-evb"), 715 .parent = TYPE_ASPEED_MACHINE, 716 .class_init = aspeed_machine_ast2600_evb_class_init, 717 }, { 718 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 719 .parent = TYPE_ASPEED_MACHINE, 720 .class_init = aspeed_machine_tacoma_class_init, 721 }, { 722 .name = TYPE_ASPEED_MACHINE, 723 .parent = TYPE_MACHINE, 724 .instance_size = sizeof(AspeedMachine), 725 .instance_init = aspeed_machine_instance_init, 726 .class_size = sizeof(AspeedMachineClass), 727 .class_init = aspeed_machine_class_init, 728 .abstract = true, 729 } 730 }; 731 732 DEFINE_TYPES(aspeed_machine_types) 733