1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/i2c/i2c_mux_pca954x.h" 18 #include "hw/i2c/smbus_eeprom.h" 19 #include "hw/misc/pca9552.h" 20 #include "hw/sensor/tmp105.h" 21 #include "hw/misc/led.h" 22 #include "hw/qdev-properties.h" 23 #include "sysemu/block-backend.h" 24 #include "sysemu/reset.h" 25 #include "hw/loader.h" 26 #include "qemu/error-report.h" 27 #include "qemu/units.h" 28 #include "hw/qdev-clock.h" 29 30 static struct arm_boot_info aspeed_board_binfo = { 31 .board_id = -1, /* device-tree-only board */ 32 }; 33 34 struct AspeedMachineState { 35 /* Private */ 36 MachineState parent_obj; 37 /* Public */ 38 39 AspeedSoCState soc; 40 MemoryRegion ram_container; 41 MemoryRegion max_ram; 42 bool mmio_exec; 43 char *fmc_model; 44 char *spi_model; 45 }; 46 47 /* Palmetto hardware value: 0x120CE416 */ 48 #define PALMETTO_BMC_HW_STRAP1 ( \ 49 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 50 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 51 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 52 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 53 SCU_HW_STRAP_VGA_CLASS_CODE | \ 54 SCU_HW_STRAP_LPC_RESET_PIN | \ 55 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 56 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 57 SCU_HW_STRAP_SPI_WIDTH | \ 58 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 59 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 60 61 /* TODO: Find the actual hardware value */ 62 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 63 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 64 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 65 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 66 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 67 SCU_HW_STRAP_VGA_CLASS_CODE | \ 68 SCU_HW_STRAP_LPC_RESET_PIN | \ 69 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 70 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 71 SCU_HW_STRAP_SPI_WIDTH | \ 72 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 73 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 74 75 /* AST2500 evb hardware value: 0xF100C2E6 */ 76 #define AST2500_EVB_HW_STRAP1 (( \ 77 AST2500_HW_STRAP1_DEFAULTS | \ 78 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 79 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 80 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 81 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 82 SCU_HW_STRAP_MAC1_RGMII | \ 83 SCU_HW_STRAP_MAC0_RGMII) & \ 84 ~SCU_HW_STRAP_2ND_BOOT_WDT) 85 86 /* Romulus hardware value: 0xF10AD206 */ 87 #define ROMULUS_BMC_HW_STRAP1 ( \ 88 AST2500_HW_STRAP1_DEFAULTS | \ 89 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 90 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 91 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 92 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 93 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 94 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 95 96 /* Sonorapass hardware value: 0xF100D216 */ 97 #define SONORAPASS_BMC_HW_STRAP1 ( \ 98 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 99 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 100 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 101 SCU_AST2500_HW_STRAP_RESERVED28 | \ 102 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 103 SCU_HW_STRAP_VGA_CLASS_CODE | \ 104 SCU_HW_STRAP_LPC_RESET_PIN | \ 105 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 106 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 107 SCU_HW_STRAP_VGA_BIOS_ROM | \ 108 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 109 SCU_AST2500_HW_STRAP_RESERVED1) 110 111 #define G220A_BMC_HW_STRAP1 ( \ 112 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 113 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 114 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 115 SCU_AST2500_HW_STRAP_RESERVED28 | \ 116 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 117 SCU_HW_STRAP_2ND_BOOT_WDT | \ 118 SCU_HW_STRAP_VGA_CLASS_CODE | \ 119 SCU_HW_STRAP_LPC_RESET_PIN | \ 120 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 121 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 122 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 123 SCU_AST2500_HW_STRAP_RESERVED1) 124 125 /* FP5280G2 hardware value: 0XF100D286 */ 126 #define FP5280G2_BMC_HW_STRAP1 ( \ 127 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 128 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 129 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 130 SCU_AST2500_HW_STRAP_RESERVED28 | \ 131 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 132 SCU_HW_STRAP_VGA_CLASS_CODE | \ 133 SCU_HW_STRAP_LPC_RESET_PIN | \ 134 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 135 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 136 SCU_HW_STRAP_MAC1_RGMII | \ 137 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 138 SCU_AST2500_HW_STRAP_RESERVED1) 139 140 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 141 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 142 143 /* Quanta-Q71l hardware value */ 144 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 145 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 146 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 147 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 148 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 149 SCU_HW_STRAP_VGA_CLASS_CODE | \ 150 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 151 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 152 SCU_HW_STRAP_SPI_WIDTH | \ 153 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 154 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 155 156 /* AST2600 evb hardware value */ 157 #define AST2600_EVB_HW_STRAP1 0x000000C0 158 #define AST2600_EVB_HW_STRAP2 0x00000003 159 160 /* Tacoma hardware value */ 161 #define TACOMA_BMC_HW_STRAP1 0x00000000 162 #define TACOMA_BMC_HW_STRAP2 0x00000040 163 164 /* Rainier hardware value: (QEMU prototype) */ 165 #define RAINIER_BMC_HW_STRAP1 0x00422016 166 #define RAINIER_BMC_HW_STRAP2 0x80000848 167 168 /* Fuji hardware value */ 169 #define FUJI_BMC_HW_STRAP1 0x00000000 170 #define FUJI_BMC_HW_STRAP2 0x00000000 171 172 /* Bletchley hardware value */ 173 /* TODO: Leave same as EVB for now. */ 174 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 175 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 176 177 /* 178 * The max ram region is for firmwares that scan the address space 179 * with load/store to guess how much RAM the SoC has. 180 */ 181 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 182 { 183 return 0; 184 } 185 186 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 187 unsigned size) 188 { 189 /* Discard writes */ 190 } 191 192 static const MemoryRegionOps max_ram_ops = { 193 .read = max_ram_read, 194 .write = max_ram_write, 195 .endianness = DEVICE_NATIVE_ENDIAN, 196 }; 197 198 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 199 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 200 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 201 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 202 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 203 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 204 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 205 206 static void aspeed_write_smpboot(ARMCPU *cpu, 207 const struct arm_boot_info *info) 208 { 209 static const uint32_t poll_mailbox_ready[] = { 210 /* 211 * r2 = per-cpu go sign value 212 * r1 = AST_SMP_MBOX_FIELD_ENTRY 213 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 214 */ 215 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 216 0xe21000ff, /* ands r0, r0, #255 */ 217 0xe59f201c, /* ldr r2, [pc, #28] */ 218 0xe1822000, /* orr r2, r2, r0 */ 219 220 0xe59f1018, /* ldr r1, [pc, #24] */ 221 0xe59f0018, /* ldr r0, [pc, #24] */ 222 223 0xe320f002, /* wfe */ 224 0xe5904000, /* ldr r4, [r0] */ 225 0xe1520004, /* cmp r2, r4 */ 226 0x1afffffb, /* bne <wfe> */ 227 0xe591f000, /* ldr pc, [r1] */ 228 AST_SMP_MBOX_GOSIGN, 229 AST_SMP_MBOX_FIELD_ENTRY, 230 AST_SMP_MBOX_FIELD_GOSIGN, 231 }; 232 233 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 234 sizeof(poll_mailbox_ready), 235 info->smp_loader_start); 236 } 237 238 static void aspeed_reset_secondary(ARMCPU *cpu, 239 const struct arm_boot_info *info) 240 { 241 AddressSpace *as = arm_boot_address_space(cpu, info); 242 CPUState *cs = CPU(cpu); 243 244 /* info->smp_bootreg_addr */ 245 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 246 MEMTXATTRS_UNSPECIFIED, NULL); 247 cpu_set_pc(cs, info->smp_loader_start); 248 } 249 250 #define FIRMWARE_ADDR 0x0 251 252 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 253 Error **errp) 254 { 255 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 256 g_autofree void *storage = NULL; 257 int64_t size; 258 259 /* The block backend size should have already been 'validated' by 260 * the creation of the m25p80 object. 261 */ 262 size = blk_getlength(blk); 263 if (size <= 0) { 264 error_setg(errp, "failed to get flash size"); 265 return; 266 } 267 268 if (rom_size > size) { 269 rom_size = size; 270 } 271 272 storage = g_malloc0(rom_size); 273 if (blk_pread(blk, 0, storage, rom_size) < 0) { 274 error_setg(errp, "failed to read the initial flash content"); 275 return; 276 } 277 278 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 279 } 280 281 static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 282 unsigned int count, int unit0) 283 { 284 int i; 285 286 if (!flashtype) { 287 return; 288 } 289 290 for (i = 0; i < count; ++i) { 291 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 292 qemu_irq cs_line; 293 DeviceState *dev; 294 295 dev = qdev_new(flashtype); 296 if (dinfo) { 297 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 298 } 299 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 300 301 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); 302 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 303 } 304 } 305 306 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 307 { 308 DeviceState *card; 309 310 if (!dinfo) { 311 return; 312 } 313 card = qdev_new(TYPE_SD_CARD); 314 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 315 &error_fatal); 316 qdev_realize_and_unref(card, 317 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 318 &error_fatal); 319 } 320 321 static void aspeed_machine_init(MachineState *machine) 322 { 323 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 324 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 325 AspeedSoCClass *sc; 326 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 327 ram_addr_t max_ram_size; 328 int i; 329 NICInfo *nd = &nd_table[0]; 330 331 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 332 4 * GiB); 333 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 334 335 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 336 337 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 338 339 /* 340 * This will error out if isize is not supported by memory controller. 341 */ 342 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size, 343 &error_fatal); 344 345 for (i = 0; i < sc->macs_num; i++) { 346 if ((amc->macs_mask & (1 << i)) && nd->used) { 347 qemu_check_nic_model(nd, TYPE_FTGMAC100); 348 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 349 nd++; 350 } 351 } 352 353 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 354 &error_abort); 355 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 356 &error_abort); 357 object_property_set_link(OBJECT(&bmc->soc), "dram", 358 OBJECT(machine->ram), &error_abort); 359 if (machine->kernel_filename) { 360 /* 361 * When booting with a -kernel command line there is no u-boot 362 * that runs to unlock the SCU. In this case set the default to 363 * be unlocked as the kernel expects 364 */ 365 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 366 ASPEED_SCU_PROT_KEY, &error_abort); 367 } 368 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", 369 amc->uart_default); 370 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 371 372 memory_region_add_subregion(get_system_memory(), 373 sc->memmap[ASPEED_DEV_SDRAM], 374 &bmc->ram_container); 375 376 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 377 &error_abort); 378 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 379 "max_ram", max_ram_size - machine->ram_size); 380 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram); 381 382 aspeed_board_init_flashes(&bmc->soc.fmc, 383 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 384 amc->num_cs, 0); 385 aspeed_board_init_flashes(&bmc->soc.spi[0], 386 bmc->spi_model ? bmc->spi_model : amc->spi_model, 387 1, amc->num_cs); 388 389 /* Install first FMC flash content as a boot rom. */ 390 if (drive0) { 391 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 392 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 393 uint64_t size = memory_region_size(&fl->mmio); 394 395 /* 396 * create a ROM region using the default mapping window size of 397 * the flash module. The window size is 64MB for the AST2400 398 * SoC and 128MB for the AST2500 SoC, which is twice as big as 399 * needed by the flash modules of the Aspeed machines. 400 */ 401 if (ASPEED_MACHINE(machine)->mmio_exec) { 402 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", 403 &fl->mmio, 0, size); 404 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 405 boot_rom); 406 } else { 407 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", 408 size, &error_abort); 409 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 410 boot_rom); 411 write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort); 412 } 413 } 414 415 if (machine->kernel_filename && sc->num_cpus > 1) { 416 /* With no u-boot we must set up a boot stub for the secondary CPU */ 417 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 418 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 419 0x80, &error_abort); 420 memory_region_add_subregion(get_system_memory(), 421 AST_SMP_MAILBOX_BASE, smpboot); 422 423 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 424 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 425 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 426 } 427 428 aspeed_board_binfo.ram_size = machine->ram_size; 429 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 430 431 if (amc->i2c_init) { 432 amc->i2c_init(bmc); 433 } 434 435 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 436 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], 437 drive_get(IF_SD, 0, i)); 438 } 439 440 if (bmc->soc.emmc.num_slots) { 441 sdhci_attach_drive(&bmc->soc.emmc.slots[0], 442 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots)); 443 } 444 445 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 446 } 447 448 static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize) 449 { 450 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 451 DeviceState *dev = DEVICE(i2c_dev); 452 453 qdev_prop_set_uint32(dev, "rom-size", rsize); 454 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); 455 } 456 457 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 458 { 459 AspeedSoCState *soc = &bmc->soc; 460 DeviceState *dev; 461 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 462 463 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 464 * enough to provide basic RTC features. Alarms will be missing */ 465 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 466 467 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 468 eeprom_buf); 469 470 /* add a TMP423 temperature sensor */ 471 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 472 "tmp423", 0x4c)); 473 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 474 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 475 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 476 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 477 } 478 479 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 480 { 481 AspeedSoCState *soc = &bmc->soc; 482 483 /* 484 * The quanta-q71l platform expects tmp75s which are compatible with 485 * tmp105s. 486 */ 487 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 488 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 489 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 490 491 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 492 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 493 /* TODO: Add Memory Riser i2c mux and eeproms. */ 494 495 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 496 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 497 498 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 499 500 /* i2c-7 */ 501 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 502 /* - i2c@0: pmbus@59 */ 503 /* - i2c@1: pmbus@58 */ 504 /* - i2c@2: pmbus@58 */ 505 /* - i2c@3: pmbus@59 */ 506 507 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 508 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 509 } 510 511 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 512 { 513 AspeedSoCState *soc = &bmc->soc; 514 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 515 516 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 517 eeprom_buf); 518 519 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 520 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 521 TYPE_TMP105, 0x4d); 522 } 523 524 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 525 { 526 AspeedSoCState *soc = &bmc->soc; 527 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 528 529 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 530 eeprom_buf); 531 532 /* LM75 is compatible with TMP105 driver */ 533 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 534 TYPE_TMP105, 0x4d); 535 } 536 537 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 538 { 539 AspeedSoCState *soc = &bmc->soc; 540 541 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 542 * good enough */ 543 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 544 } 545 546 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 547 { 548 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 549 TYPE_PCA9552, addr); 550 } 551 552 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 553 { 554 AspeedSoCState *soc = &bmc->soc; 555 556 /* bus 2 : */ 557 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 558 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 559 /* bus 2 : pca9546 @ 0x73 */ 560 561 /* bus 3 : pca9548 @ 0x70 */ 562 563 /* bus 4 : */ 564 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 565 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 566 eeprom4_54); 567 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 568 create_pca9552(soc, 4, 0x76); 569 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 570 create_pca9552(soc, 4, 0x77); 571 572 /* bus 6 : */ 573 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 574 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 575 /* bus 6 : pca9546 @ 0x73 */ 576 577 /* bus 8 : */ 578 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 579 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 580 eeprom8_56); 581 create_pca9552(soc, 8, 0x60); 582 create_pca9552(soc, 8, 0x61); 583 /* bus 8 : adc128d818 @ 0x1d */ 584 /* bus 8 : adc128d818 @ 0x1f */ 585 586 /* 587 * bus 13 : pca9548 @ 0x71 588 * - channel 3: 589 * - tmm421 @ 0x4c 590 * - tmp421 @ 0x4e 591 * - tmp421 @ 0x4f 592 */ 593 594 } 595 596 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 597 { 598 static const struct { 599 unsigned gpio_id; 600 LEDColor color; 601 const char *description; 602 bool gpio_polarity; 603 } pca1_leds[] = { 604 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 605 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 606 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 607 }; 608 AspeedSoCState *soc = &bmc->soc; 609 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 610 DeviceState *dev; 611 LEDState *led; 612 613 /* Bus 3: TODO bmp280@77 */ 614 /* Bus 3: TODO max31785@52 */ 615 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 616 qdev_prop_set_string(dev, "description", "pca1"); 617 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 618 aspeed_i2c_get_bus(&soc->i2c, 3), 619 &error_fatal); 620 621 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 622 led = led_create_simple(OBJECT(bmc), 623 pca1_leds[i].gpio_polarity, 624 pca1_leds[i].color, 625 pca1_leds[i].description); 626 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 627 qdev_get_gpio_in(DEVICE(led), 0)); 628 } 629 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 630 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 631 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 632 633 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 634 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 635 0x4a); 636 637 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 638 * good enough */ 639 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 640 641 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 642 eeprom_buf); 643 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 644 qdev_prop_set_string(dev, "description", "pca0"); 645 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 646 aspeed_i2c_get_bus(&soc->i2c, 11), 647 &error_fatal); 648 /* Bus 11: TODO ucd90160@64 */ 649 } 650 651 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 652 { 653 AspeedSoCState *soc = &bmc->soc; 654 DeviceState *dev; 655 656 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 657 "emc1413", 0x4c)); 658 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 659 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 660 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 661 662 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 663 "emc1413", 0x4c)); 664 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 665 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 666 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 667 668 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 669 "emc1413", 0x4c)); 670 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 671 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 672 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 673 674 static uint8_t eeprom_buf[2 * 1024] = { 675 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 676 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 677 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 678 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 679 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 680 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 681 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 682 }; 683 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 684 eeprom_buf); 685 } 686 687 static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize) 688 { 689 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 690 DeviceState *dev = DEVICE(i2c_dev); 691 692 qdev_prop_set_uint32(dev, "rom-size", rsize); 693 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); 694 } 695 696 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 697 { 698 AspeedSoCState *soc = &bmc->soc; 699 I2CSlave *i2c_mux; 700 701 /* The at24c256 */ 702 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 703 704 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 705 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 706 0x48); 707 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 708 0x49); 709 710 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 711 "pca9546", 0x70); 712 /* It expects a TMP112 but a TMP105 is compatible */ 713 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 714 0x4a); 715 716 /* It expects a ds3232 but a ds1338 is good enough */ 717 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 718 719 /* It expects a pca9555 but a pca9552 is compatible */ 720 create_pca9552(soc, 8, 0x30); 721 } 722 723 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 724 { 725 AspeedSoCState *soc = &bmc->soc; 726 I2CSlave *i2c_mux; 727 728 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 729 730 create_pca9552(soc, 3, 0x61); 731 732 /* The rainier expects a TMP275 but a TMP105 is compatible */ 733 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 734 0x48); 735 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 736 0x49); 737 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 738 0x4a); 739 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 740 "pca9546", 0x70); 741 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 742 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 743 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 744 create_pca9552(soc, 4, 0x60); 745 746 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 747 0x48); 748 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 749 0x49); 750 create_pca9552(soc, 5, 0x60); 751 create_pca9552(soc, 5, 0x61); 752 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 753 "pca9546", 0x70); 754 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 755 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 756 757 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 758 0x48); 759 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 760 0x4a); 761 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 762 0x4b); 763 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 764 "pca9546", 0x70); 765 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 766 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 767 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 768 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 769 770 create_pca9552(soc, 7, 0x30); 771 create_pca9552(soc, 7, 0x31); 772 create_pca9552(soc, 7, 0x32); 773 create_pca9552(soc, 7, 0x33); 774 /* Bus 7: TODO max31785@52 */ 775 create_pca9552(soc, 7, 0x60); 776 create_pca9552(soc, 7, 0x61); 777 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 778 /* Bus 7: TODO si7021-a20@20 */ 779 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 780 0x48); 781 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 782 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 783 784 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 785 0x48); 786 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 787 0x4a); 788 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB); 789 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB); 790 create_pca9552(soc, 8, 0x60); 791 create_pca9552(soc, 8, 0x61); 792 /* Bus 8: ucd90320@11 */ 793 /* Bus 8: ucd90320@b */ 794 /* Bus 8: ucd90320@c */ 795 796 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 797 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 798 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 799 800 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 801 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 802 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 803 804 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 805 0x48); 806 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 807 0x49); 808 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 809 "pca9546", 0x70); 810 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 811 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 812 create_pca9552(soc, 11, 0x60); 813 814 815 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 816 create_pca9552(soc, 13, 0x60); 817 818 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 819 create_pca9552(soc, 14, 0x60); 820 821 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 822 create_pca9552(soc, 15, 0x60); 823 } 824 825 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 826 I2CBus **channels) 827 { 828 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 829 for (int i = 0; i < 8; i++) { 830 channels[i] = pca954x_i2c_get_bus(mux, i); 831 } 832 } 833 834 #define TYPE_LM75 TYPE_TMP105 835 #define TYPE_TMP75 TYPE_TMP105 836 #define TYPE_TMP422 "tmp422" 837 838 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 839 { 840 AspeedSoCState *soc = &bmc->soc; 841 I2CBus *i2c[144] = {}; 842 843 for (int i = 0; i < 16; i++) { 844 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 845 } 846 I2CBus *i2c180 = i2c[2]; 847 I2CBus *i2c480 = i2c[8]; 848 I2CBus *i2c600 = i2c[11]; 849 850 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 851 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 852 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 853 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 854 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 855 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 856 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 857 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 858 for (int i = 0; i < 8; i++) { 859 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 860 } 861 862 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 863 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 864 865 aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB); 866 aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB); 867 aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB); 868 869 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 870 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 871 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 872 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 873 874 aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB); 875 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 876 877 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 878 aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB); 879 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 880 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 881 882 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 883 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 884 885 aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB); 886 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 887 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 888 aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB); 889 aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB); 890 aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB); 891 aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB); 892 893 aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB); 894 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 895 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 896 aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB); 897 aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB); 898 aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB); 899 aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB); 900 aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB); 901 902 for (int i = 0; i < 8; i++) { 903 aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 904 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 905 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 906 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 907 } 908 } 909 910 #define TYPE_TMP421 "tmp421" 911 912 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 913 { 914 AspeedSoCState *soc = &bmc->soc; 915 I2CBus *i2c[13] = {}; 916 for (int i = 0; i < 13; i++) { 917 if ((i == 8) || (i == 11)) { 918 continue; 919 } 920 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 921 } 922 923 /* Bus 0 - 5 all have the same config. */ 924 for (int i = 0; i < 6; i++) { 925 /* Missing model: ti,ina230 @ 0x45 */ 926 /* Missing model: mps,mp5023 @ 0x40 */ 927 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 928 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 929 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 930 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 931 /* Missing model: fsc,fusb302 @ 0x22 */ 932 } 933 934 /* Bus 6 */ 935 at24c_eeprom_init(i2c[6], 0x56, 65536); 936 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 937 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 938 939 940 /* Bus 7 */ 941 at24c_eeprom_init(i2c[7], 0x54, 65536); 942 943 /* Bus 9 */ 944 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 945 946 /* Bus 10 */ 947 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 948 /* Missing model: ti,hdc1080 @ 0x40 */ 949 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 950 951 /* Bus 12 */ 952 /* Missing model: adi,adm1278 @ 0x11 */ 953 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 954 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 955 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 956 } 957 958 static void fby35_i2c_init(AspeedMachineState *bmc) 959 { 960 AspeedSoCState *soc = &bmc->soc; 961 I2CBus *i2c[16]; 962 963 for (int i = 0; i < 16; i++) { 964 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 965 } 966 967 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 968 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 969 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 970 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 971 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 972 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 973 974 aspeed_eeprom_init(i2c[4], 0x51, 128 * KiB); 975 aspeed_eeprom_init(i2c[6], 0x51, 128 * KiB); 976 aspeed_eeprom_init(i2c[8], 0x50, 32 * KiB); 977 aspeed_eeprom_init(i2c[11], 0x51, 128 * KiB); 978 aspeed_eeprom_init(i2c[11], 0x54, 128 * KiB); 979 980 /* 981 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 982 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 983 * each. 984 */ 985 } 986 987 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 988 { 989 return ASPEED_MACHINE(obj)->mmio_exec; 990 } 991 992 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 993 { 994 ASPEED_MACHINE(obj)->mmio_exec = value; 995 } 996 997 static void aspeed_machine_instance_init(Object *obj) 998 { 999 ASPEED_MACHINE(obj)->mmio_exec = false; 1000 } 1001 1002 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1003 { 1004 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1005 return g_strdup(bmc->fmc_model); 1006 } 1007 1008 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1009 { 1010 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1011 1012 g_free(bmc->fmc_model); 1013 bmc->fmc_model = g_strdup(value); 1014 } 1015 1016 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1017 { 1018 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1019 return g_strdup(bmc->spi_model); 1020 } 1021 1022 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1023 { 1024 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1025 1026 g_free(bmc->spi_model); 1027 bmc->spi_model = g_strdup(value); 1028 } 1029 1030 static void aspeed_machine_class_props_init(ObjectClass *oc) 1031 { 1032 object_class_property_add_bool(oc, "execute-in-place", 1033 aspeed_get_mmio_exec, 1034 aspeed_set_mmio_exec); 1035 object_class_property_set_description(oc, "execute-in-place", 1036 "boot directly from CE0 flash device"); 1037 1038 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1039 aspeed_set_fmc_model); 1040 object_class_property_set_description(oc, "fmc-model", 1041 "Change the FMC Flash model"); 1042 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1043 aspeed_set_spi_model); 1044 object_class_property_set_description(oc, "spi-model", 1045 "Change the SPI Flash model"); 1046 } 1047 1048 static int aspeed_soc_num_cpus(const char *soc_name) 1049 { 1050 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 1051 return sc->num_cpus; 1052 } 1053 1054 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1055 { 1056 MachineClass *mc = MACHINE_CLASS(oc); 1057 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1058 1059 mc->init = aspeed_machine_init; 1060 mc->no_floppy = 1; 1061 mc->no_cdrom = 1; 1062 mc->no_parallel = 1; 1063 mc->default_ram_id = "ram"; 1064 amc->macs_mask = ASPEED_MAC0_ON; 1065 amc->uart_default = ASPEED_DEV_UART5; 1066 1067 aspeed_machine_class_props_init(oc); 1068 } 1069 1070 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1071 { 1072 MachineClass *mc = MACHINE_CLASS(oc); 1073 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1074 1075 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1076 amc->soc_name = "ast2400-a1"; 1077 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1078 amc->fmc_model = "n25q256a"; 1079 amc->spi_model = "mx25l25635e"; 1080 amc->num_cs = 1; 1081 amc->i2c_init = palmetto_bmc_i2c_init; 1082 mc->default_ram_size = 256 * MiB; 1083 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1084 aspeed_soc_num_cpus(amc->soc_name); 1085 }; 1086 1087 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1088 { 1089 MachineClass *mc = MACHINE_CLASS(oc); 1090 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1091 1092 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1093 amc->soc_name = "ast2400-a1"; 1094 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1095 amc->fmc_model = "n25q256a"; 1096 amc->spi_model = "mx25l25635e"; 1097 amc->num_cs = 1; 1098 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1099 mc->default_ram_size = 128 * MiB; 1100 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1101 aspeed_soc_num_cpus(amc->soc_name); 1102 } 1103 1104 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1105 void *data) 1106 { 1107 MachineClass *mc = MACHINE_CLASS(oc); 1108 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1109 1110 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1111 amc->soc_name = "ast2400-a1"; 1112 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1113 amc->fmc_model = "mx25l25635e"; 1114 amc->spi_model = "mx25l25635e"; 1115 amc->num_cs = 1; 1116 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1117 amc->i2c_init = palmetto_bmc_i2c_init; 1118 mc->default_ram_size = 256 * MiB; 1119 } 1120 1121 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1122 { 1123 MachineClass *mc = MACHINE_CLASS(oc); 1124 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1125 1126 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1127 amc->soc_name = "ast2500-a1"; 1128 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1129 amc->fmc_model = "mx25l25635e"; 1130 amc->spi_model = "mx25l25635e"; 1131 amc->num_cs = 1; 1132 amc->i2c_init = ast2500_evb_i2c_init; 1133 mc->default_ram_size = 512 * MiB; 1134 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1135 aspeed_soc_num_cpus(amc->soc_name); 1136 }; 1137 1138 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1139 { 1140 MachineClass *mc = MACHINE_CLASS(oc); 1141 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1142 1143 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1144 amc->soc_name = "ast2500-a1"; 1145 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1146 amc->fmc_model = "n25q256a"; 1147 amc->spi_model = "mx66l1g45g"; 1148 amc->num_cs = 2; 1149 amc->i2c_init = romulus_bmc_i2c_init; 1150 mc->default_ram_size = 512 * MiB; 1151 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1152 aspeed_soc_num_cpus(amc->soc_name); 1153 }; 1154 1155 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1156 { 1157 MachineClass *mc = MACHINE_CLASS(oc); 1158 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1159 1160 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1161 amc->soc_name = "ast2500-a1"; 1162 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1163 amc->fmc_model = "mx66l1g45g"; 1164 amc->spi_model = "mx66l1g45g"; 1165 amc->num_cs = 2; 1166 amc->i2c_init = sonorapass_bmc_i2c_init; 1167 mc->default_ram_size = 512 * MiB; 1168 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1169 aspeed_soc_num_cpus(amc->soc_name); 1170 }; 1171 1172 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1173 { 1174 MachineClass *mc = MACHINE_CLASS(oc); 1175 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1176 1177 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1178 amc->soc_name = "ast2500-a1"; 1179 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1180 amc->fmc_model = "mx25l25635e"; 1181 amc->spi_model = "mx66l1g45g"; 1182 amc->num_cs = 2; 1183 amc->i2c_init = witherspoon_bmc_i2c_init; 1184 mc->default_ram_size = 512 * MiB; 1185 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1186 aspeed_soc_num_cpus(amc->soc_name); 1187 }; 1188 1189 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1190 { 1191 MachineClass *mc = MACHINE_CLASS(oc); 1192 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1193 1194 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1195 amc->soc_name = "ast2600-a3"; 1196 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1197 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1198 amc->fmc_model = "mx66u51235f"; 1199 amc->spi_model = "mx66u51235f"; 1200 amc->num_cs = 1; 1201 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1202 ASPEED_MAC3_ON; 1203 amc->i2c_init = ast2600_evb_i2c_init; 1204 mc->default_ram_size = 1 * GiB; 1205 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1206 aspeed_soc_num_cpus(amc->soc_name); 1207 }; 1208 1209 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1210 { 1211 MachineClass *mc = MACHINE_CLASS(oc); 1212 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1213 1214 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1215 amc->soc_name = "ast2600-a3"; 1216 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1217 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1218 amc->fmc_model = "mx66l1g45g"; 1219 amc->spi_model = "mx66l1g45g"; 1220 amc->num_cs = 2; 1221 amc->macs_mask = ASPEED_MAC2_ON; 1222 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1223 mc->default_ram_size = 1 * GiB; 1224 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1225 aspeed_soc_num_cpus(amc->soc_name); 1226 }; 1227 1228 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1229 { 1230 MachineClass *mc = MACHINE_CLASS(oc); 1231 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1232 1233 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1234 amc->soc_name = "ast2500-a1"; 1235 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1236 amc->fmc_model = "n25q512a"; 1237 amc->spi_model = "mx25l25635e"; 1238 amc->num_cs = 2; 1239 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1240 amc->i2c_init = g220a_bmc_i2c_init; 1241 mc->default_ram_size = 1024 * MiB; 1242 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1243 aspeed_soc_num_cpus(amc->soc_name); 1244 }; 1245 1246 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1247 { 1248 MachineClass *mc = MACHINE_CLASS(oc); 1249 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1250 1251 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1252 amc->soc_name = "ast2500-a1"; 1253 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1254 amc->fmc_model = "n25q512a"; 1255 amc->spi_model = "mx25l25635e"; 1256 amc->num_cs = 2; 1257 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1258 amc->i2c_init = fp5280g2_bmc_i2c_init; 1259 mc->default_ram_size = 512 * MiB; 1260 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1261 aspeed_soc_num_cpus(amc->soc_name); 1262 }; 1263 1264 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1265 { 1266 MachineClass *mc = MACHINE_CLASS(oc); 1267 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1268 1269 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1270 amc->soc_name = "ast2600-a3"; 1271 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1272 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1273 amc->fmc_model = "mx66l1g45g"; 1274 amc->spi_model = "mx66l1g45g"; 1275 amc->num_cs = 2; 1276 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1277 amc->i2c_init = rainier_bmc_i2c_init; 1278 mc->default_ram_size = 1 * GiB; 1279 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1280 aspeed_soc_num_cpus(amc->soc_name); 1281 }; 1282 1283 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 1284 #if HOST_LONG_BITS == 32 1285 #define FUJI_BMC_RAM_SIZE (1 * GiB) 1286 #else 1287 #define FUJI_BMC_RAM_SIZE (2 * GiB) 1288 #endif 1289 1290 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1291 { 1292 MachineClass *mc = MACHINE_CLASS(oc); 1293 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1294 1295 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1296 amc->soc_name = "ast2600-a3"; 1297 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1298 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1299 amc->fmc_model = "mx66l1g45g"; 1300 amc->spi_model = "mx66l1g45g"; 1301 amc->num_cs = 2; 1302 amc->macs_mask = ASPEED_MAC3_ON; 1303 amc->i2c_init = fuji_bmc_i2c_init; 1304 amc->uart_default = ASPEED_DEV_UART1; 1305 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1306 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1307 aspeed_soc_num_cpus(amc->soc_name); 1308 }; 1309 1310 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1311 { 1312 MachineClass *mc = MACHINE_CLASS(oc); 1313 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1314 1315 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1316 amc->soc_name = "ast2600-a3"; 1317 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1318 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1319 amc->fmc_model = "w25q01jvq"; 1320 amc->spi_model = NULL; 1321 amc->num_cs = 2; 1322 amc->macs_mask = ASPEED_MAC2_ON; 1323 amc->i2c_init = bletchley_bmc_i2c_init; 1324 mc->default_ram_size = 512 * MiB; 1325 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1326 aspeed_soc_num_cpus(amc->soc_name); 1327 } 1328 1329 static void fby35_reset(MachineState *state) 1330 { 1331 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1332 AspeedGPIOState *gpio = &bmc->soc.gpio; 1333 1334 qemu_devices_reset(); 1335 1336 /* Board ID */ 1337 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1338 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1339 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1340 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1341 } 1342 1343 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) 1344 { 1345 MachineClass *mc = MACHINE_CLASS(oc); 1346 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1347 1348 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1349 mc->reset = fby35_reset; 1350 amc->fmc_model = "mx66l1g45g"; 1351 amc->num_cs = 2; 1352 amc->macs_mask = ASPEED_MAC3_ON; 1353 amc->i2c_init = fby35_i2c_init; 1354 /* FIXME: Replace this macro with something more general */ 1355 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1356 } 1357 1358 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1359 /* Main SYSCLK frequency in Hz (200MHz) */ 1360 #define SYSCLK_FRQ 200000000ULL 1361 1362 static void aspeed_minibmc_machine_init(MachineState *machine) 1363 { 1364 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1365 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1366 Clock *sysclk; 1367 1368 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1369 clock_set_hz(sysclk, SYSCLK_FRQ); 1370 1371 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 1372 qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk); 1373 1374 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", 1375 amc->uart_default); 1376 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 1377 1378 aspeed_board_init_flashes(&bmc->soc.fmc, 1379 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1380 amc->num_cs, 1381 0); 1382 1383 aspeed_board_init_flashes(&bmc->soc.spi[0], 1384 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1385 amc->num_cs, amc->num_cs); 1386 1387 aspeed_board_init_flashes(&bmc->soc.spi[1], 1388 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1389 amc->num_cs, (amc->num_cs * 2)); 1390 1391 if (amc->i2c_init) { 1392 amc->i2c_init(bmc); 1393 } 1394 1395 armv7m_load_kernel(ARM_CPU(first_cpu), 1396 machine->kernel_filename, 1397 AST1030_INTERNAL_FLASH_SIZE); 1398 } 1399 1400 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1401 { 1402 AspeedSoCState *soc = &bmc->soc; 1403 1404 /* U10 24C08 connects to SDA/SCL Groupt 1 by default */ 1405 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1406 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1407 1408 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1409 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1410 } 1411 1412 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1413 void *data) 1414 { 1415 MachineClass *mc = MACHINE_CLASS(oc); 1416 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1417 1418 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1419 amc->soc_name = "ast1030-a1"; 1420 amc->hw_strap1 = 0; 1421 amc->hw_strap2 = 0; 1422 mc->init = aspeed_minibmc_machine_init; 1423 amc->i2c_init = ast1030_evb_i2c_init; 1424 mc->default_ram_size = 0; 1425 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1; 1426 amc->fmc_model = "sst25vf032b"; 1427 amc->spi_model = "sst25vf032b"; 1428 amc->num_cs = 2; 1429 amc->macs_mask = 0; 1430 } 1431 1432 static const TypeInfo aspeed_machine_types[] = { 1433 { 1434 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1435 .parent = TYPE_ASPEED_MACHINE, 1436 .class_init = aspeed_machine_palmetto_class_init, 1437 }, { 1438 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1439 .parent = TYPE_ASPEED_MACHINE, 1440 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1441 }, { 1442 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1443 .parent = TYPE_ASPEED_MACHINE, 1444 .class_init = aspeed_machine_ast2500_evb_class_init, 1445 }, { 1446 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1447 .parent = TYPE_ASPEED_MACHINE, 1448 .class_init = aspeed_machine_romulus_class_init, 1449 }, { 1450 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1451 .parent = TYPE_ASPEED_MACHINE, 1452 .class_init = aspeed_machine_sonorapass_class_init, 1453 }, { 1454 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1455 .parent = TYPE_ASPEED_MACHINE, 1456 .class_init = aspeed_machine_witherspoon_class_init, 1457 }, { 1458 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1459 .parent = TYPE_ASPEED_MACHINE, 1460 .class_init = aspeed_machine_ast2600_evb_class_init, 1461 }, { 1462 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1463 .parent = TYPE_ASPEED_MACHINE, 1464 .class_init = aspeed_machine_tacoma_class_init, 1465 }, { 1466 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1467 .parent = TYPE_ASPEED_MACHINE, 1468 .class_init = aspeed_machine_g220a_class_init, 1469 }, { 1470 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1471 .parent = TYPE_ASPEED_MACHINE, 1472 .class_init = aspeed_machine_fp5280g2_class_init, 1473 }, { 1474 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1475 .parent = TYPE_ASPEED_MACHINE, 1476 .class_init = aspeed_machine_quanta_q71l_class_init, 1477 }, { 1478 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1479 .parent = TYPE_ASPEED_MACHINE, 1480 .class_init = aspeed_machine_rainier_class_init, 1481 }, { 1482 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1483 .parent = TYPE_ASPEED_MACHINE, 1484 .class_init = aspeed_machine_fuji_class_init, 1485 }, { 1486 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1487 .parent = TYPE_ASPEED_MACHINE, 1488 .class_init = aspeed_machine_bletchley_class_init, 1489 }, { 1490 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1491 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1492 .class_init = aspeed_machine_fby35_class_init, 1493 }, { 1494 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1495 .parent = TYPE_ASPEED_MACHINE, 1496 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1497 }, { 1498 .name = TYPE_ASPEED_MACHINE, 1499 .parent = TYPE_MACHINE, 1500 .instance_size = sizeof(AspeedMachineState), 1501 .instance_init = aspeed_machine_instance_init, 1502 .class_size = sizeof(AspeedMachineClass), 1503 .class_init = aspeed_machine_class_init, 1504 .abstract = true, 1505 } 1506 }; 1507 1508 DEFINE_TYPES(aspeed_machine_types) 1509