1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "cpu.h" 15 #include "exec/address-spaces.h" 16 #include "hw/arm/boot.h" 17 #include "hw/arm/aspeed.h" 18 #include "hw/arm/aspeed_soc.h" 19 #include "hw/boards.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/misc/pca9552.h" 22 #include "hw/misc/tmp105.h" 23 #include "hw/qdev-properties.h" 24 #include "qemu/log.h" 25 #include "sysemu/block-backend.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/loader.h" 28 #include "qemu/error-report.h" 29 #include "qemu/units.h" 30 31 static struct arm_boot_info aspeed_board_binfo = { 32 .board_id = -1, /* device-tree-only board */ 33 }; 34 35 struct AspeedBoardState { 36 AspeedSoCState soc; 37 MemoryRegion ram_container; 38 MemoryRegion max_ram; 39 }; 40 41 /* Palmetto hardware value: 0x120CE416 */ 42 #define PALMETTO_BMC_HW_STRAP1 ( \ 43 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 44 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 45 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 46 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 47 SCU_HW_STRAP_VGA_CLASS_CODE | \ 48 SCU_HW_STRAP_LPC_RESET_PIN | \ 49 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 50 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 51 SCU_HW_STRAP_SPI_WIDTH | \ 52 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 53 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 54 55 /* AST2500 evb hardware value: 0xF100C2E6 */ 56 #define AST2500_EVB_HW_STRAP1 (( \ 57 AST2500_HW_STRAP1_DEFAULTS | \ 58 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 59 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 60 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 61 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 62 SCU_HW_STRAP_MAC1_RGMII | \ 63 SCU_HW_STRAP_MAC0_RGMII) & \ 64 ~SCU_HW_STRAP_2ND_BOOT_WDT) 65 66 /* Romulus hardware value: 0xF10AD206 */ 67 #define ROMULUS_BMC_HW_STRAP1 ( \ 68 AST2500_HW_STRAP1_DEFAULTS | \ 69 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 70 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 71 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 72 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 73 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 74 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 75 76 /* Sonorapass hardware value: 0xF100D216 */ 77 #define SONORAPASS_BMC_HW_STRAP1 ( \ 78 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 79 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 80 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 81 SCU_AST2500_HW_STRAP_RESERVED28 | \ 82 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 83 SCU_HW_STRAP_VGA_CLASS_CODE | \ 84 SCU_HW_STRAP_LPC_RESET_PIN | \ 85 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 86 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 87 SCU_HW_STRAP_VGA_BIOS_ROM | \ 88 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 89 SCU_AST2500_HW_STRAP_RESERVED1) 90 91 /* Swift hardware value: 0xF11AD206 */ 92 #define SWIFT_BMC_HW_STRAP1 ( \ 93 AST2500_HW_STRAP1_DEFAULTS | \ 94 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 95 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 96 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 97 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 98 SCU_H_PLL_BYPASS_EN | \ 99 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 100 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 101 102 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 103 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 104 105 /* AST2600 evb hardware value */ 106 #define AST2600_EVB_HW_STRAP1 0x000000C0 107 #define AST2600_EVB_HW_STRAP2 0x00000003 108 109 /* Tacoma hardware value */ 110 #define TACOMA_BMC_HW_STRAP1 0x00000000 111 #define TACOMA_BMC_HW_STRAP2 0x00000040 112 113 /* 114 * The max ram region is for firmwares that scan the address space 115 * with load/store to guess how much RAM the SoC has. 116 */ 117 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 118 { 119 return 0; 120 } 121 122 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 123 unsigned size) 124 { 125 /* Discard writes */ 126 } 127 128 static const MemoryRegionOps max_ram_ops = { 129 .read = max_ram_read, 130 .write = max_ram_write, 131 .endianness = DEVICE_NATIVE_ENDIAN, 132 }; 133 134 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 135 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 136 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 137 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 138 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 139 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 140 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 141 142 static void aspeed_write_smpboot(ARMCPU *cpu, 143 const struct arm_boot_info *info) 144 { 145 static const uint32_t poll_mailbox_ready[] = { 146 /* 147 * r2 = per-cpu go sign value 148 * r1 = AST_SMP_MBOX_FIELD_ENTRY 149 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 150 */ 151 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 152 0xe21000ff, /* ands r0, r0, #255 */ 153 0xe59f201c, /* ldr r2, [pc, #28] */ 154 0xe1822000, /* orr r2, r2, r0 */ 155 156 0xe59f1018, /* ldr r1, [pc, #24] */ 157 0xe59f0018, /* ldr r0, [pc, #24] */ 158 159 0xe320f002, /* wfe */ 160 0xe5904000, /* ldr r4, [r0] */ 161 0xe1520004, /* cmp r2, r4 */ 162 0x1afffffb, /* bne <wfe> */ 163 0xe591f000, /* ldr pc, [r1] */ 164 AST_SMP_MBOX_GOSIGN, 165 AST_SMP_MBOX_FIELD_ENTRY, 166 AST_SMP_MBOX_FIELD_GOSIGN, 167 }; 168 169 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 170 sizeof(poll_mailbox_ready), 171 info->smp_loader_start); 172 } 173 174 static void aspeed_reset_secondary(ARMCPU *cpu, 175 const struct arm_boot_info *info) 176 { 177 AddressSpace *as = arm_boot_address_space(cpu, info); 178 CPUState *cs = CPU(cpu); 179 180 /* info->smp_bootreg_addr */ 181 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 182 MEMTXATTRS_UNSPECIFIED, NULL); 183 cpu_set_pc(cs, info->smp_loader_start); 184 } 185 186 #define FIRMWARE_ADDR 0x0 187 188 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 189 Error **errp) 190 { 191 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 192 uint8_t *storage; 193 int64_t size; 194 195 /* The block backend size should have already been 'validated' by 196 * the creation of the m25p80 object. 197 */ 198 size = blk_getlength(blk); 199 if (size <= 0) { 200 error_setg(errp, "failed to get flash size"); 201 return; 202 } 203 204 if (rom_size > size) { 205 rom_size = size; 206 } 207 208 storage = g_new0(uint8_t, rom_size); 209 if (blk_pread(blk, 0, storage, rom_size) < 0) { 210 error_setg(errp, "failed to read the initial flash content"); 211 return; 212 } 213 214 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 215 g_free(storage); 216 } 217 218 static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 219 Error **errp) 220 { 221 int i ; 222 223 for (i = 0; i < s->num_cs; ++i) { 224 AspeedSMCFlash *fl = &s->flashes[i]; 225 DriveInfo *dinfo = drive_get_next(IF_MTD); 226 qemu_irq cs_line; 227 228 fl->flash = qdev_new(flashtype); 229 if (dinfo) { 230 qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo), 231 errp); 232 } 233 qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal); 234 235 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); 236 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 237 } 238 } 239 240 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 241 { 242 DeviceState *card; 243 244 card = qdev_new(TYPE_SD_CARD); 245 if (dinfo) { 246 qdev_prop_set_drive(card, "drive", blk_by_legacy_dinfo(dinfo), 247 &error_fatal); 248 } 249 qdev_realize_and_unref(card, 250 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 251 &error_fatal); 252 } 253 254 static void aspeed_machine_init(MachineState *machine) 255 { 256 AspeedBoardState *bmc; 257 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 258 AspeedSoCClass *sc; 259 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 260 ram_addr_t max_ram_size; 261 int i; 262 NICInfo *nd = &nd_table[0]; 263 264 bmc = g_new0(AspeedBoardState, 1); 265 266 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 267 4 * GiB); 268 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 269 270 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, 271 (sizeof(bmc->soc)), amc->soc_name, &error_abort, 272 NULL); 273 274 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 275 276 /* 277 * This will error out if isize is not supported by memory controller. 278 */ 279 object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size", 280 &error_fatal); 281 282 for (i = 0; i < sc->macs_num; i++) { 283 if ((amc->macs_mask & (1 << i)) && nd->used) { 284 qemu_check_nic_model(nd, TYPE_FTGMAC100); 285 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 286 nd++; 287 } 288 } 289 290 object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap1, "hw-strap1", 291 &error_abort); 292 object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap2, "hw-strap2", 293 &error_abort); 294 object_property_set_int(OBJECT(&bmc->soc), amc->num_cs, "num-cs", 295 &error_abort); 296 object_property_set_link(OBJECT(&bmc->soc), OBJECT(&bmc->ram_container), 297 "dram", &error_abort); 298 if (machine->kernel_filename) { 299 /* 300 * When booting with a -kernel command line there is no u-boot 301 * that runs to unlock the SCU. In this case set the default to 302 * be unlocked as the kernel expects 303 */ 304 object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY, 305 "hw-prot-key", &error_abort); 306 } 307 object_property_set_bool(OBJECT(&bmc->soc), true, "realized", 308 &error_abort); 309 310 memory_region_add_subregion(get_system_memory(), 311 sc->memmap[ASPEED_SDRAM], 312 &bmc->ram_container); 313 314 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 315 &error_abort); 316 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 317 "max_ram", max_ram_size - ram_size); 318 memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram); 319 320 aspeed_board_init_flashes(&bmc->soc.fmc, amc->fmc_model, &error_abort); 321 aspeed_board_init_flashes(&bmc->soc.spi[0], amc->spi_model, &error_abort); 322 323 /* Install first FMC flash content as a boot rom. */ 324 if (drive0) { 325 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 326 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 327 328 /* 329 * create a ROM region using the default mapping window size of 330 * the flash module. The window size is 64MB for the AST2400 331 * SoC and 128MB for the AST2500 SoC, which is twice as big as 332 * needed by the flash modules of the Aspeed machines. 333 */ 334 if (ASPEED_MACHINE(machine)->mmio_exec) { 335 memory_region_init_alias(boot_rom, OBJECT(bmc), "aspeed.boot_rom", 336 &fl->mmio, 0, fl->size); 337 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 338 boot_rom); 339 } else { 340 memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", 341 fl->size, &error_abort); 342 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 343 boot_rom); 344 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); 345 } 346 } 347 348 if (machine->kernel_filename && sc->num_cpus > 1) { 349 /* With no u-boot we must set up a boot stub for the secondary CPU */ 350 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 351 memory_region_init_ram(smpboot, OBJECT(bmc), "aspeed.smpboot", 352 0x80, &error_abort); 353 memory_region_add_subregion(get_system_memory(), 354 AST_SMP_MAILBOX_BASE, smpboot); 355 356 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 357 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 358 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 359 } 360 361 aspeed_board_binfo.ram_size = ram_size; 362 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM]; 363 aspeed_board_binfo.nb_cpus = sc->num_cpus; 364 365 if (amc->i2c_init) { 366 amc->i2c_init(bmc); 367 } 368 369 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 370 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); 371 } 372 373 if (bmc->soc.emmc.num_slots) { 374 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); 375 } 376 377 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 378 } 379 380 static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) 381 { 382 AspeedSoCState *soc = &bmc->soc; 383 DeviceState *dev; 384 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 385 386 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 387 * enough to provide basic RTC features. Alarms will be missing */ 388 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68); 389 390 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), 0x50, 391 eeprom_buf); 392 393 /* add a TMP423 temperature sensor */ 394 dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), 395 "tmp423", 0x4c); 396 object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort); 397 object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort); 398 object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort); 399 object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); 400 } 401 402 static void ast2500_evb_i2c_init(AspeedBoardState *bmc) 403 { 404 AspeedSoCState *soc = &bmc->soc; 405 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 406 407 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), 0x50, 408 eeprom_buf); 409 410 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 411 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), 412 TYPE_TMP105, 0x4d); 413 414 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 415 * plugged on the I2C bus header */ 416 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 417 } 418 419 static void ast2600_evb_i2c_init(AspeedBoardState *bmc) 420 { 421 /* Start with some devices on our I2C busses */ 422 ast2500_evb_i2c_init(bmc); 423 } 424 425 static void romulus_bmc_i2c_init(AspeedBoardState *bmc) 426 { 427 AspeedSoCState *soc = &bmc->soc; 428 429 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 430 * good enough */ 431 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 432 } 433 434 static void swift_bmc_i2c_init(AspeedBoardState *bmc) 435 { 436 AspeedSoCState *soc = &bmc->soc; 437 438 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", 0x60); 439 440 /* The swift board expects a TMP275 but a TMP105 is compatible */ 441 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x48); 442 /* The swift board expects a pca9551 but a pca9552 is compatible */ 443 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "pca9552", 0x60); 444 445 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ 446 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "ds1338", 0x32); 447 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60); 448 449 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp423", 0x4c); 450 /* The swift board expects a pca9539 but a pca9552 is compatible */ 451 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "pca9552", 0x74); 452 453 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "tmp423", 0x4c); 454 /* The swift board expects a pca9539 but a pca9552 is compatible */ 455 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "pca9552", 456 0x74); 457 458 /* The swift board expects a TMP275 but a TMP105 is compatible */ 459 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x48); 460 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x4a); 461 } 462 463 static void sonorapass_bmc_i2c_init(AspeedBoardState *bmc) 464 { 465 AspeedSoCState *soc = &bmc->soc; 466 467 /* bus 2 : */ 468 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), "tmp105", 0x48); 469 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), "tmp105", 0x49); 470 /* bus 2 : pca9546 @ 0x73 */ 471 472 /* bus 3 : pca9548 @ 0x70 */ 473 474 /* bus 4 : */ 475 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 476 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), 0x54, 477 eeprom4_54); 478 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 479 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "pca9552", 0x76); 480 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 481 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "pca9552", 0x77); 482 483 /* bus 6 : */ 484 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 6), "tmp105", 0x48); 485 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 6), "tmp105", 0x49); 486 /* bus 6 : pca9546 @ 0x73 */ 487 488 /* bus 8 : */ 489 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 490 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), 0x56, 491 eeprom8_56); 492 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60); 493 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x61); 494 /* bus 8 : adc128d818 @ 0x1d */ 495 /* bus 8 : adc128d818 @ 0x1f */ 496 497 /* 498 * bus 13 : pca9548 @ 0x71 499 * - channel 3: 500 * - tmm421 @ 0x4c 501 * - tmp421 @ 0x4e 502 * - tmp421 @ 0x4f 503 */ 504 505 } 506 507 static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) 508 { 509 AspeedSoCState *soc = &bmc->soc; 510 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 511 512 /* Bus 3: TODO bmp280@77 */ 513 /* Bus 3: TODO max31785@52 */ 514 /* Bus 3: TODO dps310@76 */ 515 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA9552, 516 0x60); 517 518 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c); 519 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c); 520 521 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 522 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), TYPE_TMP105, 523 0x4a); 524 525 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 526 * good enough */ 527 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 528 529 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51, 530 eeprom_buf); 531 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA9552, 532 0x60); 533 /* Bus 11: TODO ucd90160@64 */ 534 } 535 536 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 537 { 538 return ASPEED_MACHINE(obj)->mmio_exec; 539 } 540 541 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 542 { 543 ASPEED_MACHINE(obj)->mmio_exec = value; 544 } 545 546 static void aspeed_machine_instance_init(Object *obj) 547 { 548 ASPEED_MACHINE(obj)->mmio_exec = false; 549 } 550 551 static void aspeed_machine_class_props_init(ObjectClass *oc) 552 { 553 object_class_property_add_bool(oc, "execute-in-place", 554 aspeed_get_mmio_exec, 555 aspeed_set_mmio_exec); 556 object_class_property_set_description(oc, "execute-in-place", 557 "boot directly from CE0 flash device"); 558 } 559 560 static int aspeed_soc_num_cpus(const char *soc_name) 561 { 562 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 563 return sc->num_cpus; 564 } 565 566 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 567 { 568 MachineClass *mc = MACHINE_CLASS(oc); 569 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 570 571 mc->init = aspeed_machine_init; 572 mc->no_floppy = 1; 573 mc->no_cdrom = 1; 574 mc->no_parallel = 1; 575 mc->default_ram_id = "ram"; 576 amc->macs_mask = ASPEED_MAC0_ON; 577 578 aspeed_machine_class_props_init(oc); 579 } 580 581 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 582 { 583 MachineClass *mc = MACHINE_CLASS(oc); 584 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 585 586 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 587 amc->soc_name = "ast2400-a1"; 588 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 589 amc->fmc_model = "n25q256a"; 590 amc->spi_model = "mx25l25635e"; 591 amc->num_cs = 1; 592 amc->i2c_init = palmetto_bmc_i2c_init; 593 mc->default_ram_size = 256 * MiB; 594 mc->default_cpus = mc->min_cpus = mc->max_cpus = 595 aspeed_soc_num_cpus(amc->soc_name); 596 }; 597 598 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 599 { 600 MachineClass *mc = MACHINE_CLASS(oc); 601 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 602 603 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 604 amc->soc_name = "ast2500-a1"; 605 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 606 amc->fmc_model = "w25q256"; 607 amc->spi_model = "mx25l25635e"; 608 amc->num_cs = 1; 609 amc->i2c_init = ast2500_evb_i2c_init; 610 mc->default_ram_size = 512 * MiB; 611 mc->default_cpus = mc->min_cpus = mc->max_cpus = 612 aspeed_soc_num_cpus(amc->soc_name); 613 }; 614 615 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 616 { 617 MachineClass *mc = MACHINE_CLASS(oc); 618 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 619 620 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 621 amc->soc_name = "ast2500-a1"; 622 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 623 amc->fmc_model = "n25q256a"; 624 amc->spi_model = "mx66l1g45g"; 625 amc->num_cs = 2; 626 amc->i2c_init = romulus_bmc_i2c_init; 627 mc->default_ram_size = 512 * MiB; 628 mc->default_cpus = mc->min_cpus = mc->max_cpus = 629 aspeed_soc_num_cpus(amc->soc_name); 630 }; 631 632 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 633 { 634 MachineClass *mc = MACHINE_CLASS(oc); 635 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 636 637 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 638 amc->soc_name = "ast2500-a1"; 639 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 640 amc->fmc_model = "mx66l1g45g"; 641 amc->spi_model = "mx66l1g45g"; 642 amc->num_cs = 2; 643 amc->i2c_init = sonorapass_bmc_i2c_init; 644 mc->default_ram_size = 512 * MiB; 645 mc->default_cpus = mc->min_cpus = mc->max_cpus = 646 aspeed_soc_num_cpus(amc->soc_name); 647 }; 648 649 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) 650 { 651 MachineClass *mc = MACHINE_CLASS(oc); 652 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 653 654 mc->desc = "OpenPOWER Swift BMC (ARM1176)"; 655 amc->soc_name = "ast2500-a1"; 656 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1; 657 amc->fmc_model = "mx66l1g45g"; 658 amc->spi_model = "mx66l1g45g"; 659 amc->num_cs = 2; 660 amc->i2c_init = swift_bmc_i2c_init; 661 mc->default_ram_size = 512 * MiB; 662 mc->default_cpus = mc->min_cpus = mc->max_cpus = 663 aspeed_soc_num_cpus(amc->soc_name); 664 }; 665 666 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 667 { 668 MachineClass *mc = MACHINE_CLASS(oc); 669 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 670 671 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 672 amc->soc_name = "ast2500-a1"; 673 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 674 amc->fmc_model = "mx25l25635e"; 675 amc->spi_model = "mx66l1g45g"; 676 amc->num_cs = 2; 677 amc->i2c_init = witherspoon_bmc_i2c_init; 678 mc->default_ram_size = 512 * MiB; 679 mc->default_cpus = mc->min_cpus = mc->max_cpus = 680 aspeed_soc_num_cpus(amc->soc_name); 681 }; 682 683 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 684 { 685 MachineClass *mc = MACHINE_CLASS(oc); 686 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 687 688 mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; 689 amc->soc_name = "ast2600-a1"; 690 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 691 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 692 amc->fmc_model = "w25q512jv"; 693 amc->spi_model = "mx66u51235f"; 694 amc->num_cs = 1; 695 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON; 696 amc->i2c_init = ast2600_evb_i2c_init; 697 mc->default_ram_size = 1 * GiB; 698 mc->default_cpus = mc->min_cpus = mc->max_cpus = 699 aspeed_soc_num_cpus(amc->soc_name); 700 }; 701 702 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 703 { 704 MachineClass *mc = MACHINE_CLASS(oc); 705 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 706 707 mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)"; 708 amc->soc_name = "ast2600-a1"; 709 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 710 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 711 amc->fmc_model = "mx66l1g45g"; 712 amc->spi_model = "mx66l1g45g"; 713 amc->num_cs = 2; 714 amc->macs_mask = ASPEED_MAC2_ON; 715 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 716 mc->default_ram_size = 1 * GiB; 717 mc->default_cpus = mc->min_cpus = mc->max_cpus = 718 aspeed_soc_num_cpus(amc->soc_name); 719 }; 720 721 static const TypeInfo aspeed_machine_types[] = { 722 { 723 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 724 .parent = TYPE_ASPEED_MACHINE, 725 .class_init = aspeed_machine_palmetto_class_init, 726 }, { 727 .name = MACHINE_TYPE_NAME("ast2500-evb"), 728 .parent = TYPE_ASPEED_MACHINE, 729 .class_init = aspeed_machine_ast2500_evb_class_init, 730 }, { 731 .name = MACHINE_TYPE_NAME("romulus-bmc"), 732 .parent = TYPE_ASPEED_MACHINE, 733 .class_init = aspeed_machine_romulus_class_init, 734 }, { 735 .name = MACHINE_TYPE_NAME("swift-bmc"), 736 .parent = TYPE_ASPEED_MACHINE, 737 .class_init = aspeed_machine_swift_class_init, 738 }, { 739 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 740 .parent = TYPE_ASPEED_MACHINE, 741 .class_init = aspeed_machine_sonorapass_class_init, 742 }, { 743 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 744 .parent = TYPE_ASPEED_MACHINE, 745 .class_init = aspeed_machine_witherspoon_class_init, 746 }, { 747 .name = MACHINE_TYPE_NAME("ast2600-evb"), 748 .parent = TYPE_ASPEED_MACHINE, 749 .class_init = aspeed_machine_ast2600_evb_class_init, 750 }, { 751 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 752 .parent = TYPE_ASPEED_MACHINE, 753 .class_init = aspeed_machine_tacoma_class_init, 754 }, { 755 .name = TYPE_ASPEED_MACHINE, 756 .parent = TYPE_MACHINE, 757 .instance_size = sizeof(AspeedMachine), 758 .instance_init = aspeed_machine_instance_init, 759 .class_size = sizeof(AspeedMachineClass), 760 .class_init = aspeed_machine_class_init, 761 .abstract = true, 762 } 763 }; 764 765 DEFINE_TYPES(aspeed_machine_types) 766