1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/block/flash.h" 19 #include "hw/i2c/i2c_mux_pca954x.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/gpio/pca9552.h" 22 #include "hw/gpio/pca9554.h" 23 #include "hw/nvram/eeprom_at24c.h" 24 #include "hw/sensor/tmp105.h" 25 #include "hw/misc/led.h" 26 #include "hw/qdev-properties.h" 27 #include "system/block-backend.h" 28 #include "system/reset.h" 29 #include "hw/loader.h" 30 #include "qemu/error-report.h" 31 #include "qemu/datadir.h" 32 #include "qemu/units.h" 33 #include "hw/qdev-clock.h" 34 #include "system/system.h" 35 36 static struct arm_boot_info aspeed_board_binfo = { 37 .board_id = -1, /* device-tree-only board */ 38 }; 39 40 struct AspeedMachineState { 41 /* Private */ 42 MachineState parent_obj; 43 /* Public */ 44 45 AspeedSoCState *soc; 46 MemoryRegion boot_rom; 47 bool mmio_exec; 48 uint32_t uart_chosen; 49 char *fmc_model; 50 char *spi_model; 51 uint32_t hw_strap1; 52 }; 53 54 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 55 #if HOST_LONG_BITS == 32 56 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) 57 #else 58 #define ASPEED_RAM_SIZE(sz) (sz) 59 #endif 60 61 /* Palmetto hardware value: 0x120CE416 */ 62 #define PALMETTO_BMC_HW_STRAP1 ( \ 63 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 64 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 65 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 66 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 67 SCU_HW_STRAP_VGA_CLASS_CODE | \ 68 SCU_HW_STRAP_LPC_RESET_PIN | \ 69 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 70 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 71 SCU_HW_STRAP_SPI_WIDTH | \ 72 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 73 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 74 75 /* TODO: Find the actual hardware value */ 76 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 77 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 78 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 79 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 80 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 81 SCU_HW_STRAP_VGA_CLASS_CODE | \ 82 SCU_HW_STRAP_LPC_RESET_PIN | \ 83 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 84 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 85 SCU_HW_STRAP_SPI_WIDTH | \ 86 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 87 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 88 89 /* TODO: Find the actual hardware value */ 90 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 91 AST2500_HW_STRAP1_DEFAULTS | \ 92 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 93 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 94 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 95 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 96 SCU_HW_STRAP_SPI_WIDTH | \ 97 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 98 99 /* AST2500 evb hardware value: 0xF100C2E6 */ 100 #define AST2500_EVB_HW_STRAP1 (( \ 101 AST2500_HW_STRAP1_DEFAULTS | \ 102 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 103 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 104 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 105 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 106 SCU_HW_STRAP_MAC1_RGMII | \ 107 SCU_HW_STRAP_MAC0_RGMII) & \ 108 ~SCU_HW_STRAP_2ND_BOOT_WDT) 109 110 /* Romulus hardware value: 0xF10AD206 */ 111 #define ROMULUS_BMC_HW_STRAP1 ( \ 112 AST2500_HW_STRAP1_DEFAULTS | \ 113 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 114 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 115 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 116 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 117 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 119 120 /* Sonorapass hardware value: 0xF100D216 */ 121 #define SONORAPASS_BMC_HW_STRAP1 ( \ 122 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 123 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 124 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 125 SCU_AST2500_HW_STRAP_RESERVED28 | \ 126 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 127 SCU_HW_STRAP_VGA_CLASS_CODE | \ 128 SCU_HW_STRAP_LPC_RESET_PIN | \ 129 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 130 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 131 SCU_HW_STRAP_VGA_BIOS_ROM | \ 132 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 133 SCU_AST2500_HW_STRAP_RESERVED1) 134 135 #define G220A_BMC_HW_STRAP1 ( \ 136 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 137 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 138 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 139 SCU_AST2500_HW_STRAP_RESERVED28 | \ 140 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 141 SCU_HW_STRAP_2ND_BOOT_WDT | \ 142 SCU_HW_STRAP_VGA_CLASS_CODE | \ 143 SCU_HW_STRAP_LPC_RESET_PIN | \ 144 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 145 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 146 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 147 SCU_AST2500_HW_STRAP_RESERVED1) 148 149 /* FP5280G2 hardware value: 0XF100D286 */ 150 #define FP5280G2_BMC_HW_STRAP1 ( \ 151 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 152 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 153 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 154 SCU_AST2500_HW_STRAP_RESERVED28 | \ 155 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 156 SCU_HW_STRAP_VGA_CLASS_CODE | \ 157 SCU_HW_STRAP_LPC_RESET_PIN | \ 158 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 159 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 160 SCU_HW_STRAP_MAC1_RGMII | \ 161 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 162 SCU_AST2500_HW_STRAP_RESERVED1) 163 164 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 165 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 166 167 /* Quanta-Q71l hardware value */ 168 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 169 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 170 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 171 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 172 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 173 SCU_HW_STRAP_VGA_CLASS_CODE | \ 174 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 175 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 176 SCU_HW_STRAP_SPI_WIDTH | \ 177 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 178 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 179 180 /* AST2600 evb hardware value */ 181 #define AST2600_EVB_HW_STRAP1 0x000000C0 182 #define AST2600_EVB_HW_STRAP2 0x00000003 183 184 #ifdef TARGET_AARCH64 185 /* AST2700 evb hardware value */ 186 /* SCU HW Strap1 */ 187 #define AST2700_EVB_HW_STRAP1 0x00000800 188 /* SCUIO HW Strap1 */ 189 #define AST2700_EVB_HW_STRAP2 0x00000700 190 #endif 191 192 /* Rainier hardware value: (QEMU prototype) */ 193 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) 194 #define RAINIER_BMC_HW_STRAP2 0x80000848 195 196 /* Fuji hardware value */ 197 #define FUJI_BMC_HW_STRAP1 0x00000000 198 #define FUJI_BMC_HW_STRAP2 0x00000000 199 200 /* Bletchley hardware value */ 201 #define BLETCHLEY_BMC_HW_STRAP1 0x00002000 202 #define BLETCHLEY_BMC_HW_STRAP2 0x00000801 203 204 /* Qualcomm DC-SCM hardware value */ 205 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 206 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 207 208 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 209 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 210 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 211 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 212 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 213 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 214 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 215 216 static void aspeed_write_smpboot(ARMCPU *cpu, 217 const struct arm_boot_info *info) 218 { 219 AddressSpace *as = arm_boot_address_space(cpu, info); 220 static const ARMInsnFixup poll_mailbox_ready[] = { 221 /* 222 * r2 = per-cpu go sign value 223 * r1 = AST_SMP_MBOX_FIELD_ENTRY 224 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 225 */ 226 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 227 { 0xe21000ff }, /* ands r0, r0, #255 */ 228 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 229 { 0xe1822000 }, /* orr r2, r2, r0 */ 230 231 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 232 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 233 234 { 0xe320f002 }, /* wfe */ 235 { 0xe5904000 }, /* ldr r4, [r0] */ 236 { 0xe1520004 }, /* cmp r2, r4 */ 237 { 0x1afffffb }, /* bne <wfe> */ 238 { 0xe591f000 }, /* ldr pc, [r1] */ 239 { AST_SMP_MBOX_GOSIGN }, 240 { AST_SMP_MBOX_FIELD_ENTRY }, 241 { AST_SMP_MBOX_FIELD_GOSIGN }, 242 { 0, FIXUP_TERMINATOR } 243 }; 244 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 245 246 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 247 poll_mailbox_ready, fixupcontext); 248 } 249 250 static void aspeed_reset_secondary(ARMCPU *cpu, 251 const struct arm_boot_info *info) 252 { 253 AddressSpace *as = arm_boot_address_space(cpu, info); 254 CPUState *cs = CPU(cpu); 255 256 /* info->smp_bootreg_addr */ 257 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 258 MEMTXATTRS_UNSPECIFIED, NULL); 259 cpu_set_pc(cs, info->smp_loader_start); 260 } 261 262 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 263 Error **errp) 264 { 265 g_autofree void *storage = NULL; 266 int64_t size; 267 268 /* 269 * The block backend size should have already been 'validated' by 270 * the creation of the m25p80 object. 271 */ 272 size = blk_getlength(blk); 273 if (size <= 0) { 274 error_setg(errp, "failed to get flash size"); 275 return; 276 } 277 278 if (rom_size > size) { 279 rom_size = size; 280 } 281 282 storage = g_malloc0(rom_size); 283 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 284 error_setg(errp, "failed to read the initial flash content"); 285 return; 286 } 287 288 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 289 } 290 291 /* 292 * Create a ROM and copy the flash contents at the expected address 293 * (0x0). Boots faster than execute-in-place. 294 */ 295 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 296 uint64_t rom_size) 297 { 298 AspeedSoCState *soc = bmc->soc; 299 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); 300 301 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 302 &error_abort); 303 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 304 &bmc->boot_rom, 1); 305 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], 306 rom_size, &error_abort); 307 } 308 309 #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" 310 311 /* 312 * This function locates the vbootrom image file specified via the command line 313 * using the -bios option. It loads the specified image into the vbootrom 314 * memory region and handles errors if the file cannot be found or loaded. 315 */ 316 static void aspeed_load_vbootrom(AspeedMachineState *bmc, const char *bios_name, 317 Error **errp) 318 { 319 g_autofree char *filename = NULL; 320 AspeedSoCState *soc = bmc->soc; 321 int ret; 322 323 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 324 if (!filename) { 325 error_setg(errp, "Could not find vbootrom image '%s'", bios_name); 326 return; 327 } 328 329 ret = load_image_mr(filename, &soc->vbootrom); 330 if (ret < 0) { 331 error_setg(errp, "Failed to load vbootrom image '%s'", bios_name); 332 return; 333 } 334 } 335 336 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 337 unsigned int count, int unit0) 338 { 339 int i; 340 341 if (!flashtype) { 342 return; 343 } 344 345 for (i = 0; i < count; ++i) { 346 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 347 DeviceState *dev; 348 349 dev = qdev_new(flashtype); 350 if (dinfo) { 351 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 352 } 353 qdev_prop_set_uint8(dev, "cs", i); 354 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 355 } 356 } 357 358 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc, 359 bool boot_emmc) 360 { 361 DeviceState *card; 362 363 if (!dinfo) { 364 return; 365 } 366 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); 367 368 /* 369 * Force the boot properties of the eMMC device only when the 370 * machine is strapped to boot from eMMC. Without these 371 * settings, the machine would not boot. 372 * 373 * This also allows the machine to use an eMMC device without 374 * boot areas when booting from the flash device (or -kernel) 375 * Ideally, the device and its properties should be defined on 376 * the command line. 377 */ 378 if (emmc && boot_emmc) { 379 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB); 380 qdev_prop_set_uint8(card, "boot-config", 0x1 << 3); 381 } 382 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 383 &error_fatal); 384 qdev_realize_and_unref(card, 385 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 386 &error_fatal); 387 } 388 389 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 390 { 391 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 392 AspeedSoCState *s = bmc->soc; 393 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 394 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 395 396 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 397 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; uart++) { 398 if (uart == uart_chosen) { 399 continue; 400 } 401 aspeed_soc_uart_set_chr(s, uart, serial_hd(i++)); 402 } 403 } 404 405 static void aspeed_machine_init(MachineState *machine) 406 { 407 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 408 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 409 AspeedSoCClass *sc; 410 int i; 411 const char *bios_name = NULL; 412 DriveInfo *emmc0 = NULL; 413 bool boot_emmc; 414 415 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 416 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 417 object_unref(OBJECT(bmc->soc)); 418 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 419 420 /* 421 * This will error out if the RAM size is not supported by the 422 * memory controller of the SoC. 423 */ 424 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 425 &error_fatal); 426 427 for (i = 0; i < sc->macs_num; i++) { 428 if ((amc->macs_mask & (1 << i)) && 429 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), 430 true, NULL)) { 431 break; /* No configs left; stop asking */ 432 } 433 } 434 435 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1, 436 &error_abort); 437 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 438 &error_abort); 439 object_property_set_link(OBJECT(bmc->soc), "memory", 440 OBJECT(get_system_memory()), &error_abort); 441 object_property_set_link(OBJECT(bmc->soc), "dram", 442 OBJECT(machine->ram), &error_abort); 443 if (amc->sdhci_wp_inverted) { 444 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 445 object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), 446 "wp-inverted", true, &error_abort); 447 } 448 } 449 if (machine->kernel_filename) { 450 /* 451 * When booting with a -kernel command line there is no u-boot 452 * that runs to unlock the SCU. In this case set the default to 453 * be unlocked as the kernel expects 454 */ 455 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 456 ASPEED_SCU_PROT_KEY, &error_abort); 457 } 458 connect_serial_hds_to_uarts(bmc); 459 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 460 461 if (defaults_enabled()) { 462 aspeed_board_init_flashes(&bmc->soc->fmc, 463 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 464 amc->num_cs, 0); 465 aspeed_board_init_flashes(&bmc->soc->spi[0], 466 bmc->spi_model ? bmc->spi_model : amc->spi_model, 467 1, amc->num_cs); 468 } 469 470 if (machine->kernel_filename && sc->num_cpus > 1) { 471 /* With no u-boot we must set up a boot stub for the secondary CPU */ 472 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 473 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 474 0x80, &error_abort); 475 memory_region_add_subregion(get_system_memory(), 476 AST_SMP_MAILBOX_BASE, smpboot); 477 478 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 479 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 480 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 481 } 482 483 aspeed_board_binfo.ram_size = machine->ram_size; 484 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 485 486 if (amc->i2c_init) { 487 amc->i2c_init(bmc); 488 } 489 490 for (i = 0; i < bmc->soc->sdhci.num_slots && defaults_enabled(); i++) { 491 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 492 drive_get(IF_SD, 0, i), false, false); 493 } 494 495 boot_emmc = sc->boot_from_emmc(bmc->soc); 496 497 if (bmc->soc->emmc.num_slots && defaults_enabled()) { 498 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); 499 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc); 500 } 501 502 if (!bmc->mmio_exec) { 503 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 504 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 505 506 if (fmc0 && !boot_emmc) { 507 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 508 aspeed_install_boot_rom(bmc, fmc0, rom_size); 509 } else if (emmc0) { 510 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB); 511 } 512 } 513 514 if (amc->vbootrom) { 515 bios_name = machine->firmware ?: VBOOTROM_FILE_NAME; 516 aspeed_load_vbootrom(bmc, bios_name, &error_abort); 517 } 518 519 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 520 } 521 522 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 523 { 524 AspeedSoCState *soc = bmc->soc; 525 DeviceState *dev; 526 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 527 528 /* 529 * The palmetto platform expects a ds3231 RTC but a ds1338 is 530 * enough to provide basic RTC features. Alarms will be missing 531 */ 532 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 533 534 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 535 eeprom_buf); 536 537 /* add a TMP423 temperature sensor */ 538 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 539 "tmp423", 0x4c)); 540 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 541 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 542 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 543 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 544 } 545 546 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 547 { 548 AspeedSoCState *soc = bmc->soc; 549 550 /* 551 * The quanta-q71l platform expects tmp75s which are compatible with 552 * tmp105s. 553 */ 554 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 555 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 556 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 557 558 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 559 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 560 /* TODO: Add Memory Riser i2c mux and eeproms. */ 561 562 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 563 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 564 565 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 566 567 /* i2c-7 */ 568 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 569 /* - i2c@0: pmbus@59 */ 570 /* - i2c@1: pmbus@58 */ 571 /* - i2c@2: pmbus@58 */ 572 /* - i2c@3: pmbus@59 */ 573 574 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 575 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 576 } 577 578 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 579 { 580 AspeedSoCState *soc = bmc->soc; 581 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 582 583 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 584 eeprom_buf); 585 586 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 587 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 588 TYPE_TMP105, 0x4d); 589 } 590 591 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 592 { 593 AspeedSoCState *soc = bmc->soc; 594 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 595 596 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 597 eeprom_buf); 598 599 /* LM75 is compatible with TMP105 driver */ 600 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 601 TYPE_TMP105, 0x4d); 602 } 603 604 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 605 { 606 AspeedSoCState *soc = bmc->soc; 607 608 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 609 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 610 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 611 /* TMP421 */ 612 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 613 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 614 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 615 616 } 617 618 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 619 { 620 AspeedSoCState *soc = bmc->soc; 621 622 /* 623 * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 624 * good enough 625 */ 626 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 627 } 628 629 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 630 { 631 AspeedSoCState *soc = bmc->soc; 632 633 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 634 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 635 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 636 /* TMP421 */ 637 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 638 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 639 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 640 } 641 642 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 643 { 644 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 645 TYPE_PCA9552, addr); 646 } 647 648 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 649 { 650 AspeedSoCState *soc = bmc->soc; 651 652 /* bus 2 : */ 653 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 654 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 655 /* bus 2 : pca9546 @ 0x73 */ 656 657 /* bus 3 : pca9548 @ 0x70 */ 658 659 /* bus 4 : */ 660 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 661 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 662 eeprom4_54); 663 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 664 create_pca9552(soc, 4, 0x76); 665 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 666 create_pca9552(soc, 4, 0x77); 667 668 /* bus 6 : */ 669 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 670 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 671 /* bus 6 : pca9546 @ 0x73 */ 672 673 /* bus 8 : */ 674 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 675 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 676 eeprom8_56); 677 create_pca9552(soc, 8, 0x60); 678 create_pca9552(soc, 8, 0x61); 679 /* bus 8 : adc128d818 @ 0x1d */ 680 /* bus 8 : adc128d818 @ 0x1f */ 681 682 /* 683 * bus 13 : pca9548 @ 0x71 684 * - channel 3: 685 * - tmm421 @ 0x4c 686 * - tmp421 @ 0x4e 687 * - tmp421 @ 0x4f 688 */ 689 690 } 691 692 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 693 { 694 static const struct { 695 unsigned gpio_id; 696 LEDColor color; 697 const char *description; 698 bool gpio_polarity; 699 } pca1_leds[] = { 700 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 701 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 702 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 703 }; 704 AspeedSoCState *soc = bmc->soc; 705 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 706 DeviceState *dev; 707 LEDState *led; 708 709 /* Bus 3: TODO bmp280@77 */ 710 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 711 qdev_prop_set_string(dev, "description", "pca1"); 712 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 713 aspeed_i2c_get_bus(&soc->i2c, 3), 714 &error_fatal); 715 716 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 717 led = led_create_simple(OBJECT(bmc), 718 pca1_leds[i].gpio_polarity, 719 pca1_leds[i].color, 720 pca1_leds[i].description); 721 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 722 qdev_get_gpio_in(DEVICE(led), 0)); 723 } 724 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 725 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 726 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 727 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 728 729 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 730 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 731 0x4a); 732 733 /* 734 * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 735 * good enough 736 */ 737 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 738 739 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 740 eeprom_buf); 741 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 742 qdev_prop_set_string(dev, "description", "pca0"); 743 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 744 aspeed_i2c_get_bus(&soc->i2c, 11), 745 &error_fatal); 746 /* Bus 11: TODO ucd90160@64 */ 747 } 748 749 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 750 { 751 AspeedSoCState *soc = bmc->soc; 752 DeviceState *dev; 753 754 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 755 "emc1413", 0x4c)); 756 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 757 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 758 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 759 760 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 761 "emc1413", 0x4c)); 762 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 763 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 764 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 765 766 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 767 "emc1413", 0x4c)); 768 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 769 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 770 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 771 772 static uint8_t eeprom_buf[2 * 1024] = { 773 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 774 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 775 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 776 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 777 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 778 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 779 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 780 }; 781 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 782 eeprom_buf); 783 } 784 785 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 786 { 787 AspeedSoCState *soc = bmc->soc; 788 I2CSlave *i2c_mux; 789 790 /* The at24c256 */ 791 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 792 793 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 794 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 795 0x48); 796 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 797 0x49); 798 799 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 800 "pca9546", 0x70); 801 /* It expects a TMP112 but a TMP105 is compatible */ 802 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 803 0x4a); 804 805 /* It expects a ds3232 but a ds1338 is good enough */ 806 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 807 808 /* It expects a pca9555 but a pca9552 is compatible */ 809 create_pca9552(soc, 8, 0x30); 810 } 811 812 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 813 { 814 AspeedSoCState *soc = bmc->soc; 815 I2CSlave *i2c_mux; 816 817 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 818 819 create_pca9552(soc, 3, 0x61); 820 821 /* The rainier expects a TMP275 but a TMP105 is compatible */ 822 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 823 0x48); 824 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 825 0x49); 826 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 827 0x4a); 828 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 829 "pca9546", 0x70); 830 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 831 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 832 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 833 create_pca9552(soc, 4, 0x60); 834 835 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 836 0x48); 837 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 838 0x49); 839 create_pca9552(soc, 5, 0x60); 840 create_pca9552(soc, 5, 0x61); 841 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 842 "pca9546", 0x70); 843 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 844 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 845 846 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 847 0x48); 848 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 849 0x4a); 850 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 851 0x4b); 852 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 853 "pca9546", 0x70); 854 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 855 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 856 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 857 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 858 859 create_pca9552(soc, 7, 0x30); 860 create_pca9552(soc, 7, 0x31); 861 create_pca9552(soc, 7, 0x32); 862 create_pca9552(soc, 7, 0x33); 863 create_pca9552(soc, 7, 0x60); 864 create_pca9552(soc, 7, 0x61); 865 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 866 /* Bus 7: TODO si7021-a20@20 */ 867 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 868 0x48); 869 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 870 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 871 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 872 873 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 874 0x48); 875 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 876 0x4a); 877 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 878 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 879 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 880 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 881 create_pca9552(soc, 8, 0x60); 882 create_pca9552(soc, 8, 0x61); 883 /* Bus 8: ucd90320@11 */ 884 /* Bus 8: ucd90320@b */ 885 /* Bus 8: ucd90320@c */ 886 887 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 888 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 889 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 890 891 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 892 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 893 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 894 895 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 896 0x48); 897 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 898 0x49); 899 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 900 "pca9546", 0x70); 901 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 902 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 903 create_pca9552(soc, 11, 0x60); 904 905 906 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 907 create_pca9552(soc, 13, 0x60); 908 909 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 910 create_pca9552(soc, 14, 0x60); 911 912 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 913 create_pca9552(soc, 15, 0x60); 914 } 915 916 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 917 I2CBus **channels) 918 { 919 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 920 for (int i = 0; i < 8; i++) { 921 channels[i] = pca954x_i2c_get_bus(mux, i); 922 } 923 } 924 925 #define TYPE_LM75 TYPE_TMP105 926 #define TYPE_TMP75 TYPE_TMP105 927 #define TYPE_TMP422 "tmp422" 928 929 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 930 { 931 AspeedSoCState *soc = bmc->soc; 932 I2CBus *i2c[144] = {}; 933 934 for (int i = 0; i < 16; i++) { 935 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 936 } 937 I2CBus *i2c180 = i2c[2]; 938 I2CBus *i2c480 = i2c[8]; 939 I2CBus *i2c600 = i2c[11]; 940 941 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 942 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 943 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 944 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 945 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 946 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 947 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 948 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 949 for (int i = 0; i < 8; i++) { 950 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 951 } 952 953 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 954 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 955 956 /* 957 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 958 * 24c02 size is 2Kbits or 256 bytes 959 */ 960 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 961 at24c_eeprom_init(i2c[20], 0x50, 256); 962 at24c_eeprom_init(i2c[22], 0x52, 256); 963 964 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 965 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 966 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 967 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 968 969 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 970 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 971 972 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 973 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 974 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 975 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 976 977 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 978 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 979 980 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 981 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 982 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 983 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 984 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 985 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 986 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 987 988 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 989 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 990 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 991 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 992 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 993 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 994 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 995 at24c_eeprom_init(i2c[28], 0x50, 256); 996 997 for (int i = 0; i < 8; i++) { 998 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 999 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 1000 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 1001 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 1002 } 1003 } 1004 1005 #define TYPE_TMP421 "tmp421" 1006 #define TYPE_DS1338 "ds1338" 1007 1008 /* Catalina hardware value */ 1009 #define CATALINA_BMC_HW_STRAP1 0x00002002 1010 #define CATALINA_BMC_HW_STRAP2 0x00000800 1011 1012 #define CATALINA_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1013 1014 static void catalina_bmc_i2c_init(AspeedMachineState *bmc) 1015 { 1016 /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ 1017 1018 AspeedSoCState *soc = bmc->soc; 1019 I2CBus *i2c[16] = {}; 1020 I2CSlave *i2c_mux; 1021 1022 /* busses 0-15 are all used. */ 1023 for (int i = 0; i < ARRAY_SIZE(i2c); i++) { 1024 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1025 } 1026 1027 /* &i2c0 */ 1028 /* i2c-mux@71 (PCA9546) on i2c0 */ 1029 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x71); 1030 1031 /* i2c-mux@72 (PCA9546) on i2c0 */ 1032 i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x72); 1033 1034 /* i2c0mux1ch1 */ 1035 /* io_expander7 - pca9535@20 */ 1036 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), 1037 TYPE_PCA9552, 0x20); 1038 /* eeprom@50 */ 1039 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB); 1040 1041 /* i2c-mux@73 (PCA9546) on i2c0 */ 1042 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x73); 1043 1044 /* i2c-mux@75 (PCA9546) on i2c0 */ 1045 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x75); 1046 1047 /* i2c-mux@76 (PCA9546) on i2c0 */ 1048 i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x76); 1049 1050 /* i2c0mux4ch1 */ 1051 /* io_expander8 - pca9535@21 */ 1052 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), 1053 TYPE_PCA9552, 0x21); 1054 /* eeprom@50 */ 1055 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB); 1056 1057 /* i2c-mux@77 (PCA9546) on i2c0 */ 1058 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x77); 1059 1060 1061 /* &i2c1 */ 1062 /* i2c-mux@70 (PCA9548) on i2c1 */ 1063 i2c_mux = i2c_slave_create_simple(i2c[1], TYPE_PCA9548, 0x70); 1064 /* i2c1mux0ch0 */ 1065 /* ina238@41 - no model */ 1066 /* ina238@42 - no model */ 1067 /* ina238@44 - no model */ 1068 /* i2c1mux0ch1 */ 1069 /* ina238@41 - no model */ 1070 /* ina238@43 - no model */ 1071 /* i2c1mux0ch4 */ 1072 /* ltc4287@42 - no model */ 1073 /* ltc4287@43 - no model */ 1074 1075 /* i2c1mux0ch5 */ 1076 /* eeprom@54 */ 1077 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 5), 0x54, 8 * KiB); 1078 /* tpm75@4f */ 1079 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), TYPE_TMP75, 0x4f); 1080 1081 /* i2c1mux0ch6 */ 1082 /* io_expander5 - pca9554@27 */ 1083 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), 1084 TYPE_PCA9554, 0x27); 1085 /* io_expander6 - pca9555@25 */ 1086 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), 1087 TYPE_PCA9552, 0x25); 1088 /* eeprom@51 */ 1089 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x51, 8 * KiB); 1090 1091 /* i2c1mux0ch7 */ 1092 /* eeprom@53 */ 1093 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 7), 0x53, 8 * KiB); 1094 /* temperature-sensor@4b - tmp75 */ 1095 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), TYPE_TMP75, 0x4b); 1096 1097 /* &i2c2 */ 1098 /* io_expander0 - pca9555@20 */ 1099 i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x20); 1100 /* io_expander0 - pca9555@21 */ 1101 i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x21); 1102 /* io_expander0 - pca9555@27 */ 1103 i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x27); 1104 /* eeprom@50 */ 1105 at24c_eeprom_init(i2c[2], 0x50, 8 * KiB); 1106 /* eeprom@51 */ 1107 at24c_eeprom_init(i2c[2], 0x51, 8 * KiB); 1108 1109 /* &i2c5 */ 1110 /* i2c-mux@70 (PCA9548) on i2c5 */ 1111 i2c_mux = i2c_slave_create_simple(i2c[5], TYPE_PCA9548, 0x70); 1112 /* i2c5mux0ch6 */ 1113 /* eeprom@52 */ 1114 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x52, 8 * KiB); 1115 /* i2c5mux0ch7 */ 1116 /* ina230@40 - no model */ 1117 /* ina230@41 - no model */ 1118 /* ina230@44 - no model */ 1119 /* ina230@45 - no model */ 1120 1121 /* &i2c6 */ 1122 /* io_expander3 - pca9555@21 */ 1123 i2c_slave_create_simple(i2c[6], TYPE_PCA9552, 0x21); 1124 /* rtc@6f - nct3018y */ 1125 i2c_slave_create_simple(i2c[6], TYPE_DS1338, 0x6f); 1126 1127 /* &i2c9 */ 1128 /* io_expander4 - pca9555@4f */ 1129 i2c_slave_create_simple(i2c[9], TYPE_PCA9552, 0x4f); 1130 /* temperature-sensor@4b - tpm75 */ 1131 i2c_slave_create_simple(i2c[9], TYPE_TMP75, 0x4b); 1132 /* eeprom@50 */ 1133 at24c_eeprom_init(i2c[9], 0x50, 8 * KiB); 1134 /* eeprom@56 */ 1135 at24c_eeprom_init(i2c[9], 0x56, 8 * KiB); 1136 1137 /* &i2c10 */ 1138 /* temperature-sensor@1f - tpm421 */ 1139 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x1f); 1140 /* eeprom@50 */ 1141 at24c_eeprom_init(i2c[10], 0x50, 8 * KiB); 1142 1143 /* &i2c11 */ 1144 /* ssif-bmc@10 - no model */ 1145 1146 /* &i2c12 */ 1147 /* eeprom@50 */ 1148 at24c_eeprom_init(i2c[12], 0x50, 8 * KiB); 1149 1150 /* &i2c13 */ 1151 /* eeprom@50 */ 1152 at24c_eeprom_init(i2c[13], 0x50, 8 * KiB); 1153 /* eeprom@54 */ 1154 at24c_eeprom_init(i2c[13], 0x54, 256); 1155 /* eeprom@55 */ 1156 at24c_eeprom_init(i2c[13], 0x55, 256); 1157 /* eeprom@57 */ 1158 at24c_eeprom_init(i2c[13], 0x57, 256); 1159 1160 /* &i2c14 */ 1161 /* io_expander9 - pca9555@10 */ 1162 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x10); 1163 /* io_expander10 - pca9555@11 */ 1164 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x11); 1165 /* io_expander11 - pca9555@12 */ 1166 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x12); 1167 /* io_expander12 - pca9555@13 */ 1168 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x13); 1169 /* io_expander13 - pca9555@14 */ 1170 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x14); 1171 /* io_expander14 - pca9555@15 */ 1172 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x15); 1173 1174 /* &i2c15 */ 1175 /* temperature-sensor@1f - tmp421 */ 1176 i2c_slave_create_simple(i2c[15], TYPE_TMP421, 0x1f); 1177 /* eeprom@52 */ 1178 at24c_eeprom_init(i2c[15], 0x52, 8 * KiB); 1179 } 1180 1181 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 1182 { 1183 AspeedSoCState *soc = bmc->soc; 1184 I2CBus *i2c[13] = {}; 1185 for (int i = 0; i < 13; i++) { 1186 if ((i == 8) || (i == 11)) { 1187 continue; 1188 } 1189 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1190 } 1191 1192 /* Bus 0 - 5 all have the same config. */ 1193 for (int i = 0; i < 6; i++) { 1194 /* Missing model: ti,ina230 @ 0x45 */ 1195 /* Missing model: mps,mp5023 @ 0x40 */ 1196 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 1197 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 1198 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 1199 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 1200 /* Missing model: fsc,fusb302 @ 0x22 */ 1201 } 1202 1203 /* Bus 6 */ 1204 at24c_eeprom_init(i2c[6], 0x56, 65536); 1205 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 1206 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 1207 1208 1209 /* Bus 7 */ 1210 at24c_eeprom_init(i2c[7], 0x54, 65536); 1211 1212 /* Bus 9 */ 1213 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 1214 1215 /* Bus 10 */ 1216 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 1217 /* Missing model: ti,hdc1080 @ 0x40 */ 1218 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 1219 1220 /* Bus 12 */ 1221 /* Missing model: adi,adm1278 @ 0x11 */ 1222 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 1223 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 1224 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 1225 } 1226 1227 static void fby35_i2c_init(AspeedMachineState *bmc) 1228 { 1229 AspeedSoCState *soc = bmc->soc; 1230 I2CBus *i2c[16]; 1231 1232 for (int i = 0; i < 16; i++) { 1233 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1234 } 1235 1236 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 1237 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 1238 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 1239 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 1240 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 1241 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 1242 1243 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 1244 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 1245 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 1246 fby35_nic_fruid_len); 1247 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 1248 fby35_bb_fruid_len); 1249 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 1250 fby35_bmc_fruid_len); 1251 1252 /* 1253 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 1254 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 1255 * each. 1256 */ 1257 } 1258 1259 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1260 { 1261 AspeedSoCState *soc = bmc->soc; 1262 1263 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1264 } 1265 1266 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1267 { 1268 AspeedSoCState *soc = bmc->soc; 1269 I2CSlave *therm_mux, *cpuvr_mux; 1270 1271 /* Create the generic DC-SCM hardware */ 1272 qcom_dc_scm_bmc_i2c_init(bmc); 1273 1274 /* Now create the Firework specific hardware */ 1275 1276 /* I2C7 CPUVR MUX */ 1277 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1278 "pca9546", 0x70); 1279 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1280 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1281 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1282 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1283 1284 /* I2C8 Thermal Diodes*/ 1285 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1286 "pca9548", 0x70); 1287 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1288 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1289 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1290 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1291 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1292 1293 /* I2C9 Fan Controller (MAX31785) */ 1294 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1295 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1296 } 1297 1298 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1299 { 1300 return ASPEED_MACHINE(obj)->mmio_exec; 1301 } 1302 1303 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1304 { 1305 ASPEED_MACHINE(obj)->mmio_exec = value; 1306 } 1307 1308 static void aspeed_machine_instance_init(Object *obj) 1309 { 1310 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj); 1311 1312 ASPEED_MACHINE(obj)->mmio_exec = false; 1313 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1; 1314 } 1315 1316 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1317 { 1318 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1319 return g_strdup(bmc->fmc_model); 1320 } 1321 1322 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1323 { 1324 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1325 1326 g_free(bmc->fmc_model); 1327 bmc->fmc_model = g_strdup(value); 1328 } 1329 1330 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1331 { 1332 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1333 return g_strdup(bmc->spi_model); 1334 } 1335 1336 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1337 { 1338 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1339 1340 g_free(bmc->spi_model); 1341 bmc->spi_model = g_strdup(value); 1342 } 1343 1344 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1345 { 1346 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1347 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1348 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1349 1350 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); 1351 } 1352 1353 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1354 { 1355 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1356 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1357 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1358 int val; 1359 int uart_first = aspeed_uart_first(sc); 1360 int uart_last = aspeed_uart_last(sc); 1361 1362 if (sscanf(value, "uart%u", &val) != 1) { 1363 error_setg(errp, "Bad value for \"uart\" property"); 1364 return; 1365 } 1366 1367 /* The number of UART depends on the SoC */ 1368 if (val < uart_first || val > uart_last) { 1369 error_setg(errp, "\"uart\" should be in range [%d - %d]", 1370 uart_first, uart_last); 1371 return; 1372 } 1373 bmc->uart_chosen = val + ASPEED_DEV_UART0; 1374 } 1375 1376 static void aspeed_machine_class_props_init(ObjectClass *oc) 1377 { 1378 object_class_property_add_bool(oc, "execute-in-place", 1379 aspeed_get_mmio_exec, 1380 aspeed_set_mmio_exec); 1381 object_class_property_set_description(oc, "execute-in-place", 1382 "boot directly from CE0 flash device"); 1383 1384 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1385 aspeed_set_bmc_console); 1386 object_class_property_set_description(oc, "bmc-console", 1387 "Change the default UART to \"uartX\""); 1388 1389 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1390 aspeed_set_fmc_model); 1391 object_class_property_set_description(oc, "fmc-model", 1392 "Change the FMC Flash model"); 1393 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1394 aspeed_set_spi_model); 1395 object_class_property_set_description(oc, "spi-model", 1396 "Change the SPI Flash model"); 1397 } 1398 1399 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) 1400 { 1401 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); 1402 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1403 1404 mc->default_cpus = sc->num_cpus; 1405 mc->min_cpus = sc->num_cpus; 1406 mc->max_cpus = sc->num_cpus; 1407 mc->valid_cpu_types = sc->valid_cpu_types; 1408 } 1409 1410 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp) 1411 { 1412 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1413 1414 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 1415 } 1416 1417 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value, 1418 Error **errp) 1419 { 1420 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1421 1422 if (value) { 1423 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1424 } else { 1425 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1426 } 1427 } 1428 1429 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc) 1430 { 1431 object_class_property_add_bool(oc, "boot-emmc", 1432 aspeed_machine_ast2600_get_boot_from_emmc, 1433 aspeed_machine_ast2600_set_boot_from_emmc); 1434 object_class_property_set_description(oc, "boot-emmc", 1435 "Set or unset boot from EMMC"); 1436 } 1437 1438 static void aspeed_machine_class_init(ObjectClass *oc, const void *data) 1439 { 1440 MachineClass *mc = MACHINE_CLASS(oc); 1441 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1442 1443 mc->init = aspeed_machine_init; 1444 mc->no_floppy = 1; 1445 mc->no_cdrom = 1; 1446 mc->no_parallel = 1; 1447 mc->default_ram_id = "ram"; 1448 amc->macs_mask = ASPEED_MAC0_ON; 1449 amc->uart_default = ASPEED_DEV_UART5; 1450 1451 aspeed_machine_class_props_init(oc); 1452 } 1453 1454 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, 1455 const void *data) 1456 { 1457 MachineClass *mc = MACHINE_CLASS(oc); 1458 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1459 1460 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1461 amc->soc_name = "ast2400-a1"; 1462 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1463 amc->fmc_model = "n25q256a"; 1464 amc->spi_model = "mx25l25635f"; 1465 amc->num_cs = 1; 1466 amc->i2c_init = palmetto_bmc_i2c_init; 1467 mc->auto_create_sdcard = true; 1468 mc->default_ram_size = 256 * MiB; 1469 aspeed_machine_class_init_cpus_defaults(mc); 1470 }; 1471 1472 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, 1473 const void *data) 1474 { 1475 MachineClass *mc = MACHINE_CLASS(oc); 1476 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1477 1478 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1479 amc->soc_name = "ast2400-a1"; 1480 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1481 amc->fmc_model = "n25q256a"; 1482 amc->spi_model = "mx25l25635e"; 1483 amc->num_cs = 1; 1484 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1485 mc->auto_create_sdcard = true; 1486 mc->default_ram_size = 128 * MiB; 1487 aspeed_machine_class_init_cpus_defaults(mc); 1488 } 1489 1490 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1491 const void *data) 1492 { 1493 MachineClass *mc = MACHINE_CLASS(oc); 1494 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1495 1496 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1497 amc->soc_name = "ast2400-a1"; 1498 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1499 amc->fmc_model = "mx25l25635e"; 1500 amc->spi_model = "mx25l25635e"; 1501 amc->num_cs = 1; 1502 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1503 amc->i2c_init = palmetto_bmc_i2c_init; 1504 mc->auto_create_sdcard = true; 1505 mc->default_ram_size = 256 * MiB; 1506 aspeed_machine_class_init_cpus_defaults(mc); 1507 } 1508 1509 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1510 const void *data) 1511 { 1512 MachineClass *mc = MACHINE_CLASS(oc); 1513 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1514 1515 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1516 amc->soc_name = "ast2500-a1"; 1517 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1518 amc->fmc_model = "mx25l25635e"; 1519 amc->spi_model = "mx25l25635e"; 1520 amc->num_cs = 1; 1521 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1522 amc->i2c_init = palmetto_bmc_i2c_init; 1523 mc->auto_create_sdcard = true; 1524 mc->default_ram_size = 512 * MiB; 1525 aspeed_machine_class_init_cpus_defaults(mc); 1526 } 1527 1528 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, 1529 const void *data) 1530 { 1531 MachineClass *mc = MACHINE_CLASS(oc); 1532 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1533 1534 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1535 amc->soc_name = "ast2500-a1"; 1536 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1537 amc->fmc_model = "mx25l25635e"; 1538 amc->spi_model = "mx25l25635f"; 1539 amc->num_cs = 1; 1540 amc->i2c_init = ast2500_evb_i2c_init; 1541 mc->auto_create_sdcard = true; 1542 mc->default_ram_size = 512 * MiB; 1543 aspeed_machine_class_init_cpus_defaults(mc); 1544 }; 1545 1546 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, 1547 const void *data) 1548 { 1549 MachineClass *mc = MACHINE_CLASS(oc); 1550 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1551 1552 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1553 amc->soc_name = "ast2500-a1"; 1554 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1555 amc->hw_strap2 = 0; 1556 amc->fmc_model = "n25q256a"; 1557 amc->spi_model = "mx25l25635e"; 1558 amc->num_cs = 2; 1559 amc->i2c_init = yosemitev2_bmc_i2c_init; 1560 mc->auto_create_sdcard = true; 1561 mc->default_ram_size = 512 * MiB; 1562 aspeed_machine_class_init_cpus_defaults(mc); 1563 }; 1564 1565 static void aspeed_machine_romulus_class_init(ObjectClass *oc, 1566 const void *data) 1567 { 1568 MachineClass *mc = MACHINE_CLASS(oc); 1569 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1570 1571 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1572 amc->soc_name = "ast2500-a1"; 1573 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1574 amc->fmc_model = "n25q256a"; 1575 amc->spi_model = "mx66l1g45g"; 1576 amc->num_cs = 2; 1577 amc->i2c_init = romulus_bmc_i2c_init; 1578 mc->auto_create_sdcard = true; 1579 mc->default_ram_size = 512 * MiB; 1580 aspeed_machine_class_init_cpus_defaults(mc); 1581 }; 1582 1583 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, 1584 const void *data) 1585 { 1586 MachineClass *mc = MACHINE_CLASS(oc); 1587 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1588 1589 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1590 amc->soc_name = "ast2500-a1"; 1591 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1592 amc->hw_strap2 = 0; 1593 amc->fmc_model = "n25q256a"; 1594 amc->spi_model = "mx25l25635e"; 1595 amc->num_cs = 2; 1596 amc->i2c_init = tiogapass_bmc_i2c_init; 1597 mc->auto_create_sdcard = true; 1598 mc->default_ram_size = 1 * GiB; 1599 aspeed_machine_class_init_cpus_defaults(mc); 1600 }; 1601 1602 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, 1603 const void *data) 1604 { 1605 MachineClass *mc = MACHINE_CLASS(oc); 1606 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1607 1608 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1609 amc->soc_name = "ast2500-a1"; 1610 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1611 amc->fmc_model = "mx66l1g45g"; 1612 amc->spi_model = "mx66l1g45g"; 1613 amc->num_cs = 2; 1614 amc->i2c_init = sonorapass_bmc_i2c_init; 1615 mc->auto_create_sdcard = true; 1616 mc->default_ram_size = 512 * MiB; 1617 aspeed_machine_class_init_cpus_defaults(mc); 1618 }; 1619 1620 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, 1621 const void *data) 1622 { 1623 MachineClass *mc = MACHINE_CLASS(oc); 1624 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1625 1626 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1627 amc->soc_name = "ast2500-a1"; 1628 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1629 amc->fmc_model = "mx25l25635f"; 1630 amc->spi_model = "mx66l1g45g"; 1631 amc->num_cs = 2; 1632 amc->i2c_init = witherspoon_bmc_i2c_init; 1633 mc->auto_create_sdcard = true; 1634 mc->default_ram_size = 512 * MiB; 1635 aspeed_machine_class_init_cpus_defaults(mc); 1636 }; 1637 1638 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, 1639 const void *data) 1640 { 1641 MachineClass *mc = MACHINE_CLASS(oc); 1642 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1643 1644 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1645 amc->soc_name = "ast2600-a3"; 1646 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1647 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1648 amc->fmc_model = "mx66u51235f"; 1649 amc->spi_model = "mx66u51235f"; 1650 amc->num_cs = 1; 1651 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1652 ASPEED_MAC3_ON; 1653 amc->sdhci_wp_inverted = true; 1654 amc->i2c_init = ast2600_evb_i2c_init; 1655 mc->auto_create_sdcard = true; 1656 mc->default_ram_size = 1 * GiB; 1657 aspeed_machine_class_init_cpus_defaults(mc); 1658 aspeed_machine_ast2600_class_emmc_init(oc); 1659 }; 1660 1661 static void aspeed_machine_g220a_class_init(ObjectClass *oc, const void *data) 1662 { 1663 MachineClass *mc = MACHINE_CLASS(oc); 1664 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1665 1666 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1667 amc->soc_name = "ast2500-a1"; 1668 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1669 amc->fmc_model = "n25q512a"; 1670 amc->spi_model = "mx25l25635e"; 1671 amc->num_cs = 2; 1672 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1673 amc->i2c_init = g220a_bmc_i2c_init; 1674 mc->auto_create_sdcard = true; 1675 mc->default_ram_size = 1024 * MiB; 1676 aspeed_machine_class_init_cpus_defaults(mc); 1677 }; 1678 1679 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, 1680 const void *data) 1681 { 1682 MachineClass *mc = MACHINE_CLASS(oc); 1683 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1684 1685 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1686 amc->soc_name = "ast2500-a1"; 1687 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1688 amc->fmc_model = "n25q512a"; 1689 amc->spi_model = "mx25l25635e"; 1690 amc->num_cs = 2; 1691 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1692 amc->i2c_init = fp5280g2_bmc_i2c_init; 1693 mc->auto_create_sdcard = true; 1694 mc->default_ram_size = 512 * MiB; 1695 aspeed_machine_class_init_cpus_defaults(mc); 1696 }; 1697 1698 static void aspeed_machine_rainier_class_init(ObjectClass *oc, const void *data) 1699 { 1700 MachineClass *mc = MACHINE_CLASS(oc); 1701 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1702 1703 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1704 amc->soc_name = "ast2600-a3"; 1705 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1706 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1707 amc->fmc_model = "mx66l1g45g"; 1708 amc->spi_model = "mx66l1g45g"; 1709 amc->num_cs = 2; 1710 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1711 amc->i2c_init = rainier_bmc_i2c_init; 1712 mc->auto_create_sdcard = true; 1713 mc->default_ram_size = 1 * GiB; 1714 aspeed_machine_class_init_cpus_defaults(mc); 1715 aspeed_machine_ast2600_class_emmc_init(oc); 1716 }; 1717 1718 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1719 1720 static void aspeed_machine_fuji_class_init(ObjectClass *oc, const void *data) 1721 { 1722 MachineClass *mc = MACHINE_CLASS(oc); 1723 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1724 1725 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1726 amc->soc_name = "ast2600-a3"; 1727 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1728 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1729 amc->fmc_model = "mx66l1g45g"; 1730 amc->spi_model = "mx66l1g45g"; 1731 amc->num_cs = 2; 1732 amc->macs_mask = ASPEED_MAC3_ON; 1733 amc->i2c_init = fuji_bmc_i2c_init; 1734 amc->uart_default = ASPEED_DEV_UART1; 1735 mc->auto_create_sdcard = true; 1736 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1737 aspeed_machine_class_init_cpus_defaults(mc); 1738 }; 1739 1740 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1741 1742 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, 1743 const void *data) 1744 { 1745 MachineClass *mc = MACHINE_CLASS(oc); 1746 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1747 1748 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1749 amc->soc_name = "ast2600-a3"; 1750 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1751 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1752 amc->fmc_model = "w25q01jvq"; 1753 amc->spi_model = NULL; 1754 amc->num_cs = 2; 1755 amc->macs_mask = ASPEED_MAC2_ON; 1756 amc->i2c_init = bletchley_bmc_i2c_init; 1757 mc->auto_create_sdcard = true; 1758 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1759 aspeed_machine_class_init_cpus_defaults(mc); 1760 } 1761 1762 static void aspeed_machine_catalina_class_init(ObjectClass *oc, 1763 const void *data) 1764 { 1765 MachineClass *mc = MACHINE_CLASS(oc); 1766 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1767 1768 mc->desc = "Facebook Catalina BMC (Cortex-A7)"; 1769 amc->soc_name = "ast2600-a3"; 1770 amc->hw_strap1 = CATALINA_BMC_HW_STRAP1; 1771 amc->hw_strap2 = CATALINA_BMC_HW_STRAP2; 1772 amc->fmc_model = "w25q01jvq"; 1773 amc->spi_model = NULL; 1774 amc->num_cs = 2; 1775 amc->macs_mask = ASPEED_MAC2_ON; 1776 amc->i2c_init = catalina_bmc_i2c_init; 1777 mc->auto_create_sdcard = true; 1778 mc->default_ram_size = CATALINA_BMC_RAM_SIZE; 1779 aspeed_machine_class_init_cpus_defaults(mc); 1780 aspeed_machine_ast2600_class_emmc_init(oc); 1781 } 1782 1783 static void fby35_reset(MachineState *state, ResetType type) 1784 { 1785 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1786 AspeedGPIOState *gpio = &bmc->soc->gpio; 1787 1788 qemu_devices_reset(type); 1789 1790 /* Board ID: 7 (Class-1, 4 slots) */ 1791 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1792 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1793 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1794 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1795 1796 /* Slot presence pins, inverse polarity. (False means present) */ 1797 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1798 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1799 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1800 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1801 1802 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1803 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1804 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1805 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1806 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1807 } 1808 1809 static void aspeed_machine_fby35_class_init(ObjectClass *oc, const void *data) 1810 { 1811 MachineClass *mc = MACHINE_CLASS(oc); 1812 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1813 1814 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1815 mc->reset = fby35_reset; 1816 amc->fmc_model = "mx66l1g45g"; 1817 amc->num_cs = 2; 1818 amc->macs_mask = ASPEED_MAC3_ON; 1819 amc->i2c_init = fby35_i2c_init; 1820 mc->auto_create_sdcard = true; 1821 /* FIXME: Replace this macro with something more general */ 1822 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1823 aspeed_machine_class_init_cpus_defaults(mc); 1824 } 1825 1826 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1827 /* Main SYSCLK frequency in Hz (200MHz) */ 1828 #define SYSCLK_FRQ 200000000ULL 1829 1830 static void aspeed_minibmc_machine_init(MachineState *machine) 1831 { 1832 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1833 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1834 Clock *sysclk; 1835 1836 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1837 clock_set_hz(sysclk, SYSCLK_FRQ); 1838 1839 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 1840 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 1841 object_unref(OBJECT(bmc->soc)); 1842 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); 1843 1844 object_property_set_link(OBJECT(bmc->soc), "memory", 1845 OBJECT(get_system_memory()), &error_abort); 1846 connect_serial_hds_to_uarts(bmc); 1847 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 1848 1849 if (defaults_enabled()) { 1850 aspeed_board_init_flashes(&bmc->soc->fmc, 1851 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1852 amc->num_cs, 1853 0); 1854 1855 aspeed_board_init_flashes(&bmc->soc->spi[0], 1856 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1857 amc->num_cs, amc->num_cs); 1858 1859 aspeed_board_init_flashes(&bmc->soc->spi[1], 1860 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1861 amc->num_cs, (amc->num_cs * 2)); 1862 } 1863 1864 if (amc->i2c_init) { 1865 amc->i2c_init(bmc); 1866 } 1867 1868 armv7m_load_kernel(ARM_CPU(first_cpu), 1869 machine->kernel_filename, 1870 0, 1871 AST1030_INTERNAL_FLASH_SIZE); 1872 } 1873 1874 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1875 { 1876 AspeedSoCState *soc = bmc->soc; 1877 1878 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1879 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1880 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1881 1882 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1883 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1884 } 1885 1886 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1887 const void *data) 1888 { 1889 MachineClass *mc = MACHINE_CLASS(oc); 1890 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1891 1892 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1893 amc->soc_name = "ast1030-a1"; 1894 amc->hw_strap1 = 0; 1895 amc->hw_strap2 = 0; 1896 mc->init = aspeed_minibmc_machine_init; 1897 amc->i2c_init = ast1030_evb_i2c_init; 1898 mc->default_ram_size = 0; 1899 amc->fmc_model = "w25q80bl"; 1900 amc->spi_model = "w25q256"; 1901 amc->num_cs = 2; 1902 amc->macs_mask = 0; 1903 aspeed_machine_class_init_cpus_defaults(mc); 1904 } 1905 1906 #ifdef TARGET_AARCH64 1907 static void ast2700_evb_i2c_init(AspeedMachineState *bmc) 1908 { 1909 AspeedSoCState *soc = bmc->soc; 1910 1911 /* LM75 is compatible with TMP105 driver */ 1912 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), 1913 TYPE_TMP105, 0x4d); 1914 } 1915 1916 static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, 1917 const void *data) 1918 { 1919 MachineClass *mc = MACHINE_CLASS(oc); 1920 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1921 1922 mc->alias = "ast2700-evb"; 1923 mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)"; 1924 amc->soc_name = "ast2700-a0"; 1925 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 1926 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 1927 amc->fmc_model = "w25q01jvq"; 1928 amc->spi_model = "w25q512jv"; 1929 amc->num_cs = 2; 1930 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 1931 amc->uart_default = ASPEED_DEV_UART12; 1932 amc->i2c_init = ast2700_evb_i2c_init; 1933 amc->vbootrom = true; 1934 mc->auto_create_sdcard = true; 1935 mc->default_ram_size = 1 * GiB; 1936 aspeed_machine_class_init_cpus_defaults(mc); 1937 } 1938 1939 static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, 1940 const void *data) 1941 { 1942 MachineClass *mc = MACHINE_CLASS(oc); 1943 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1944 1945 mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)"; 1946 amc->soc_name = "ast2700-a1"; 1947 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 1948 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 1949 amc->fmc_model = "w25q01jvq"; 1950 amc->spi_model = "w25q512jv"; 1951 amc->num_cs = 2; 1952 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 1953 amc->uart_default = ASPEED_DEV_UART12; 1954 amc->i2c_init = ast2700_evb_i2c_init; 1955 amc->vbootrom = true; 1956 mc->auto_create_sdcard = true; 1957 mc->default_ram_size = 1 * GiB; 1958 aspeed_machine_class_init_cpus_defaults(mc); 1959 } 1960 #endif 1961 1962 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1963 const void *data) 1964 { 1965 MachineClass *mc = MACHINE_CLASS(oc); 1966 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1967 1968 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1969 amc->soc_name = "ast2600-a3"; 1970 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1971 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1972 amc->fmc_model = "n25q512a"; 1973 amc->spi_model = "n25q512a"; 1974 amc->num_cs = 2; 1975 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1976 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1977 mc->auto_create_sdcard = true; 1978 mc->default_ram_size = 1 * GiB; 1979 aspeed_machine_class_init_cpus_defaults(mc); 1980 }; 1981 1982 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1983 const void *data) 1984 { 1985 MachineClass *mc = MACHINE_CLASS(oc); 1986 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1987 1988 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1989 amc->soc_name = "ast2600-a3"; 1990 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1991 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1992 amc->fmc_model = "n25q512a"; 1993 amc->spi_model = "n25q512a"; 1994 amc->num_cs = 2; 1995 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1996 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1997 mc->auto_create_sdcard = true; 1998 mc->default_ram_size = 1 * GiB; 1999 aspeed_machine_class_init_cpus_defaults(mc); 2000 }; 2001 2002 static const TypeInfo aspeed_machine_types[] = { 2003 { 2004 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 2005 .parent = TYPE_ASPEED_MACHINE, 2006 .class_init = aspeed_machine_palmetto_class_init, 2007 }, { 2008 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 2009 .parent = TYPE_ASPEED_MACHINE, 2010 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 2011 }, { 2012 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 2013 .parent = TYPE_ASPEED_MACHINE, 2014 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 2015 }, { 2016 .name = MACHINE_TYPE_NAME("ast2500-evb"), 2017 .parent = TYPE_ASPEED_MACHINE, 2018 .class_init = aspeed_machine_ast2500_evb_class_init, 2019 }, { 2020 .name = MACHINE_TYPE_NAME("romulus-bmc"), 2021 .parent = TYPE_ASPEED_MACHINE, 2022 .class_init = aspeed_machine_romulus_class_init, 2023 }, { 2024 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 2025 .parent = TYPE_ASPEED_MACHINE, 2026 .class_init = aspeed_machine_sonorapass_class_init, 2027 }, { 2028 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 2029 .parent = TYPE_ASPEED_MACHINE, 2030 .class_init = aspeed_machine_witherspoon_class_init, 2031 }, { 2032 .name = MACHINE_TYPE_NAME("ast2600-evb"), 2033 .parent = TYPE_ASPEED_MACHINE, 2034 .class_init = aspeed_machine_ast2600_evb_class_init, 2035 }, { 2036 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 2037 .parent = TYPE_ASPEED_MACHINE, 2038 .class_init = aspeed_machine_yosemitev2_class_init, 2039 }, { 2040 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 2041 .parent = TYPE_ASPEED_MACHINE, 2042 .class_init = aspeed_machine_tiogapass_class_init, 2043 }, { 2044 .name = MACHINE_TYPE_NAME("g220a-bmc"), 2045 .parent = TYPE_ASPEED_MACHINE, 2046 .class_init = aspeed_machine_g220a_class_init, 2047 }, { 2048 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 2049 .parent = TYPE_ASPEED_MACHINE, 2050 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 2051 }, { 2052 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 2053 .parent = TYPE_ASPEED_MACHINE, 2054 .class_init = aspeed_machine_qcom_firework_class_init, 2055 }, { 2056 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 2057 .parent = TYPE_ASPEED_MACHINE, 2058 .class_init = aspeed_machine_fp5280g2_class_init, 2059 }, { 2060 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 2061 .parent = TYPE_ASPEED_MACHINE, 2062 .class_init = aspeed_machine_quanta_q71l_class_init, 2063 }, { 2064 .name = MACHINE_TYPE_NAME("rainier-bmc"), 2065 .parent = TYPE_ASPEED_MACHINE, 2066 .class_init = aspeed_machine_rainier_class_init, 2067 }, { 2068 .name = MACHINE_TYPE_NAME("fuji-bmc"), 2069 .parent = TYPE_ASPEED_MACHINE, 2070 .class_init = aspeed_machine_fuji_class_init, 2071 }, { 2072 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 2073 .parent = TYPE_ASPEED_MACHINE, 2074 .class_init = aspeed_machine_bletchley_class_init, 2075 }, { 2076 .name = MACHINE_TYPE_NAME("catalina-bmc"), 2077 .parent = TYPE_ASPEED_MACHINE, 2078 .class_init = aspeed_machine_catalina_class_init, 2079 }, { 2080 .name = MACHINE_TYPE_NAME("fby35-bmc"), 2081 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 2082 .class_init = aspeed_machine_fby35_class_init, 2083 }, { 2084 .name = MACHINE_TYPE_NAME("ast1030-evb"), 2085 .parent = TYPE_ASPEED_MACHINE, 2086 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 2087 #ifdef TARGET_AARCH64 2088 }, { 2089 .name = MACHINE_TYPE_NAME("ast2700a0-evb"), 2090 .parent = TYPE_ASPEED_MACHINE, 2091 .class_init = aspeed_machine_ast2700a0_evb_class_init, 2092 }, { 2093 .name = MACHINE_TYPE_NAME("ast2700a1-evb"), 2094 .parent = TYPE_ASPEED_MACHINE, 2095 .class_init = aspeed_machine_ast2700a1_evb_class_init, 2096 #endif 2097 }, { 2098 .name = TYPE_ASPEED_MACHINE, 2099 .parent = TYPE_MACHINE, 2100 .instance_size = sizeof(AspeedMachineState), 2101 .instance_init = aspeed_machine_instance_init, 2102 .class_size = sizeof(AspeedMachineClass), 2103 .class_init = aspeed_machine_class_init, 2104 .abstract = true, 2105 } 2106 }; 2107 2108 DEFINE_TYPES(aspeed_machine_types) 2109