1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/block/flash.h" 19 #include "hw/i2c/i2c_mux_pca954x.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/misc/pca9552.h" 22 #include "hw/nvram/eeprom_at24c.h" 23 #include "hw/sensor/tmp105.h" 24 #include "hw/misc/led.h" 25 #include "hw/qdev-properties.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/reset.h" 28 #include "hw/loader.h" 29 #include "qemu/error-report.h" 30 #include "qemu/units.h" 31 #include "hw/qdev-clock.h" 32 #include "sysemu/sysemu.h" 33 34 static struct arm_boot_info aspeed_board_binfo = { 35 .board_id = -1, /* device-tree-only board */ 36 }; 37 38 struct AspeedMachineState { 39 /* Private */ 40 MachineState parent_obj; 41 /* Public */ 42 43 AspeedSoCState *soc; 44 MemoryRegion boot_rom; 45 bool mmio_exec; 46 uint32_t uart_chosen; 47 char *fmc_model; 48 char *spi_model; 49 uint32_t hw_strap1; 50 }; 51 52 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 53 #if HOST_LONG_BITS == 32 54 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) 55 #else 56 #define ASPEED_RAM_SIZE(sz) (sz) 57 #endif 58 59 /* Palmetto hardware value: 0x120CE416 */ 60 #define PALMETTO_BMC_HW_STRAP1 ( \ 61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 63 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 65 SCU_HW_STRAP_VGA_CLASS_CODE | \ 66 SCU_HW_STRAP_LPC_RESET_PIN | \ 67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 69 SCU_HW_STRAP_SPI_WIDTH | \ 70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 72 73 /* TODO: Find the actual hardware value */ 74 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 75 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 76 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 77 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 78 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 79 SCU_HW_STRAP_VGA_CLASS_CODE | \ 80 SCU_HW_STRAP_LPC_RESET_PIN | \ 81 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 82 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 83 SCU_HW_STRAP_SPI_WIDTH | \ 84 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 85 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 86 87 /* TODO: Find the actual hardware value */ 88 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 89 AST2500_HW_STRAP1_DEFAULTS | \ 90 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 91 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 92 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 93 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 94 SCU_HW_STRAP_SPI_WIDTH | \ 95 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 96 97 /* AST2500 evb hardware value: 0xF100C2E6 */ 98 #define AST2500_EVB_HW_STRAP1 (( \ 99 AST2500_HW_STRAP1_DEFAULTS | \ 100 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 101 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 102 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 103 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 104 SCU_HW_STRAP_MAC1_RGMII | \ 105 SCU_HW_STRAP_MAC0_RGMII) & \ 106 ~SCU_HW_STRAP_2ND_BOOT_WDT) 107 108 /* Romulus hardware value: 0xF10AD206 */ 109 #define ROMULUS_BMC_HW_STRAP1 ( \ 110 AST2500_HW_STRAP1_DEFAULTS | \ 111 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 112 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 113 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 114 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 115 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 116 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 117 118 /* Sonorapass hardware value: 0xF100D216 */ 119 #define SONORAPASS_BMC_HW_STRAP1 ( \ 120 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 121 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 122 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 123 SCU_AST2500_HW_STRAP_RESERVED28 | \ 124 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 125 SCU_HW_STRAP_VGA_CLASS_CODE | \ 126 SCU_HW_STRAP_LPC_RESET_PIN | \ 127 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 128 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 129 SCU_HW_STRAP_VGA_BIOS_ROM | \ 130 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 131 SCU_AST2500_HW_STRAP_RESERVED1) 132 133 #define G220A_BMC_HW_STRAP1 ( \ 134 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 135 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 136 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 137 SCU_AST2500_HW_STRAP_RESERVED28 | \ 138 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 139 SCU_HW_STRAP_2ND_BOOT_WDT | \ 140 SCU_HW_STRAP_VGA_CLASS_CODE | \ 141 SCU_HW_STRAP_LPC_RESET_PIN | \ 142 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 143 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 144 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 145 SCU_AST2500_HW_STRAP_RESERVED1) 146 147 /* FP5280G2 hardware value: 0XF100D286 */ 148 #define FP5280G2_BMC_HW_STRAP1 ( \ 149 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 150 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 151 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 152 SCU_AST2500_HW_STRAP_RESERVED28 | \ 153 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 154 SCU_HW_STRAP_VGA_CLASS_CODE | \ 155 SCU_HW_STRAP_LPC_RESET_PIN | \ 156 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 157 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 158 SCU_HW_STRAP_MAC1_RGMII | \ 159 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 160 SCU_AST2500_HW_STRAP_RESERVED1) 161 162 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 163 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 164 165 /* Quanta-Q71l hardware value */ 166 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 167 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 168 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 169 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 170 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 171 SCU_HW_STRAP_VGA_CLASS_CODE | \ 172 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 173 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 174 SCU_HW_STRAP_SPI_WIDTH | \ 175 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 176 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 177 178 /* AST2600 evb hardware value */ 179 #define AST2600_EVB_HW_STRAP1 0x000000C0 180 #define AST2600_EVB_HW_STRAP2 0x00000003 181 182 /* Tacoma hardware value */ 183 #define TACOMA_BMC_HW_STRAP1 (0x00000000 | AST26500_HW_STRAP_BOOT_SRC_EMMC) 184 #define TACOMA_BMC_HW_STRAP2 0x00000040 185 186 /* Rainier hardware value: (QEMU prototype) */ 187 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | AST26500_HW_STRAP_BOOT_SRC_EMMC) 188 #define RAINIER_BMC_HW_STRAP2 0x80000848 189 190 /* Fuji hardware value */ 191 #define FUJI_BMC_HW_STRAP1 0x00000000 192 #define FUJI_BMC_HW_STRAP2 0x00000000 193 194 /* Montblanc hardware value */ 195 #define MONTBLANC_BMC_HW_STRAP1 0x00000000 196 #define MONTBLANC_BMC_HW_STRAP2 0x00000000 197 198 /* Bletchley hardware value */ 199 /* TODO: Leave same as EVB for now. */ 200 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 201 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 202 203 /* Qualcomm DC-SCM hardware value */ 204 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 205 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 206 207 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 208 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 209 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 210 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 211 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 212 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 213 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 214 215 static void aspeed_write_smpboot(ARMCPU *cpu, 216 const struct arm_boot_info *info) 217 { 218 AddressSpace *as = arm_boot_address_space(cpu, info); 219 static const ARMInsnFixup poll_mailbox_ready[] = { 220 /* 221 * r2 = per-cpu go sign value 222 * r1 = AST_SMP_MBOX_FIELD_ENTRY 223 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 224 */ 225 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 226 { 0xe21000ff }, /* ands r0, r0, #255 */ 227 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 228 { 0xe1822000 }, /* orr r2, r2, r0 */ 229 230 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 231 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 232 233 { 0xe320f002 }, /* wfe */ 234 { 0xe5904000 }, /* ldr r4, [r0] */ 235 { 0xe1520004 }, /* cmp r2, r4 */ 236 { 0x1afffffb }, /* bne <wfe> */ 237 { 0xe591f000 }, /* ldr pc, [r1] */ 238 { AST_SMP_MBOX_GOSIGN }, 239 { AST_SMP_MBOX_FIELD_ENTRY }, 240 { AST_SMP_MBOX_FIELD_GOSIGN }, 241 { 0, FIXUP_TERMINATOR } 242 }; 243 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 244 245 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 246 poll_mailbox_ready, fixupcontext); 247 } 248 249 static void aspeed_reset_secondary(ARMCPU *cpu, 250 const struct arm_boot_info *info) 251 { 252 AddressSpace *as = arm_boot_address_space(cpu, info); 253 CPUState *cs = CPU(cpu); 254 255 /* info->smp_bootreg_addr */ 256 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 257 MEMTXATTRS_UNSPECIFIED, NULL); 258 cpu_set_pc(cs, info->smp_loader_start); 259 } 260 261 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 262 Error **errp) 263 { 264 g_autofree void *storage = NULL; 265 int64_t size; 266 267 /* The block backend size should have already been 'validated' by 268 * the creation of the m25p80 object. 269 */ 270 size = blk_getlength(blk); 271 if (size <= 0) { 272 error_setg(errp, "failed to get flash size"); 273 return; 274 } 275 276 if (rom_size > size) { 277 rom_size = size; 278 } 279 280 storage = g_malloc0(rom_size); 281 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 282 error_setg(errp, "failed to read the initial flash content"); 283 return; 284 } 285 286 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 287 } 288 289 /* 290 * Create a ROM and copy the flash contents at the expected address 291 * (0x0). Boots faster than execute-in-place. 292 */ 293 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 294 uint64_t rom_size) 295 { 296 AspeedSoCState *soc = bmc->soc; 297 298 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 299 &error_abort); 300 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 301 &bmc->boot_rom, 1); 302 write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort); 303 } 304 305 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 306 unsigned int count, int unit0) 307 { 308 int i; 309 310 if (!flashtype) { 311 return; 312 } 313 314 for (i = 0; i < count; ++i) { 315 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 316 DeviceState *dev; 317 318 dev = qdev_new(flashtype); 319 if (dinfo) { 320 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 321 } 322 qdev_prop_set_uint8(dev, "cs", i); 323 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 324 } 325 } 326 327 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc, 328 bool boot_emmc) 329 { 330 DeviceState *card; 331 332 if (!dinfo) { 333 return; 334 } 335 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); 336 if (emmc) { 337 qdev_prop_set_uint8(card, "spec_version", SD_PHY_SPECv3_01_VERS); 338 qdev_prop_set_uint8(card, "boot-config", boot_emmc ? 0x48 : 0x0); 339 } 340 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 341 &error_fatal); 342 qdev_realize_and_unref(card, 343 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 344 &error_fatal); 345 } 346 347 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 348 { 349 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 350 AspeedSoCState *s = bmc->soc; 351 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 352 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 353 354 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 355 for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) { 356 if (uart == uart_chosen) { 357 continue; 358 } 359 aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); 360 } 361 } 362 363 static void aspeed_machine_init(MachineState *machine) 364 { 365 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 366 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 367 AspeedSoCClass *sc; 368 int i; 369 NICInfo *nd = &nd_table[0]; 370 DriveInfo *emmc0 = NULL; 371 bool boot_emmc; 372 373 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 374 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 375 object_unref(OBJECT(bmc->soc)); 376 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 377 378 boot_emmc = sc->boot_emmc && 379 !!(bmc->hw_strap1 & AST26500_HW_STRAP_BOOT_SRC_EMMC); 380 381 /* 382 * This will error out if the RAM size is not supported by the 383 * memory controller of the SoC. 384 */ 385 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 386 &error_fatal); 387 388 for (i = 0; i < sc->macs_num; i++) { 389 if ((amc->macs_mask & (1 << i)) && nd->used) { 390 qemu_check_nic_model(nd, TYPE_FTGMAC100); 391 qdev_set_nic_properties(DEVICE(&bmc->soc->ftgmac100[i]), nd); 392 nd++; 393 } 394 } 395 396 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1, 397 &error_abort); 398 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 399 &error_abort); 400 object_property_set_link(OBJECT(bmc->soc), "memory", 401 OBJECT(get_system_memory()), &error_abort); 402 object_property_set_link(OBJECT(bmc->soc), "dram", 403 OBJECT(machine->ram), &error_abort); 404 if (machine->kernel_filename) { 405 /* 406 * When booting with a -kernel command line there is no u-boot 407 * that runs to unlock the SCU. In this case set the default to 408 * be unlocked as the kernel expects 409 */ 410 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 411 ASPEED_SCU_PROT_KEY, &error_abort); 412 } 413 connect_serial_hds_to_uarts(bmc); 414 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 415 416 if (defaults_enabled()) { 417 aspeed_board_init_flashes(&bmc->soc->fmc, 418 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 419 amc->num_cs, 0); 420 aspeed_board_init_flashes(&bmc->soc->spi[0], 421 bmc->spi_model ? bmc->spi_model : amc->spi_model, 422 1, amc->num_cs); 423 } 424 425 if (machine->kernel_filename && sc->num_cpus > 1) { 426 /* With no u-boot we must set up a boot stub for the secondary CPU */ 427 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 428 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 429 0x80, &error_abort); 430 memory_region_add_subregion(get_system_memory(), 431 AST_SMP_MAILBOX_BASE, smpboot); 432 433 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 434 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 435 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 436 } 437 438 aspeed_board_binfo.ram_size = machine->ram_size; 439 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 440 441 if (amc->i2c_init) { 442 amc->i2c_init(bmc); 443 } 444 445 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 446 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 447 drive_get(IF_SD, 0, i), false, false); 448 } 449 450 if (bmc->soc->emmc.num_slots) { 451 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); 452 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc); 453 } 454 455 if (!bmc->mmio_exec) { 456 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 457 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 458 459 if (fmc0 && !boot_emmc) { 460 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 461 aspeed_install_boot_rom(bmc, fmc0, rom_size); 462 } else if (emmc0) { 463 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB); 464 } 465 } 466 467 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 468 } 469 470 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 471 { 472 AspeedSoCState *soc = bmc->soc; 473 DeviceState *dev; 474 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 475 476 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 477 * enough to provide basic RTC features. Alarms will be missing */ 478 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 479 480 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 481 eeprom_buf); 482 483 /* add a TMP423 temperature sensor */ 484 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 485 "tmp423", 0x4c)); 486 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 487 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 488 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 489 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 490 } 491 492 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 493 { 494 AspeedSoCState *soc = bmc->soc; 495 496 /* 497 * The quanta-q71l platform expects tmp75s which are compatible with 498 * tmp105s. 499 */ 500 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 501 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 502 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 503 504 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 505 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 506 /* TODO: Add Memory Riser i2c mux and eeproms. */ 507 508 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 509 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 510 511 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 512 513 /* i2c-7 */ 514 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 515 /* - i2c@0: pmbus@59 */ 516 /* - i2c@1: pmbus@58 */ 517 /* - i2c@2: pmbus@58 */ 518 /* - i2c@3: pmbus@59 */ 519 520 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 521 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 522 } 523 524 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 525 { 526 AspeedSoCState *soc = bmc->soc; 527 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 528 529 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 530 eeprom_buf); 531 532 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 533 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 534 TYPE_TMP105, 0x4d); 535 } 536 537 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 538 { 539 AspeedSoCState *soc = bmc->soc; 540 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 541 542 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 543 eeprom_buf); 544 545 /* LM75 is compatible with TMP105 driver */ 546 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 547 TYPE_TMP105, 0x4d); 548 } 549 550 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 551 { 552 AspeedSoCState *soc = bmc->soc; 553 554 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 555 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 556 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 557 /* TMP421 */ 558 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 559 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 560 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 561 562 } 563 564 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 565 { 566 AspeedSoCState *soc = bmc->soc; 567 568 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 569 * good enough */ 570 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 571 } 572 573 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 574 { 575 AspeedSoCState *soc = bmc->soc; 576 577 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 578 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 579 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 580 /* TMP421 */ 581 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 582 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 583 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 584 } 585 586 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 587 { 588 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 589 TYPE_PCA9552, addr); 590 } 591 592 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 593 { 594 AspeedSoCState *soc = bmc->soc; 595 596 /* bus 2 : */ 597 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 598 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 599 /* bus 2 : pca9546 @ 0x73 */ 600 601 /* bus 3 : pca9548 @ 0x70 */ 602 603 /* bus 4 : */ 604 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 605 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 606 eeprom4_54); 607 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 608 create_pca9552(soc, 4, 0x76); 609 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 610 create_pca9552(soc, 4, 0x77); 611 612 /* bus 6 : */ 613 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 614 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 615 /* bus 6 : pca9546 @ 0x73 */ 616 617 /* bus 8 : */ 618 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 619 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 620 eeprom8_56); 621 create_pca9552(soc, 8, 0x60); 622 create_pca9552(soc, 8, 0x61); 623 /* bus 8 : adc128d818 @ 0x1d */ 624 /* bus 8 : adc128d818 @ 0x1f */ 625 626 /* 627 * bus 13 : pca9548 @ 0x71 628 * - channel 3: 629 * - tmm421 @ 0x4c 630 * - tmp421 @ 0x4e 631 * - tmp421 @ 0x4f 632 */ 633 634 } 635 636 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 637 { 638 static const struct { 639 unsigned gpio_id; 640 LEDColor color; 641 const char *description; 642 bool gpio_polarity; 643 } pca1_leds[] = { 644 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 645 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 646 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 647 }; 648 AspeedSoCState *soc = bmc->soc; 649 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 650 DeviceState *dev; 651 LEDState *led; 652 653 /* Bus 3: TODO bmp280@77 */ 654 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 655 qdev_prop_set_string(dev, "description", "pca1"); 656 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 657 aspeed_i2c_get_bus(&soc->i2c, 3), 658 &error_fatal); 659 660 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 661 led = led_create_simple(OBJECT(bmc), 662 pca1_leds[i].gpio_polarity, 663 pca1_leds[i].color, 664 pca1_leds[i].description); 665 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 666 qdev_get_gpio_in(DEVICE(led), 0)); 667 } 668 669 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 670 0x68); 671 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 672 0x69); 673 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 674 675 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 676 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 677 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ir35221", 0x70); 678 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ir35221", 0x71); 679 680 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 681 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "ir35221", 0x70); 682 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "ir35221", 0x71); 683 684 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 685 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 686 0x4a); 687 688 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 689 * good enough */ 690 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 691 692 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 693 eeprom_buf); 694 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 695 qdev_prop_set_string(dev, "description", "pca0"); 696 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 697 aspeed_i2c_get_bus(&soc->i2c, 11), 698 &error_fatal); 699 /* Bus 11: TODO ucd90160@64 */ 700 } 701 702 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 703 { 704 AspeedSoCState *soc = bmc->soc; 705 DeviceState *dev; 706 707 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 708 "emc1413", 0x4c)); 709 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 710 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 711 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 712 713 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 714 "emc1413", 0x4c)); 715 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 716 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 717 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 718 719 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 720 "emc1413", 0x4c)); 721 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 722 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 723 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 724 725 static uint8_t eeprom_buf[2 * 1024] = { 726 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 727 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 728 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 729 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 730 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 731 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 732 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 733 }; 734 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 735 eeprom_buf); 736 } 737 738 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 739 { 740 AspeedSoCState *soc = bmc->soc; 741 I2CSlave *i2c_mux; 742 743 /* The at24c256 */ 744 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 745 746 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 747 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 748 0x48); 749 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 750 0x49); 751 752 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 753 "pca9546", 0x70); 754 /* It expects a TMP112 but a TMP105 is compatible */ 755 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 756 0x4a); 757 758 /* It expects a ds3232 but a ds1338 is good enough */ 759 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 760 761 /* It expects a pca9555 but a pca9552 is compatible */ 762 create_pca9552(soc, 8, 0x30); 763 } 764 765 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 766 { 767 AspeedSoCState *soc = bmc->soc; 768 I2CSlave *i2c_mux; 769 770 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 771 772 create_pca9552(soc, 3, 0x61); 773 774 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 775 0x68); 776 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 777 0x69); 778 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 779 0x6a); 780 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 781 0x6b); 782 783 /* The rainier expects a TMP275 but a TMP105 is compatible */ 784 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 785 0x48); 786 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 787 0x49); 788 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 789 0x4a); 790 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 791 "pca9546", 0x70); 792 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 793 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 794 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 795 create_pca9552(soc, 4, 0x60); 796 797 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 798 0x48); 799 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 800 0x49); 801 create_pca9552(soc, 5, 0x60); 802 create_pca9552(soc, 5, 0x61); 803 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 804 "pca9546", 0x70); 805 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 806 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 807 808 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 809 0x48); 810 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 811 0x4a); 812 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 813 0x4b); 814 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 815 "pca9546", 0x70); 816 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 817 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 818 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 819 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 820 821 create_pca9552(soc, 7, 0x30); 822 create_pca9552(soc, 7, 0x31); 823 create_pca9552(soc, 7, 0x32); 824 create_pca9552(soc, 7, 0x33); 825 create_pca9552(soc, 7, 0x60); 826 create_pca9552(soc, 7, 0x61); 827 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 828 /* Bus 7: TODO si7021-a20@20 */ 829 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 830 0x48); 831 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 832 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 833 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 834 835 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 836 0x48); 837 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 838 0x4a); 839 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 840 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 841 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 842 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 843 create_pca9552(soc, 8, 0x60); 844 create_pca9552(soc, 8, 0x61); 845 /* Bus 8: ucd90320@11 */ 846 /* Bus 8: ucd90320@b */ 847 /* Bus 8: ucd90320@c */ 848 849 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x42); 850 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x43); 851 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x44); 852 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x72); 853 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x73); 854 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x74); 855 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 856 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 857 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 858 859 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x42); 860 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x43); 861 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x44); 862 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x72); 863 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x73); 864 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x74); 865 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 866 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 867 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 868 869 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 870 0x48); 871 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 872 0x49); 873 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 874 "pca9546", 0x70); 875 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 876 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 877 create_pca9552(soc, 11, 0x60); 878 879 880 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 881 create_pca9552(soc, 13, 0x60); 882 883 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 884 create_pca9552(soc, 14, 0x60); 885 886 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 887 create_pca9552(soc, 15, 0x60); 888 } 889 890 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 891 I2CBus **channels) 892 { 893 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 894 for (int i = 0; i < 8; i++) { 895 channels[i] = pca954x_i2c_get_bus(mux, i); 896 } 897 } 898 899 #define TYPE_LM75 TYPE_TMP105 900 #define TYPE_TMP75 TYPE_TMP105 901 #define TYPE_TMP422 "tmp422" 902 903 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 904 { 905 AspeedSoCState *soc = bmc->soc; 906 I2CBus *i2c[144] = {}; 907 908 for (int i = 0; i < 16; i++) { 909 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 910 } 911 I2CBus *i2c180 = i2c[2]; 912 I2CBus *i2c480 = i2c[8]; 913 I2CBus *i2c600 = i2c[11]; 914 915 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 916 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 917 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 918 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 919 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 920 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 921 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 922 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 923 for (int i = 0; i < 8; i++) { 924 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 925 } 926 927 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 928 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 929 930 /* 931 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 932 * 24c02 size is 2Kbits or 256 bytes 933 */ 934 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 935 at24c_eeprom_init(i2c[20], 0x50, 256); 936 at24c_eeprom_init(i2c[22], 0x52, 256); 937 938 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 939 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 940 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 941 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 942 943 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 944 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 945 946 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 947 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 948 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 949 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 950 951 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 952 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 953 954 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 955 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 956 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 957 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 958 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 959 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 960 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 961 962 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 963 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 964 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 965 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 966 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 967 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 968 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 969 at24c_eeprom_init(i2c[28], 0x50, 256); 970 971 for (int i = 0; i < 8; i++) { 972 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 973 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 974 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 975 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 976 } 977 } 978 979 static void montblanc_bmc_i2c_init(AspeedMachineState *bmc) 980 { 981 AspeedSoCState *soc = bmc->soc; 982 I2CBus *i2c[16] = {}; 983 984 for (int i = 0; i < 16; i++) { 985 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 986 } 987 988 /* Ref from Minipack3_I2C_Tree_V1.6 20230320 */ 989 at24c_eeprom_init_rom(i2c[3], 0x56, 8192, montblanc_scm_fruid, 990 montblanc_scm_fruid_len); 991 at24c_eeprom_init_rom(i2c[6], 0x53, 8192, montblanc_fcm_fruid, 992 montblanc_fcm_fruid_len); 993 994 /* CPLD and FPGA */ 995 at24c_eeprom_init(i2c[1], 0x35, 256); /* SCM CPLD */ 996 at24c_eeprom_init(i2c[5], 0x35, 256); /* COMe CPLD TODO: need to update */ 997 at24c_eeprom_init(i2c[12], 0x60, 256); /* MCB PWR CPLD */ 998 at24c_eeprom_init(i2c[13], 0x35, 256); /* IOB FPGA */ 999 1000 /* on BMC board */ 1001 at24c_eeprom_init_rom(i2c[8], 0x51, 8192, montblanc_bmc_fruid, 1002 montblanc_bmc_fruid_len); /* BMC EEPROM */ 1003 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x48); /* Thermal Sensor */ 1004 1005 /* COMe Sensor/EEPROM */ 1006 at24c_eeprom_init(i2c[0], 0x56, 16384); /* FRU EEPROM */ 1007 i2c_slave_create_simple(i2c[0], TYPE_LM75, 0x48); /* INLET Sensor */ 1008 i2c_slave_create_simple(i2c[0], TYPE_LM75, 0x4A); /* OUTLET Sensor */ 1009 1010 /* It expects a pca9555 but a pca9552 is compatible */ 1011 create_pca9552(soc, 4, 0x27); 1012 } 1013 1014 #define TYPE_TMP421 "tmp421" 1015 1016 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 1017 { 1018 AspeedSoCState *soc = bmc->soc; 1019 I2CBus *i2c[13] = {}; 1020 for (int i = 0; i < 13; i++) { 1021 if ((i == 8) || (i == 11)) { 1022 continue; 1023 } 1024 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1025 } 1026 1027 /* Bus 0 - 5 all have the same config. */ 1028 for (int i = 0; i < 6; i++) { 1029 /* Missing model: ti,ina230 @ 0x45 */ 1030 /* Missing model: mps,mp5023 @ 0x40 */ 1031 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 1032 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 1033 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 1034 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 1035 /* Missing model: fsc,fusb302 @ 0x22 */ 1036 } 1037 1038 /* Bus 6 */ 1039 at24c_eeprom_init(i2c[6], 0x56, 65536); 1040 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 1041 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 1042 1043 1044 /* Bus 7 */ 1045 at24c_eeprom_init(i2c[7], 0x54, 65536); 1046 1047 /* Bus 9 */ 1048 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 1049 1050 /* Bus 10 */ 1051 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 1052 /* Missing model: ti,hdc1080 @ 0x40 */ 1053 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 1054 1055 /* Bus 12 */ 1056 /* Missing model: adi,adm1278 @ 0x11 */ 1057 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 1058 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 1059 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 1060 } 1061 1062 static void fby35_i2c_init(AspeedMachineState *bmc) 1063 { 1064 AspeedSoCState *soc = bmc->soc; 1065 I2CBus *i2c[16]; 1066 1067 for (int i = 0; i < 16; i++) { 1068 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1069 } 1070 1071 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 1072 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 1073 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 1074 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 1075 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 1076 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 1077 1078 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 1079 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 1080 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 1081 fby35_nic_fruid_len); 1082 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 1083 fby35_bb_fruid_len); 1084 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 1085 fby35_bmc_fruid_len); 1086 1087 /* 1088 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 1089 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 1090 * each. 1091 */ 1092 } 1093 1094 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1095 { 1096 AspeedSoCState *soc = bmc->soc; 1097 1098 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1099 } 1100 1101 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1102 { 1103 AspeedSoCState *soc = bmc->soc; 1104 I2CSlave *therm_mux, *cpuvr_mux; 1105 1106 /* Create the generic DC-SCM hardware */ 1107 qcom_dc_scm_bmc_i2c_init(bmc); 1108 1109 /* Now create the Firework specific hardware */ 1110 1111 /* I2C7 CPUVR MUX */ 1112 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1113 "pca9546", 0x70); 1114 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1115 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1116 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1117 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1118 1119 /* I2C8 Thermal Diodes*/ 1120 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1121 "pca9548", 0x70); 1122 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1123 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1124 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1125 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1126 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1127 1128 /* I2C9 Fan Controller (MAX31785) */ 1129 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1130 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1131 } 1132 1133 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1134 { 1135 return ASPEED_MACHINE(obj)->mmio_exec; 1136 } 1137 1138 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1139 { 1140 ASPEED_MACHINE(obj)->mmio_exec = value; 1141 } 1142 1143 static void aspeed_machine_instance_init(Object *obj) 1144 { 1145 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj); 1146 1147 ASPEED_MACHINE(obj)->mmio_exec = false; 1148 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1; 1149 } 1150 1151 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1152 { 1153 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1154 return g_strdup(bmc->fmc_model); 1155 } 1156 1157 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1158 { 1159 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1160 1161 g_free(bmc->fmc_model); 1162 bmc->fmc_model = g_strdup(value); 1163 } 1164 1165 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1166 { 1167 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1168 return g_strdup(bmc->spi_model); 1169 } 1170 1171 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1172 { 1173 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1174 1175 g_free(bmc->spi_model); 1176 bmc->spi_model = g_strdup(value); 1177 } 1178 1179 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1180 { 1181 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1182 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1183 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1184 1185 return g_strdup_printf("uart%d", uart_chosen - ASPEED_DEV_UART1 + 1); 1186 } 1187 1188 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1189 { 1190 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1191 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1192 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1193 int val; 1194 1195 if (sscanf(value, "uart%u", &val) != 1) { 1196 error_setg(errp, "Bad value for \"uart\" property"); 1197 return; 1198 } 1199 1200 /* The number of UART depends on the SoC */ 1201 if (val < 1 || val > sc->uarts_num) { 1202 error_setg(errp, "\"uart\" should be in range [1 - %d]", sc->uarts_num); 1203 return; 1204 } 1205 bmc->uart_chosen = ASPEED_DEV_UART1 + val - 1; 1206 } 1207 1208 static void aspeed_machine_class_props_init(ObjectClass *oc) 1209 { 1210 object_class_property_add_bool(oc, "execute-in-place", 1211 aspeed_get_mmio_exec, 1212 aspeed_set_mmio_exec); 1213 object_class_property_set_description(oc, "execute-in-place", 1214 "boot directly from CE0 flash device"); 1215 1216 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1217 aspeed_set_bmc_console); 1218 object_class_property_set_description(oc, "bmc-console", 1219 "Change the default UART to \"uartX\""); 1220 1221 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1222 aspeed_set_fmc_model); 1223 object_class_property_set_description(oc, "fmc-model", 1224 "Change the FMC Flash model"); 1225 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1226 aspeed_set_spi_model); 1227 object_class_property_set_description(oc, "spi-model", 1228 "Change the SPI Flash model"); 1229 } 1230 1231 static int aspeed_soc_num_cpus(const char *soc_name) 1232 { 1233 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 1234 return sc->num_cpus; 1235 } 1236 1237 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1238 { 1239 MachineClass *mc = MACHINE_CLASS(oc); 1240 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1241 1242 mc->init = aspeed_machine_init; 1243 mc->no_floppy = 1; 1244 mc->no_cdrom = 1; 1245 mc->no_parallel = 1; 1246 mc->default_ram_id = "ram"; 1247 amc->macs_mask = ASPEED_MAC0_ON; 1248 amc->uart_default = ASPEED_DEV_UART5; 1249 1250 aspeed_machine_class_props_init(oc); 1251 } 1252 1253 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1254 { 1255 MachineClass *mc = MACHINE_CLASS(oc); 1256 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1257 1258 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1259 amc->soc_name = "ast2400-a1"; 1260 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1261 amc->fmc_model = "n25q256a"; 1262 amc->spi_model = "mx25l25635f"; 1263 amc->num_cs = 1; 1264 amc->i2c_init = palmetto_bmc_i2c_init; 1265 mc->default_ram_size = 256 * MiB; 1266 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1267 aspeed_soc_num_cpus(amc->soc_name); 1268 }; 1269 1270 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1271 { 1272 MachineClass *mc = MACHINE_CLASS(oc); 1273 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1274 1275 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1276 amc->soc_name = "ast2400-a1"; 1277 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1278 amc->fmc_model = "n25q256a"; 1279 amc->spi_model = "mx25l25635e"; 1280 amc->num_cs = 1; 1281 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1282 mc->default_ram_size = 128 * MiB; 1283 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1284 aspeed_soc_num_cpus(amc->soc_name); 1285 } 1286 1287 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1288 void *data) 1289 { 1290 MachineClass *mc = MACHINE_CLASS(oc); 1291 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1292 1293 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1294 amc->soc_name = "ast2400-a1"; 1295 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1296 amc->fmc_model = "mx25l25635e"; 1297 amc->spi_model = "mx25l25635e"; 1298 amc->num_cs = 1; 1299 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1300 amc->i2c_init = palmetto_bmc_i2c_init; 1301 mc->default_ram_size = 256 * MiB; 1302 } 1303 1304 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1305 void *data) 1306 { 1307 MachineClass *mc = MACHINE_CLASS(oc); 1308 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1309 1310 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1311 amc->soc_name = "ast2500-a1"; 1312 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1313 amc->fmc_model = "mx25l25635e"; 1314 amc->spi_model = "mx25l25635e"; 1315 amc->num_cs = 1; 1316 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1317 amc->i2c_init = palmetto_bmc_i2c_init; 1318 mc->default_ram_size = 512 * MiB; 1319 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1320 aspeed_soc_num_cpus(amc->soc_name); 1321 } 1322 1323 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1324 { 1325 MachineClass *mc = MACHINE_CLASS(oc); 1326 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1327 1328 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1329 amc->soc_name = "ast2500-a1"; 1330 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1331 amc->fmc_model = "mx25l25635e"; 1332 amc->spi_model = "mx25l25635f"; 1333 amc->num_cs = 1; 1334 amc->i2c_init = ast2500_evb_i2c_init; 1335 mc->default_ram_size = 512 * MiB; 1336 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1337 aspeed_soc_num_cpus(amc->soc_name); 1338 }; 1339 1340 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data) 1341 { 1342 MachineClass *mc = MACHINE_CLASS(oc); 1343 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1344 1345 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1346 amc->soc_name = "ast2500-a1"; 1347 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1348 amc->hw_strap2 = 0; 1349 amc->fmc_model = "n25q256a"; 1350 amc->spi_model = "mx25l25635e"; 1351 amc->num_cs = 2; 1352 amc->i2c_init = yosemitev2_bmc_i2c_init; 1353 mc->default_ram_size = 512 * MiB; 1354 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1355 aspeed_soc_num_cpus(amc->soc_name); 1356 }; 1357 1358 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1359 { 1360 MachineClass *mc = MACHINE_CLASS(oc); 1361 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1362 1363 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1364 amc->soc_name = "ast2500-a1"; 1365 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1366 amc->fmc_model = "n25q256a"; 1367 amc->spi_model = "mx66l1g45g"; 1368 amc->num_cs = 2; 1369 amc->i2c_init = romulus_bmc_i2c_init; 1370 mc->default_ram_size = 512 * MiB; 1371 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1372 aspeed_soc_num_cpus(amc->soc_name); 1373 }; 1374 1375 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data) 1376 { 1377 MachineClass *mc = MACHINE_CLASS(oc); 1378 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1379 1380 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1381 amc->soc_name = "ast2500-a1"; 1382 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1383 amc->hw_strap2 = 0; 1384 amc->fmc_model = "n25q256a"; 1385 amc->spi_model = "mx25l25635e"; 1386 amc->num_cs = 2; 1387 amc->i2c_init = tiogapass_bmc_i2c_init; 1388 mc->default_ram_size = 1 * GiB; 1389 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1390 aspeed_soc_num_cpus(amc->soc_name); 1391 aspeed_soc_num_cpus(amc->soc_name); 1392 }; 1393 1394 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1395 { 1396 MachineClass *mc = MACHINE_CLASS(oc); 1397 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1398 1399 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1400 amc->soc_name = "ast2500-a1"; 1401 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1402 amc->fmc_model = "mx66l1g45g"; 1403 amc->spi_model = "mx66l1g45g"; 1404 amc->num_cs = 2; 1405 amc->i2c_init = sonorapass_bmc_i2c_init; 1406 mc->default_ram_size = 512 * MiB; 1407 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1408 aspeed_soc_num_cpus(amc->soc_name); 1409 }; 1410 1411 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1412 { 1413 MachineClass *mc = MACHINE_CLASS(oc); 1414 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1415 1416 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1417 amc->soc_name = "ast2500-a1"; 1418 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1419 amc->fmc_model = "mx25l25635f"; 1420 amc->spi_model = "mx66l1g45g"; 1421 amc->num_cs = 2; 1422 amc->i2c_init = witherspoon_bmc_i2c_init; 1423 mc->default_ram_size = 512 * MiB; 1424 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1425 aspeed_soc_num_cpus(amc->soc_name); 1426 }; 1427 1428 static bool aspeed_get_boot_emmc(Object *obj, Error **errp) 1429 { 1430 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1431 1432 return !!(bmc->hw_strap1 & AST26500_HW_STRAP_BOOT_SRC_EMMC); 1433 } 1434 1435 static void aspeed_set_boot_emmc(Object *obj, bool value, Error **errp) 1436 { 1437 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1438 1439 if (value) { 1440 bmc->hw_strap1 |= AST26500_HW_STRAP_BOOT_SRC_EMMC; 1441 } else { 1442 bmc->hw_strap1 &= ~AST26500_HW_STRAP_BOOT_SRC_EMMC; 1443 } 1444 } 1445 1446 static void aspeed_machine_ast2600_class_init(ObjectClass *oc, void *data) 1447 { 1448 object_class_property_add_bool(oc, "boot-emmc", aspeed_get_boot_emmc, 1449 aspeed_set_boot_emmc); 1450 object_class_property_set_description(oc, "boot-emmc", 1451 "Set or unset boot from EMMC"); 1452 } 1453 1454 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1455 { 1456 MachineClass *mc = MACHINE_CLASS(oc); 1457 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1458 1459 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1460 amc->soc_name = "ast2600-a3"; 1461 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1462 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1463 amc->fmc_model = "mx66u51235f"; 1464 amc->spi_model = "mx66u51235f"; 1465 amc->num_cs = 1; 1466 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1467 ASPEED_MAC3_ON; 1468 amc->i2c_init = ast2600_evb_i2c_init; 1469 mc->default_ram_size = 1 * GiB; 1470 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1471 aspeed_soc_num_cpus(amc->soc_name); 1472 1473 aspeed_machine_ast2600_class_init(oc, data); 1474 }; 1475 1476 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1477 { 1478 MachineClass *mc = MACHINE_CLASS(oc); 1479 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1480 1481 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1482 amc->soc_name = "ast2600-a3"; 1483 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1484 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1485 amc->fmc_model = "mx66l1g45g"; 1486 amc->spi_model = "mx66l1g45g"; 1487 amc->num_cs = 2; 1488 amc->macs_mask = ASPEED_MAC2_ON; 1489 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1490 mc->default_ram_size = 1 * GiB; 1491 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1492 aspeed_soc_num_cpus(amc->soc_name); 1493 1494 aspeed_machine_ast2600_class_init(oc, data); 1495 }; 1496 1497 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1498 { 1499 MachineClass *mc = MACHINE_CLASS(oc); 1500 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1501 1502 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1503 amc->soc_name = "ast2500-a1"; 1504 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1505 amc->fmc_model = "n25q512a"; 1506 amc->spi_model = "mx25l25635e"; 1507 amc->num_cs = 2; 1508 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1509 amc->i2c_init = g220a_bmc_i2c_init; 1510 mc->default_ram_size = 1024 * MiB; 1511 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1512 aspeed_soc_num_cpus(amc->soc_name); 1513 }; 1514 1515 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1516 { 1517 MachineClass *mc = MACHINE_CLASS(oc); 1518 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1519 1520 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1521 amc->soc_name = "ast2500-a1"; 1522 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1523 amc->fmc_model = "n25q512a"; 1524 amc->spi_model = "mx25l25635e"; 1525 amc->num_cs = 2; 1526 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1527 amc->i2c_init = fp5280g2_bmc_i2c_init; 1528 mc->default_ram_size = 512 * MiB; 1529 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1530 aspeed_soc_num_cpus(amc->soc_name); 1531 }; 1532 1533 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1534 { 1535 MachineClass *mc = MACHINE_CLASS(oc); 1536 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1537 1538 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1539 amc->soc_name = "ast2600-a3"; 1540 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1541 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1542 amc->fmc_model = "mx66l1g45g"; 1543 amc->spi_model = "mx66l1g45g"; 1544 amc->num_cs = 2; 1545 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1546 amc->i2c_init = rainier_bmc_i2c_init; 1547 mc->default_ram_size = 1 * GiB; 1548 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1549 aspeed_soc_num_cpus(amc->soc_name); 1550 1551 aspeed_machine_ast2600_class_init(oc, data); 1552 }; 1553 1554 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1555 1556 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1557 { 1558 MachineClass *mc = MACHINE_CLASS(oc); 1559 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1560 1561 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1562 amc->soc_name = "ast2600-a3"; 1563 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1564 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1565 amc->fmc_model = "mx66l1g45g"; 1566 amc->spi_model = "mx66l1g45g"; 1567 amc->num_cs = 2; 1568 amc->macs_mask = ASPEED_MAC3_ON; 1569 amc->i2c_init = fuji_bmc_i2c_init; 1570 amc->uart_default = ASPEED_DEV_UART1; 1571 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1572 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1573 aspeed_soc_num_cpus(amc->soc_name); 1574 1575 aspeed_machine_ast2600_class_init(oc, data); 1576 }; 1577 1578 #define MONTBLANC_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1579 1580 static void aspeed_machine_montblanc_class_init(ObjectClass *oc, void *data) 1581 { 1582 MachineClass *mc = MACHINE_CLASS(oc); 1583 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1584 1585 mc->desc = "Facebook Montblanc BMC (Cortex-A7)"; 1586 amc->soc_name = "ast2600-a3"; 1587 amc->hw_strap1 = MONTBLANC_BMC_HW_STRAP1; 1588 amc->hw_strap2 = MONTBLANC_BMC_HW_STRAP2; 1589 amc->fmc_model = "mx66l1g45g"; 1590 amc->spi_model = "mx66l1g45g"; 1591 amc->num_cs = 2; 1592 amc->macs_mask = ASPEED_MAC3_ON; 1593 amc->i2c_init = montblanc_bmc_i2c_init; 1594 amc->uart_default = ASPEED_DEV_UART1; 1595 mc->default_ram_size = MONTBLANC_BMC_RAM_SIZE; 1596 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1597 aspeed_soc_num_cpus(amc->soc_name); 1598 }; 1599 1600 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1601 1602 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1603 { 1604 MachineClass *mc = MACHINE_CLASS(oc); 1605 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1606 1607 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1608 amc->soc_name = "ast2600-a3"; 1609 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1610 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1611 amc->fmc_model = "w25q01jvq"; 1612 amc->spi_model = NULL; 1613 amc->num_cs = 2; 1614 amc->macs_mask = ASPEED_MAC2_ON; 1615 amc->i2c_init = bletchley_bmc_i2c_init; 1616 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1617 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1618 aspeed_soc_num_cpus(amc->soc_name); 1619 } 1620 1621 static void fby35_reset(MachineState *state, ShutdownCause reason) 1622 { 1623 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1624 AspeedGPIOState *gpio = &bmc->soc->gpio; 1625 1626 qemu_devices_reset(reason); 1627 1628 /* Board ID: 7 (Class-1, 4 slots) */ 1629 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1630 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1631 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1632 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1633 1634 /* Slot presence pins, inverse polarity. (False means present) */ 1635 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1636 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1637 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1638 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1639 1640 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1641 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1642 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1643 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1644 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1645 } 1646 1647 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) 1648 { 1649 MachineClass *mc = MACHINE_CLASS(oc); 1650 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1651 1652 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1653 mc->reset = fby35_reset; 1654 amc->fmc_model = "mx66l1g45g"; 1655 amc->num_cs = 2; 1656 amc->macs_mask = ASPEED_MAC3_ON; 1657 amc->i2c_init = fby35_i2c_init; 1658 /* FIXME: Replace this macro with something more general */ 1659 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1660 } 1661 1662 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1663 /* Main SYSCLK frequency in Hz (200MHz) */ 1664 #define SYSCLK_FRQ 200000000ULL 1665 1666 static void aspeed_minibmc_machine_init(MachineState *machine) 1667 { 1668 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1669 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1670 Clock *sysclk; 1671 1672 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1673 clock_set_hz(sysclk, SYSCLK_FRQ); 1674 1675 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 1676 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 1677 object_unref(OBJECT(bmc->soc)); 1678 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); 1679 1680 object_property_set_link(OBJECT(bmc->soc), "memory", 1681 OBJECT(get_system_memory()), &error_abort); 1682 connect_serial_hds_to_uarts(bmc); 1683 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 1684 1685 aspeed_board_init_flashes(&bmc->soc->fmc, 1686 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1687 amc->num_cs, 1688 0); 1689 1690 aspeed_board_init_flashes(&bmc->soc->spi[0], 1691 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1692 amc->num_cs, amc->num_cs); 1693 1694 aspeed_board_init_flashes(&bmc->soc->spi[1], 1695 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1696 amc->num_cs, (amc->num_cs * 2)); 1697 1698 if (amc->i2c_init) { 1699 amc->i2c_init(bmc); 1700 } 1701 1702 armv7m_load_kernel(ARM_CPU(first_cpu), 1703 machine->kernel_filename, 1704 0, 1705 AST1030_INTERNAL_FLASH_SIZE); 1706 } 1707 1708 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1709 { 1710 AspeedSoCState *soc = bmc->soc; 1711 1712 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1713 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1714 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1715 1716 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1717 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1718 } 1719 1720 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1721 void *data) 1722 { 1723 MachineClass *mc = MACHINE_CLASS(oc); 1724 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1725 1726 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1727 amc->soc_name = "ast1030-a1"; 1728 amc->hw_strap1 = 0; 1729 amc->hw_strap2 = 0; 1730 mc->init = aspeed_minibmc_machine_init; 1731 amc->i2c_init = ast1030_evb_i2c_init; 1732 mc->default_ram_size = 0; 1733 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1; 1734 amc->fmc_model = "sst25vf032b"; 1735 amc->spi_model = "sst25vf032b"; 1736 amc->num_cs = 2; 1737 amc->macs_mask = 0; 1738 } 1739 1740 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1741 void *data) 1742 { 1743 MachineClass *mc = MACHINE_CLASS(oc); 1744 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1745 1746 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1747 amc->soc_name = "ast2600-a3"; 1748 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1749 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1750 amc->fmc_model = "n25q512a"; 1751 amc->spi_model = "n25q512a"; 1752 amc->num_cs = 2; 1753 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1754 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1755 mc->default_ram_size = 1 * GiB; 1756 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1757 aspeed_soc_num_cpus(amc->soc_name); 1758 }; 1759 1760 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1761 void *data) 1762 { 1763 MachineClass *mc = MACHINE_CLASS(oc); 1764 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1765 1766 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1767 amc->soc_name = "ast2600-a3"; 1768 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1769 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1770 amc->fmc_model = "n25q512a"; 1771 amc->spi_model = "n25q512a"; 1772 amc->num_cs = 2; 1773 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1774 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1775 mc->default_ram_size = 1 * GiB; 1776 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1777 aspeed_soc_num_cpus(amc->soc_name); 1778 }; 1779 1780 static const TypeInfo aspeed_machine_types[] = { 1781 { 1782 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1783 .parent = TYPE_ASPEED_MACHINE, 1784 .class_init = aspeed_machine_palmetto_class_init, 1785 }, { 1786 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1787 .parent = TYPE_ASPEED_MACHINE, 1788 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1789 }, { 1790 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 1791 .parent = TYPE_ASPEED_MACHINE, 1792 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 1793 }, { 1794 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1795 .parent = TYPE_ASPEED_MACHINE, 1796 .class_init = aspeed_machine_ast2500_evb_class_init, 1797 }, { 1798 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1799 .parent = TYPE_ASPEED_MACHINE, 1800 .class_init = aspeed_machine_romulus_class_init, 1801 }, { 1802 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1803 .parent = TYPE_ASPEED_MACHINE, 1804 .class_init = aspeed_machine_sonorapass_class_init, 1805 }, { 1806 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1807 .parent = TYPE_ASPEED_MACHINE, 1808 .class_init = aspeed_machine_witherspoon_class_init, 1809 }, { 1810 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1811 .parent = TYPE_ASPEED_MACHINE, 1812 .class_init = aspeed_machine_ast2600_evb_class_init, 1813 }, { 1814 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 1815 .parent = TYPE_ASPEED_MACHINE, 1816 .class_init = aspeed_machine_yosemitev2_class_init, 1817 }, { 1818 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1819 .parent = TYPE_ASPEED_MACHINE, 1820 .class_init = aspeed_machine_tacoma_class_init, 1821 }, { 1822 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 1823 .parent = TYPE_ASPEED_MACHINE, 1824 .class_init = aspeed_machine_tiogapass_class_init, 1825 }, { 1826 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1827 .parent = TYPE_ASPEED_MACHINE, 1828 .class_init = aspeed_machine_g220a_class_init, 1829 }, { 1830 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 1831 .parent = TYPE_ASPEED_MACHINE, 1832 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 1833 }, { 1834 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 1835 .parent = TYPE_ASPEED_MACHINE, 1836 .class_init = aspeed_machine_qcom_firework_class_init, 1837 }, { 1838 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1839 .parent = TYPE_ASPEED_MACHINE, 1840 .class_init = aspeed_machine_fp5280g2_class_init, 1841 }, { 1842 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1843 .parent = TYPE_ASPEED_MACHINE, 1844 .class_init = aspeed_machine_quanta_q71l_class_init, 1845 }, { 1846 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1847 .parent = TYPE_ASPEED_MACHINE, 1848 .class_init = aspeed_machine_rainier_class_init, 1849 }, { 1850 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1851 .parent = TYPE_ASPEED_MACHINE, 1852 .class_init = aspeed_machine_fuji_class_init, 1853 }, { 1854 .name = MACHINE_TYPE_NAME("montblanc-bmc"), 1855 .parent = TYPE_ASPEED_MACHINE, 1856 .class_init = aspeed_machine_montblanc_class_init, 1857 }, { 1858 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1859 .parent = TYPE_ASPEED_MACHINE, 1860 .class_init = aspeed_machine_bletchley_class_init, 1861 }, { 1862 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1863 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1864 .class_init = aspeed_machine_fby35_class_init, 1865 }, { 1866 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1867 .parent = TYPE_ASPEED_MACHINE, 1868 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1869 }, { 1870 .name = TYPE_ASPEED_MACHINE, 1871 .parent = TYPE_MACHINE, 1872 .instance_size = sizeof(AspeedMachineState), 1873 .instance_init = aspeed_machine_instance_init, 1874 .class_size = sizeof(AspeedMachineClass), 1875 .class_init = aspeed_machine_class_init, 1876 .abstract = true, 1877 } 1878 }; 1879 1880 DEFINE_TYPES(aspeed_machine_types) 1881