1 /* 2 * ARMV7M System emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/arm/armv7m.h" 12 #include "qapi/error.h" 13 #include "cpu.h" 14 #include "hw/sysbus.h" 15 #include "hw/arm/boot.h" 16 #include "hw/loader.h" 17 #include "elf.h" 18 #include "sysemu/qtest.h" 19 #include "qemu/error-report.h" 20 #include "qemu/module.h" 21 #include "exec/address-spaces.h" 22 #include "target/arm/idau.h" 23 24 /* Bitbanded IO. Each word corresponds to a single bit. */ 25 26 /* Get the byte address of the real memory for a bitband access. */ 27 static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset) 28 { 29 return s->base | (offset & 0x1ffffff) >> 5; 30 } 31 32 static MemTxResult bitband_read(void *opaque, hwaddr offset, 33 uint64_t *data, unsigned size, MemTxAttrs attrs) 34 { 35 BitBandState *s = opaque; 36 uint8_t buf[4]; 37 MemTxResult res; 38 int bitpos, bit; 39 hwaddr addr; 40 41 assert(size <= 4); 42 43 /* Find address in underlying memory and round down to multiple of size */ 44 addr = bitband_addr(s, offset) & (-size); 45 res = address_space_read(&s->source_as, addr, attrs, buf, size); 46 if (res) { 47 return res; 48 } 49 /* Bit position in the N bytes read... */ 50 bitpos = (offset >> 2) & ((size * 8) - 1); 51 /* ...converted to byte in buffer and bit in byte */ 52 bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1; 53 *data = bit; 54 return MEMTX_OK; 55 } 56 57 static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value, 58 unsigned size, MemTxAttrs attrs) 59 { 60 BitBandState *s = opaque; 61 uint8_t buf[4]; 62 MemTxResult res; 63 int bitpos, bit; 64 hwaddr addr; 65 66 assert(size <= 4); 67 68 /* Find address in underlying memory and round down to multiple of size */ 69 addr = bitband_addr(s, offset) & (-size); 70 res = address_space_read(&s->source_as, addr, attrs, buf, size); 71 if (res) { 72 return res; 73 } 74 /* Bit position in the N bytes read... */ 75 bitpos = (offset >> 2) & ((size * 8) - 1); 76 /* ...converted to byte in buffer and bit in byte */ 77 bit = 1 << (bitpos & 7); 78 if (value & 1) { 79 buf[bitpos >> 3] |= bit; 80 } else { 81 buf[bitpos >> 3] &= ~bit; 82 } 83 return address_space_write(&s->source_as, addr, attrs, buf, size); 84 } 85 86 static const MemoryRegionOps bitband_ops = { 87 .read_with_attrs = bitband_read, 88 .write_with_attrs = bitband_write, 89 .endianness = DEVICE_NATIVE_ENDIAN, 90 .impl.min_access_size = 1, 91 .impl.max_access_size = 4, 92 .valid.min_access_size = 1, 93 .valid.max_access_size = 4, 94 }; 95 96 static void bitband_init(Object *obj) 97 { 98 BitBandState *s = BITBAND(obj); 99 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 100 101 memory_region_init_io(&s->iomem, obj, &bitband_ops, s, 102 "bitband", 0x02000000); 103 sysbus_init_mmio(dev, &s->iomem); 104 } 105 106 static void bitband_realize(DeviceState *dev, Error **errp) 107 { 108 BitBandState *s = BITBAND(dev); 109 110 if (!s->source_memory) { 111 error_setg(errp, "source-memory property not set"); 112 return; 113 } 114 115 address_space_init(&s->source_as, s->source_memory, "bitband-source"); 116 } 117 118 /* Board init. */ 119 120 static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = { 121 0x20000000, 0x40000000 122 }; 123 124 static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = { 125 0x22000000, 0x42000000 126 }; 127 128 static void armv7m_instance_init(Object *obj) 129 { 130 ARMv7MState *s = ARMV7M(obj); 131 int i; 132 133 /* Can't init the cpu here, we don't yet know which model to use */ 134 135 memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX); 136 137 sysbus_init_child_obj(obj, "nvnic", &s->nvic, sizeof(s->nvic), TYPE_NVIC); 138 object_property_add_alias(obj, "num-irq", 139 OBJECT(&s->nvic), "num-irq", &error_abort); 140 141 for (i = 0; i < ARRAY_SIZE(s->bitband); i++) { 142 sysbus_init_child_obj(obj, "bitband[*]", &s->bitband[i], 143 sizeof(s->bitband[i]), TYPE_BITBAND); 144 } 145 } 146 147 static void armv7m_realize(DeviceState *dev, Error **errp) 148 { 149 ARMv7MState *s = ARMV7M(dev); 150 SysBusDevice *sbd; 151 Error *err = NULL; 152 int i; 153 154 if (!s->board_memory) { 155 error_setg(errp, "memory property was not set"); 156 return; 157 } 158 159 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); 160 161 s->cpu = ARM_CPU(object_new_with_props(s->cpu_type, OBJECT(s), "cpu", 162 &err, NULL)); 163 if (err != NULL) { 164 error_propagate(errp, err); 165 return; 166 } 167 168 object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory", 169 &error_abort); 170 if (object_property_find(OBJECT(s->cpu), "idau", NULL)) { 171 object_property_set_link(OBJECT(s->cpu), s->idau, "idau", &err); 172 if (err != NULL) { 173 error_propagate(errp, err); 174 return; 175 } 176 } 177 if (object_property_find(OBJECT(s->cpu), "init-svtor", NULL)) { 178 object_property_set_uint(OBJECT(s->cpu), s->init_svtor, 179 "init-svtor", &err); 180 if (err != NULL) { 181 error_propagate(errp, err); 182 return; 183 } 184 } 185 if (object_property_find(OBJECT(s->cpu), "start-powered-off", NULL)) { 186 object_property_set_bool(OBJECT(s->cpu), s->start_powered_off, 187 "start-powered-off", &err); 188 if (err != NULL) { 189 error_propagate(errp, err); 190 return; 191 } 192 } 193 if (object_property_find(OBJECT(s->cpu), "vfp", NULL)) { 194 object_property_set_bool(OBJECT(s->cpu), s->vfp, 195 "vfp", &err); 196 if (err != NULL) { 197 error_propagate(errp, err); 198 return; 199 } 200 } 201 if (object_property_find(OBJECT(s->cpu), "dsp", NULL)) { 202 object_property_set_bool(OBJECT(s->cpu), s->dsp, 203 "dsp", &err); 204 if (err != NULL) { 205 error_propagate(errp, err); 206 return; 207 } 208 } 209 210 /* 211 * Tell the CPU where the NVIC is; it will fail realize if it doesn't 212 * have one. Similarly, tell the NVIC where its CPU is. 213 */ 214 s->cpu->env.nvic = &s->nvic; 215 s->nvic.cpu = s->cpu; 216 217 object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); 218 if (err != NULL) { 219 error_propagate(errp, err); 220 return; 221 } 222 223 /* Note that we must realize the NVIC after the CPU */ 224 object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err); 225 if (err != NULL) { 226 error_propagate(errp, err); 227 return; 228 } 229 230 /* Alias the NVIC's input and output GPIOs as our own so the board 231 * code can wire them up. (We do this in realize because the 232 * NVIC doesn't create the input GPIO array until realize.) 233 */ 234 qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL); 235 qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ"); 236 qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI"); 237 238 /* Wire the NVIC up to the CPU */ 239 sbd = SYS_BUS_DEVICE(&s->nvic); 240 sysbus_connect_irq(sbd, 0, 241 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); 242 243 memory_region_add_subregion(&s->container, 0xe000e000, 244 sysbus_mmio_get_region(sbd, 0)); 245 246 if (s->enable_bitband) { 247 for (i = 0; i < ARRAY_SIZE(s->bitband); i++) { 248 Object *obj = OBJECT(&s->bitband[i]); 249 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]); 250 251 object_property_set_int(obj, bitband_input_addr[i], "base", &err); 252 if (err != NULL) { 253 error_propagate(errp, err); 254 return; 255 } 256 object_property_set_link(obj, OBJECT(s->board_memory), 257 "source-memory", &error_abort); 258 object_property_set_bool(obj, true, "realized", &err); 259 if (err != NULL) { 260 error_propagate(errp, err); 261 return; 262 } 263 264 memory_region_add_subregion(&s->container, bitband_output_addr[i], 265 sysbus_mmio_get_region(sbd, 0)); 266 } 267 } 268 } 269 270 static Property armv7m_properties[] = { 271 DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type), 272 DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, 273 MemoryRegion *), 274 DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *), 275 DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0), 276 DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false), 277 DEFINE_PROP_BOOL("start-powered-off", ARMv7MState, start_powered_off, 278 false), 279 DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true), 280 DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true), 281 DEFINE_PROP_END_OF_LIST(), 282 }; 283 284 static void armv7m_class_init(ObjectClass *klass, void *data) 285 { 286 DeviceClass *dc = DEVICE_CLASS(klass); 287 288 dc->realize = armv7m_realize; 289 dc->props = armv7m_properties; 290 } 291 292 static const TypeInfo armv7m_info = { 293 .name = TYPE_ARMV7M, 294 .parent = TYPE_SYS_BUS_DEVICE, 295 .instance_size = sizeof(ARMv7MState), 296 .instance_init = armv7m_instance_init, 297 .class_init = armv7m_class_init, 298 }; 299 300 static void armv7m_reset(void *opaque) 301 { 302 ARMCPU *cpu = opaque; 303 304 cpu_reset(CPU(cpu)); 305 } 306 307 void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) 308 { 309 int image_size; 310 uint64_t entry; 311 uint64_t lowaddr; 312 int big_endian; 313 AddressSpace *as; 314 int asidx; 315 CPUState *cs = CPU(cpu); 316 317 #ifdef TARGET_WORDS_BIGENDIAN 318 big_endian = 1; 319 #else 320 big_endian = 0; 321 #endif 322 323 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 324 asidx = ARMASIdx_S; 325 } else { 326 asidx = ARMASIdx_NS; 327 } 328 as = cpu_get_address_space(cs, asidx); 329 330 if (kernel_filename) { 331 image_size = load_elf_as(kernel_filename, NULL, NULL, NULL, 332 &entry, &lowaddr, 333 NULL, big_endian, EM_ARM, 1, 0, as); 334 if (image_size < 0) { 335 image_size = load_image_targphys_as(kernel_filename, 0, 336 mem_size, as); 337 lowaddr = 0; 338 } 339 if (image_size < 0) { 340 error_report("Could not load kernel '%s'", kernel_filename); 341 exit(1); 342 } 343 } 344 345 /* CPU objects (unlike devices) are not automatically reset on system 346 * reset, so we must always register a handler to do so. Unlike 347 * A-profile CPUs, we don't need to do anything special in the 348 * handler to arrange that it starts correctly. 349 * This is arguably the wrong place to do this, but it matches the 350 * way A-profile does it. Note that this means that every M profile 351 * board must call this function! 352 */ 353 qemu_register_reset(armv7m_reset, cpu); 354 } 355 356 static Property bitband_properties[] = { 357 DEFINE_PROP_UINT32("base", BitBandState, base, 0), 358 DEFINE_PROP_LINK("source-memory", BitBandState, source_memory, 359 TYPE_MEMORY_REGION, MemoryRegion *), 360 DEFINE_PROP_END_OF_LIST(), 361 }; 362 363 static void bitband_class_init(ObjectClass *klass, void *data) 364 { 365 DeviceClass *dc = DEVICE_CLASS(klass); 366 367 dc->realize = bitband_realize; 368 dc->props = bitband_properties; 369 } 370 371 static const TypeInfo bitband_info = { 372 .name = TYPE_BITBAND, 373 .parent = TYPE_SYS_BUS_DEVICE, 374 .instance_size = sizeof(BitBandState), 375 .instance_init = bitband_init, 376 .class_init = bitband_class_init, 377 }; 378 379 static void armv7m_register_types(void) 380 { 381 type_register_static(&bitband_info); 382 type_register_static(&armv7m_info); 383 } 384 385 type_init(armv7m_register_types) 386