1 /* 2 * ARMV7M System emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/arm/armv7m.h" 12 #include "qapi/error.h" 13 #include "hw/sysbus.h" 14 #include "hw/arm/boot.h" 15 #include "hw/loader.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/qdev-clock.h" 18 #include "elf.h" 19 #include "sysemu/reset.h" 20 #include "qemu/error-report.h" 21 #include "qemu/module.h" 22 #include "qemu/log.h" 23 #include "target/arm/idau.h" 24 #include "target/arm/cpu-features.h" 25 #include "migration/vmstate.h" 26 27 /* Bitbanded IO. Each word corresponds to a single bit. */ 28 29 /* Get the byte address of the real memory for a bitband access. */ 30 static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset) 31 { 32 return s->base | (offset & 0x1ffffff) >> 5; 33 } 34 35 static MemTxResult bitband_read(void *opaque, hwaddr offset, 36 uint64_t *data, unsigned size, MemTxAttrs attrs) 37 { 38 BitBandState *s = opaque; 39 uint8_t buf[4]; 40 MemTxResult res; 41 int bitpos, bit; 42 hwaddr addr; 43 44 assert(size <= 4); 45 46 /* Find address in underlying memory and round down to multiple of size */ 47 addr = bitband_addr(s, offset) & (-size); 48 res = address_space_read(&s->source_as, addr, attrs, buf, size); 49 if (res) { 50 return res; 51 } 52 /* Bit position in the N bytes read... */ 53 bitpos = (offset >> 2) & ((size * 8) - 1); 54 /* ...converted to byte in buffer and bit in byte */ 55 bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1; 56 *data = bit; 57 return MEMTX_OK; 58 } 59 60 static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value, 61 unsigned size, MemTxAttrs attrs) 62 { 63 BitBandState *s = opaque; 64 uint8_t buf[4]; 65 MemTxResult res; 66 int bitpos, bit; 67 hwaddr addr; 68 69 assert(size <= 4); 70 71 /* Find address in underlying memory and round down to multiple of size */ 72 addr = bitband_addr(s, offset) & (-size); 73 res = address_space_read(&s->source_as, addr, attrs, buf, size); 74 if (res) { 75 return res; 76 } 77 /* Bit position in the N bytes read... */ 78 bitpos = (offset >> 2) & ((size * 8) - 1); 79 /* ...converted to byte in buffer and bit in byte */ 80 bit = 1 << (bitpos & 7); 81 if (value & 1) { 82 buf[bitpos >> 3] |= bit; 83 } else { 84 buf[bitpos >> 3] &= ~bit; 85 } 86 return address_space_write(&s->source_as, addr, attrs, buf, size); 87 } 88 89 static const MemoryRegionOps bitband_ops = { 90 .read_with_attrs = bitband_read, 91 .write_with_attrs = bitband_write, 92 .endianness = DEVICE_NATIVE_ENDIAN, 93 .impl.min_access_size = 1, 94 .impl.max_access_size = 4, 95 .valid.min_access_size = 1, 96 .valid.max_access_size = 4, 97 }; 98 99 static void bitband_init(Object *obj) 100 { 101 BitBandState *s = BITBAND(obj); 102 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 103 104 memory_region_init_io(&s->iomem, obj, &bitband_ops, s, 105 "bitband", 0x02000000); 106 sysbus_init_mmio(dev, &s->iomem); 107 } 108 109 static void bitband_realize(DeviceState *dev, Error **errp) 110 { 111 BitBandState *s = BITBAND(dev); 112 113 if (!s->source_memory) { 114 error_setg(errp, "source-memory property not set"); 115 return; 116 } 117 118 address_space_init(&s->source_as, s->source_memory, "bitband-source"); 119 } 120 121 /* Board init. */ 122 123 static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = { 124 0x20000000, 0x40000000 125 }; 126 127 static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = { 128 0x22000000, 0x42000000 129 }; 130 131 static MemTxResult v7m_sysreg_ns_write(void *opaque, hwaddr addr, 132 uint64_t value, unsigned size, 133 MemTxAttrs attrs) 134 { 135 MemoryRegion *mr = opaque; 136 137 if (attrs.secure) { 138 /* S accesses to the alias act like NS accesses to the real region */ 139 attrs.secure = 0; 140 return memory_region_dispatch_write(mr, addr, value, 141 size_memop(size) | MO_TE, attrs); 142 } else { 143 /* NS attrs are RAZ/WI for privileged, and BusFault for user */ 144 if (attrs.user) { 145 return MEMTX_ERROR; 146 } 147 return MEMTX_OK; 148 } 149 } 150 151 static MemTxResult v7m_sysreg_ns_read(void *opaque, hwaddr addr, 152 uint64_t *data, unsigned size, 153 MemTxAttrs attrs) 154 { 155 MemoryRegion *mr = opaque; 156 157 if (attrs.secure) { 158 /* S accesses to the alias act like NS accesses to the real region */ 159 attrs.secure = 0; 160 return memory_region_dispatch_read(mr, addr, data, 161 size_memop(size) | MO_TE, attrs); 162 } else { 163 /* NS attrs are RAZ/WI for privileged, and BusFault for user */ 164 if (attrs.user) { 165 return MEMTX_ERROR; 166 } 167 *data = 0; 168 return MEMTX_OK; 169 } 170 } 171 172 static const MemoryRegionOps v7m_sysreg_ns_ops = { 173 .read_with_attrs = v7m_sysreg_ns_read, 174 .write_with_attrs = v7m_sysreg_ns_write, 175 .endianness = DEVICE_NATIVE_ENDIAN, 176 }; 177 178 static MemTxResult v7m_systick_write(void *opaque, hwaddr addr, 179 uint64_t value, unsigned size, 180 MemTxAttrs attrs) 181 { 182 ARMv7MState *s = opaque; 183 MemoryRegion *mr; 184 185 /* Direct the access to the correct systick */ 186 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); 187 return memory_region_dispatch_write(mr, addr, value, 188 size_memop(size) | MO_TE, attrs); 189 } 190 191 static MemTxResult v7m_systick_read(void *opaque, hwaddr addr, 192 uint64_t *data, unsigned size, 193 MemTxAttrs attrs) 194 { 195 ARMv7MState *s = opaque; 196 MemoryRegion *mr; 197 198 /* Direct the access to the correct systick */ 199 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); 200 return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE, 201 attrs); 202 } 203 204 static const MemoryRegionOps v7m_systick_ops = { 205 .read_with_attrs = v7m_systick_read, 206 .write_with_attrs = v7m_systick_write, 207 .endianness = DEVICE_NATIVE_ENDIAN, 208 }; 209 210 /* 211 * Unassigned portions of the PPB space are RAZ/WI for privileged 212 * accesses, and fault for non-privileged accesses. 213 */ 214 static MemTxResult ppb_default_read(void *opaque, hwaddr addr, 215 uint64_t *data, unsigned size, 216 MemTxAttrs attrs) 217 { 218 qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n", 219 (uint32_t)addr); 220 if (attrs.user) { 221 return MEMTX_ERROR; 222 } 223 *data = 0; 224 return MEMTX_OK; 225 } 226 227 static MemTxResult ppb_default_write(void *opaque, hwaddr addr, 228 uint64_t value, unsigned size, 229 MemTxAttrs attrs) 230 { 231 qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x\n", 232 (uint32_t)addr); 233 if (attrs.user) { 234 return MEMTX_ERROR; 235 } 236 return MEMTX_OK; 237 } 238 239 static const MemoryRegionOps ppb_default_ops = { 240 .read_with_attrs = ppb_default_read, 241 .write_with_attrs = ppb_default_write, 242 .endianness = DEVICE_NATIVE_ENDIAN, 243 .valid.min_access_size = 1, 244 .valid.max_access_size = 8, 245 }; 246 247 static void armv7m_instance_init(Object *obj) 248 { 249 ARMv7MState *s = ARMV7M(obj); 250 int i; 251 252 /* Can't init the cpu here, we don't yet know which model to use */ 253 254 memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX); 255 256 object_initialize_child(obj, "nvic", &s->nvic, TYPE_NVIC); 257 object_property_add_alias(obj, "num-irq", 258 OBJECT(&s->nvic), "num-irq"); 259 260 object_initialize_child(obj, "systick-reg-ns", &s->systick[M_REG_NS], 261 TYPE_SYSTICK); 262 /* 263 * We can't initialize the secure systick here, as we don't know 264 * yet if we need it. 265 */ 266 267 for (i = 0; i < ARRAY_SIZE(s->bitband); i++) { 268 object_initialize_child(obj, "bitband[*]", &s->bitband[i], 269 TYPE_BITBAND); 270 } 271 272 s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); 273 s->cpuclk = qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0); 274 } 275 276 static void armv7m_realize(DeviceState *dev, Error **errp) 277 { 278 ARMv7MState *s = ARMV7M(dev); 279 SysBusDevice *sbd; 280 Error *err = NULL; 281 int i; 282 283 if (!s->board_memory) { 284 error_setg(errp, "memory property was not set"); 285 return; 286 } 287 288 /* cpuclk must be connected; refclk is optional */ 289 if (!clock_has_source(s->cpuclk)) { 290 error_setg(errp, "armv7m: cpuclk must be connected"); 291 return; 292 } 293 294 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); 295 296 s->cpu = ARM_CPU(object_new_with_props(s->cpu_type, OBJECT(s), "cpu", 297 &err, NULL)); 298 if (err != NULL) { 299 error_propagate(errp, err); 300 return; 301 } 302 303 object_property_set_link(OBJECT(s->cpu), "memory", OBJECT(&s->container), 304 &error_abort); 305 if (object_property_find(OBJECT(s->cpu), "idau")) { 306 object_property_set_link(OBJECT(s->cpu), "idau", s->idau, 307 &error_abort); 308 } 309 if (object_property_find(OBJECT(s->cpu), "init-svtor")) { 310 if (!object_property_set_uint(OBJECT(s->cpu), "init-svtor", 311 s->init_svtor, errp)) { 312 return; 313 } 314 } 315 if (object_property_find(OBJECT(s->cpu), "init-nsvtor")) { 316 if (!object_property_set_uint(OBJECT(s->cpu), "init-nsvtor", 317 s->init_nsvtor, errp)) { 318 return; 319 } 320 } 321 if (object_property_find(OBJECT(s->cpu), "vfp")) { 322 if (!object_property_set_bool(OBJECT(s->cpu), "vfp", s->vfp, errp)) { 323 return; 324 } 325 } 326 if (object_property_find(OBJECT(s->cpu), "dsp")) { 327 if (!object_property_set_bool(OBJECT(s->cpu), "dsp", s->dsp, errp)) { 328 return; 329 } 330 } 331 object_property_set_bool(OBJECT(s->cpu), "start-powered-off", 332 s->start_powered_off, &error_abort); 333 334 /* 335 * Real M-profile hardware can be configured with a different number of 336 * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't 337 * support that yet, so catch attempts to select that. 338 */ 339 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && 340 s->mpu_ns_regions != s->mpu_s_regions) { 341 error_setg(errp, 342 "mpu-ns-regions and mpu-s-regions properties must have the same value"); 343 return; 344 } 345 if (s->mpu_ns_regions != UINT_MAX && 346 object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) { 347 if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion", 348 s->mpu_ns_regions, errp)) { 349 return; 350 } 351 } 352 353 /* 354 * Tell the CPU where the NVIC is; it will fail realize if it doesn't 355 * have one. Similarly, tell the NVIC where its CPU is. 356 */ 357 s->cpu->env.nvic = &s->nvic; 358 s->nvic.cpu = s->cpu; 359 360 if (!qdev_realize(DEVICE(s->cpu), NULL, errp)) { 361 return; 362 } 363 364 /* Note that we must realize the NVIC after the CPU */ 365 if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvic), errp)) { 366 return; 367 } 368 369 /* Alias the NVIC's input and output GPIOs as our own so the board 370 * code can wire them up. (We do this in realize because the 371 * NVIC doesn't create the input GPIO array until realize.) 372 */ 373 qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL); 374 qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ"); 375 qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI"); 376 377 /* 378 * We map various devices into the container MR at their architected 379 * addresses. In particular, we map everything corresponding to the 380 * "System PPB" space. This is the range from 0xe0000000 to 0xe00fffff 381 * and includes the NVIC, the System Control Space (system registers), 382 * the systick timer, and for CPUs with the Security extension an NS 383 * banked version of all of these. 384 * 385 * The default behaviour for unimplemented registers/ranges 386 * (for instance the Data Watchpoint and Trace unit at 0xe0001000) 387 * is to RAZ/WI for privileged access and BusFault for non-privileged 388 * access. 389 * 390 * The NVIC and System Control Space (SCS) starts at 0xe000e000 391 * and looks like this: 392 * 0x004 - ICTR 393 * 0x010 - 0xff - systick 394 * 0x100..0x7ec - NVIC 395 * 0x7f0..0xcff - Reserved 396 * 0xd00..0xd3c - SCS registers 397 * 0xd40..0xeff - Reserved or Not implemented 398 * 0xf00 - STIR 399 * 400 * Some registers within this space are banked between security states. 401 * In v8M there is a second range 0xe002e000..0xe002efff which is the 402 * NonSecure alias SCS; secure accesses to this behave like NS accesses 403 * to the main SCS range, and non-secure accesses (including when 404 * the security extension is not implemented) are RAZ/WI. 405 * Note that both the main SCS range and the alias range are defined 406 * to be exempt from memory attribution (R_BLJT) and so the memory 407 * transaction attribute always matches the current CPU security 408 * state (attrs.secure == env->v7m.secure). In the v7m_sysreg_ns_ops 409 * wrappers we change attrs.secure to indicate the NS access; so 410 * generally code determining which banked register to use should 411 * use attrs.secure; code determining actual behaviour of the system 412 * should use env->v7m.secure. 413 * 414 * Within the PPB space, some MRs overlap, and the priority 415 * of overlapping regions is: 416 * - default region (for RAZ/WI and BusFault) : -1 417 * - system register regions (provided by the NVIC) : 0 418 * - systick : 1 419 * This is because the systick device is a small block of registers 420 * in the middle of the other system control registers. 421 */ 422 423 memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s, 424 "nvic-default", 0x100000); 425 memory_region_add_subregion_overlap(&s->container, 0xe0000000, 426 &s->defaultmem, -1); 427 428 /* Wire the NVIC up to the CPU */ 429 sbd = SYS_BUS_DEVICE(&s->nvic); 430 sysbus_connect_irq(sbd, 0, 431 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); 432 433 memory_region_add_subregion(&s->container, 0xe000e000, 434 sysbus_mmio_get_region(sbd, 0)); 435 if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { 436 /* Create the NS alias region for the NVIC sysregs */ 437 memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), 438 &v7m_sysreg_ns_ops, 439 sysbus_mmio_get_region(sbd, 0), 440 "nvic_sysregs_ns", 0x1000); 441 memory_region_add_subregion(&s->container, 0xe002e000, 442 &s->sysreg_ns_mem); 443 } 444 445 /* 446 * Create and map the systick devices. Note that we only connect 447 * refclk if it has been connected to us; otherwise the systick 448 * device gets the wrong answer for clock_has_source(refclk), because 449 * it has an immediate source (the ARMv7M's clock object) but not 450 * an ultimate source, and then it won't correctly auto-select the 451 * CPU clock as its only possible clock source. 452 */ 453 if (clock_has_source(s->refclk)) { 454 qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "refclk", 455 s->refclk); 456 } 457 qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "cpuclk", s->cpuclk); 458 if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) { 459 return; 460 } 461 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0, 462 qdev_get_gpio_in_named(DEVICE(&s->nvic), 463 "systick-trigger", M_REG_NS)); 464 465 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { 466 /* 467 * We couldn't init the secure systick device in instance_init 468 * as we didn't know then if the CPU had the security extensions; 469 * so we have to do it here. 470 */ 471 object_initialize_child(OBJECT(dev), "systick-reg-s", 472 &s->systick[M_REG_S], TYPE_SYSTICK); 473 if (clock_has_source(s->refclk)) { 474 qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "refclk", 475 s->refclk); 476 } 477 qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "cpuclk", 478 s->cpuclk); 479 480 if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) { 481 return; 482 } 483 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0, 484 qdev_get_gpio_in_named(DEVICE(&s->nvic), 485 "systick-trigger", M_REG_S)); 486 } 487 488 memory_region_init_io(&s->systickmem, OBJECT(s), 489 &v7m_systick_ops, s, 490 "v7m_systick", 0xe0); 491 492 memory_region_add_subregion_overlap(&s->container, 0xe000e010, 493 &s->systickmem, 1); 494 if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { 495 memory_region_init_io(&s->systick_ns_mem, OBJECT(s), 496 &v7m_sysreg_ns_ops, &s->systickmem, 497 "v7m_systick_ns", 0xe0); 498 memory_region_add_subregion_overlap(&s->container, 0xe002e010, 499 &s->systick_ns_mem, 1); 500 } 501 502 /* If the CPU has RAS support, create the RAS register block */ 503 if (cpu_isar_feature(aa32_ras, s->cpu)) { 504 object_initialize_child(OBJECT(dev), "armv7m-ras", 505 &s->ras, TYPE_ARMV7M_RAS); 506 sbd = SYS_BUS_DEVICE(&s->ras); 507 if (!sysbus_realize(sbd, errp)) { 508 return; 509 } 510 memory_region_add_subregion_overlap(&s->container, 0xe0005000, 511 sysbus_mmio_get_region(sbd, 0), 1); 512 } 513 514 for (i = 0; i < ARRAY_SIZE(s->bitband); i++) { 515 if (s->enable_bitband) { 516 Object *obj = OBJECT(&s->bitband[i]); 517 sbd = SYS_BUS_DEVICE(&s->bitband[i]); 518 519 if (!object_property_set_int(obj, "base", 520 bitband_input_addr[i], errp)) { 521 return; 522 } 523 object_property_set_link(obj, "source-memory", 524 OBJECT(s->board_memory), &error_abort); 525 if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) { 526 return; 527 } 528 529 memory_region_add_subregion(&s->container, bitband_output_addr[i], 530 sysbus_mmio_get_region(sbd, 0)); 531 } else { 532 object_unparent(OBJECT(&s->bitband[i])); 533 } 534 } 535 } 536 537 static Property armv7m_properties[] = { 538 DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type), 539 DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, 540 MemoryRegion *), 541 DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *), 542 DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0), 543 DEFINE_PROP_UINT32("init-nsvtor", ARMv7MState, init_nsvtor, 0), 544 DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false), 545 DEFINE_PROP_BOOL("start-powered-off", ARMv7MState, start_powered_off, 546 false), 547 DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true), 548 DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true), 549 DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX), 550 DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX), 551 DEFINE_PROP_END_OF_LIST(), 552 }; 553 554 static const VMStateDescription vmstate_armv7m = { 555 .name = "armv7m", 556 .version_id = 1, 557 .minimum_version_id = 1, 558 .fields = (const VMStateField[]) { 559 VMSTATE_CLOCK(refclk, ARMv7MState), 560 VMSTATE_CLOCK(cpuclk, ARMv7MState), 561 VMSTATE_END_OF_LIST() 562 } 563 }; 564 565 static void armv7m_class_init(ObjectClass *klass, void *data) 566 { 567 DeviceClass *dc = DEVICE_CLASS(klass); 568 569 dc->realize = armv7m_realize; 570 dc->vmsd = &vmstate_armv7m; 571 device_class_set_props(dc, armv7m_properties); 572 } 573 574 static const TypeInfo armv7m_info = { 575 .name = TYPE_ARMV7M, 576 .parent = TYPE_SYS_BUS_DEVICE, 577 .instance_size = sizeof(ARMv7MState), 578 .instance_init = armv7m_instance_init, 579 .class_init = armv7m_class_init, 580 }; 581 582 static void armv7m_reset(void *opaque) 583 { 584 ARMCPU *cpu = opaque; 585 586 cpu_reset(CPU(cpu)); 587 } 588 589 void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, 590 hwaddr mem_base, int mem_size) 591 { 592 ssize_t image_size; 593 uint64_t entry; 594 AddressSpace *as; 595 int asidx; 596 CPUState *cs = CPU(cpu); 597 598 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 599 asidx = ARMASIdx_S; 600 } else { 601 asidx = ARMASIdx_NS; 602 } 603 as = cpu_get_address_space(cs, asidx); 604 605 if (kernel_filename) { 606 image_size = load_elf_as(kernel_filename, NULL, NULL, NULL, 607 &entry, NULL, NULL, 608 NULL, 0, EM_ARM, 1, 0, as); 609 if (image_size < 0) { 610 image_size = load_image_targphys_as(kernel_filename, mem_base, 611 mem_size, as); 612 } 613 if (image_size < 0) { 614 error_report("Could not load kernel '%s'", kernel_filename); 615 exit(1); 616 } 617 } 618 619 /* CPU objects (unlike devices) are not automatically reset on system 620 * reset, so we must always register a handler to do so. Unlike 621 * A-profile CPUs, we don't need to do anything special in the 622 * handler to arrange that it starts correctly. 623 * This is arguably the wrong place to do this, but it matches the 624 * way A-profile does it. Note that this means that every M profile 625 * board must call this function! 626 */ 627 qemu_register_reset(armv7m_reset, cpu); 628 } 629 630 static Property bitband_properties[] = { 631 DEFINE_PROP_UINT32("base", BitBandState, base, 0), 632 DEFINE_PROP_LINK("source-memory", BitBandState, source_memory, 633 TYPE_MEMORY_REGION, MemoryRegion *), 634 DEFINE_PROP_END_OF_LIST(), 635 }; 636 637 static void bitband_class_init(ObjectClass *klass, void *data) 638 { 639 DeviceClass *dc = DEVICE_CLASS(klass); 640 641 dc->realize = bitband_realize; 642 device_class_set_props(dc, bitband_properties); 643 } 644 645 static const TypeInfo bitband_info = { 646 .name = TYPE_BITBAND, 647 .parent = TYPE_SYS_BUS_DEVICE, 648 .instance_size = sizeof(BitBandState), 649 .instance_init = bitband_init, 650 .class_init = bitband_class_init, 651 }; 652 653 static void armv7m_register_types(void) 654 { 655 type_register_static(&bitband_info); 656 type_register_static(&armv7m_info); 657 } 658 659 type_init(armv7m_register_types) 660