1 /* 2 * Arm SSE (Subsystems for Embedded): IoTKit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qemu/bitops.h" 16 #include "qapi/error.h" 17 #include "trace.h" 18 #include "hw/sysbus.h" 19 #include "migration/vmstate.h" 20 #include "hw/registerfields.h" 21 #include "hw/arm/armsse.h" 22 #include "hw/arm/boot.h" 23 #include "hw/irq.h" 24 25 /* Format of the System Information block SYS_CONFIG register */ 26 typedef enum SysConfigFormat { 27 IoTKitFormat, 28 SSE200Format, 29 } SysConfigFormat; 30 31 struct ARMSSEInfo { 32 const char *name; 33 int sram_banks; 34 int num_cpus; 35 uint32_t sys_version; 36 uint32_t cpuwait_rst; 37 SysConfigFormat sys_config_format; 38 bool has_mhus; 39 bool has_ppus; 40 bool has_cachectrl; 41 bool has_cpusecctrl; 42 bool has_cpuid; 43 Property *props; 44 }; 45 46 static Property iotkit_properties[] = { 47 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 48 MemoryRegion *), 49 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 50 DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), 51 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 52 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 53 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), 54 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), 55 DEFINE_PROP_END_OF_LIST() 56 }; 57 58 static Property armsse_properties[] = { 59 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 60 MemoryRegion *), 61 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 62 DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), 63 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 64 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 65 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), 66 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), 67 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), 68 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), 69 DEFINE_PROP_END_OF_LIST() 70 }; 71 72 static const ARMSSEInfo armsse_variants[] = { 73 { 74 .name = TYPE_IOTKIT, 75 .sram_banks = 1, 76 .num_cpus = 1, 77 .sys_version = 0x41743, 78 .cpuwait_rst = 0, 79 .sys_config_format = IoTKitFormat, 80 .has_mhus = false, 81 .has_ppus = false, 82 .has_cachectrl = false, 83 .has_cpusecctrl = false, 84 .has_cpuid = false, 85 .props = iotkit_properties, 86 }, 87 { 88 .name = TYPE_SSE200, 89 .sram_banks = 4, 90 .num_cpus = 2, 91 .sys_version = 0x22041743, 92 .cpuwait_rst = 2, 93 .sys_config_format = SSE200Format, 94 .has_mhus = true, 95 .has_ppus = true, 96 .has_cachectrl = true, 97 .has_cpusecctrl = true, 98 .has_cpuid = true, 99 .props = armsse_properties, 100 }, 101 }; 102 103 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) 104 { 105 /* Return the SYS_CONFIG value for this SSE */ 106 uint32_t sys_config; 107 108 switch (info->sys_config_format) { 109 case IoTKitFormat: 110 sys_config = 0; 111 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 112 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); 113 break; 114 case SSE200Format: 115 sys_config = 0; 116 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 117 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 118 sys_config = deposit32(sys_config, 24, 4, 2); 119 if (info->num_cpus > 1) { 120 sys_config = deposit32(sys_config, 10, 1, 1); 121 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1); 122 sys_config = deposit32(sys_config, 28, 4, 2); 123 } 124 break; 125 default: 126 g_assert_not_reached(); 127 } 128 return sys_config; 129 } 130 131 /* Clock frequency in HZ of the 32KHz "slow clock" */ 132 #define S32KCLK (32 * 1000) 133 134 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ 135 static bool irq_is_common[32] = { 136 [0 ... 5] = true, 137 /* 6, 7: per-CPU MHU interrupts */ 138 [8 ... 12] = true, 139 /* 13: per-CPU icache interrupt */ 140 /* 14: reserved */ 141 [15 ... 20] = true, 142 /* 21: reserved */ 143 [22 ... 26] = true, 144 /* 27: reserved */ 145 /* 28, 29: per-CPU CTI interrupts */ 146 /* 30, 31: reserved */ 147 }; 148 149 /* 150 * Create an alias region in @container of @size bytes starting at @base 151 * which mirrors the memory starting at @orig. 152 */ 153 static void make_alias(ARMSSE *s, MemoryRegion *mr, MemoryRegion *container, 154 const char *name, hwaddr base, hwaddr size, hwaddr orig) 155 { 156 memory_region_init_alias(mr, NULL, name, container, orig, size); 157 /* The alias is even lower priority than unimplemented_device regions */ 158 memory_region_add_subregion_overlap(container, base, mr, -1500); 159 } 160 161 static void irq_status_forwarder(void *opaque, int n, int level) 162 { 163 qemu_irq destirq = opaque; 164 165 qemu_set_irq(destirq, level); 166 } 167 168 static void nsccfg_handler(void *opaque, int n, int level) 169 { 170 ARMSSE *s = ARM_SSE(opaque); 171 172 s->nsccfg = level; 173 } 174 175 static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) 176 { 177 /* Each of the 4 AHB and 4 APB PPCs that might be present in a 178 * system using the ARMSSE has a collection of control lines which 179 * are provided by the security controller and which we want to 180 * expose as control lines on the ARMSSE device itself, so the 181 * code using the ARMSSE can wire them up to the PPCs. 182 */ 183 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; 184 DeviceState *armssedev = DEVICE(s); 185 DeviceState *dev_secctl = DEVICE(&s->secctl); 186 DeviceState *dev_splitter = DEVICE(splitter); 187 char *name; 188 189 name = g_strdup_printf("%s_nonsec", ppcname); 190 qdev_pass_gpios(dev_secctl, armssedev, name); 191 g_free(name); 192 name = g_strdup_printf("%s_ap", ppcname); 193 qdev_pass_gpios(dev_secctl, armssedev, name); 194 g_free(name); 195 name = g_strdup_printf("%s_irq_enable", ppcname); 196 qdev_pass_gpios(dev_secctl, armssedev, name); 197 g_free(name); 198 name = g_strdup_printf("%s_irq_clear", ppcname); 199 qdev_pass_gpios(dev_secctl, armssedev, name); 200 g_free(name); 201 202 /* irq_status is a little more tricky, because we need to 203 * split it so we can send it both to the security controller 204 * and to our OR gate for the NVIC interrupt line. 205 * Connect up the splitter's outputs, and create a GPIO input 206 * which will pass the line state to the input splitter. 207 */ 208 name = g_strdup_printf("%s_irq_status", ppcname); 209 qdev_connect_gpio_out(dev_splitter, 0, 210 qdev_get_gpio_in_named(dev_secctl, 211 name, 0)); 212 qdev_connect_gpio_out(dev_splitter, 1, 213 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); 214 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); 215 qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder, 216 s->irq_status_in[ppcnum], name, 1); 217 g_free(name); 218 } 219 220 static void armsse_forward_sec_resp_cfg(ARMSSE *s) 221 { 222 /* Forward the 3rd output from the splitter device as a 223 * named GPIO output of the armsse object. 224 */ 225 DeviceState *dev = DEVICE(s); 226 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); 227 228 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); 229 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, 230 s->sec_resp_cfg, 1); 231 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); 232 } 233 234 static void armsse_init(Object *obj) 235 { 236 ARMSSE *s = ARM_SSE(obj); 237 ARMSSEClass *asc = ARM_SSE_GET_CLASS(obj); 238 const ARMSSEInfo *info = asc->info; 239 int i; 240 241 assert(info->sram_banks <= MAX_SRAM_BANKS); 242 assert(info->num_cpus <= SSE_MAX_CPUS); 243 244 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); 245 246 for (i = 0; i < info->num_cpus; i++) { 247 /* 248 * We put each CPU in its own cluster as they are logically 249 * distinct and may be configured differently. 250 */ 251 char *name; 252 253 name = g_strdup_printf("cluster%d", i); 254 object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER); 255 qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); 256 g_free(name); 257 258 name = g_strdup_printf("armv7m%d", i); 259 object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i], 260 TYPE_ARMV7M); 261 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", 262 ARM_CPU_TYPE_NAME("cortex-m33")); 263 g_free(name); 264 name = g_strdup_printf("arm-sse-cpu-container%d", i); 265 memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); 266 g_free(name); 267 if (i > 0) { 268 name = g_strdup_printf("arm-sse-container-alias%d", i); 269 memory_region_init_alias(&s->container_alias[i - 1], obj, 270 name, &s->container, 0, UINT64_MAX); 271 g_free(name); 272 } 273 } 274 275 object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL); 276 object_initialize_child(obj, "apb-ppc0", &s->apb_ppc0, TYPE_TZ_PPC); 277 object_initialize_child(obj, "apb-ppc1", &s->apb_ppc1, TYPE_TZ_PPC); 278 for (i = 0; i < info->sram_banks; i++) { 279 char *name = g_strdup_printf("mpc%d", i); 280 object_initialize_child(obj, name, &s->mpc[i], TYPE_TZ_MPC); 281 g_free(name); 282 } 283 object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate, 284 TYPE_OR_IRQ); 285 286 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 287 char *name = g_strdup_printf("mpc-irq-splitter-%d", i); 288 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 289 290 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 291 g_free(name); 292 } 293 object_initialize_child(obj, "timer0", &s->timer0, TYPE_CMSDK_APB_TIMER); 294 object_initialize_child(obj, "timer1", &s->timer1, TYPE_CMSDK_APB_TIMER); 295 object_initialize_child(obj, "s32ktimer", &s->s32ktimer, 296 TYPE_CMSDK_APB_TIMER); 297 object_initialize_child(obj, "dualtimer", &s->dualtimer, 298 TYPE_CMSDK_APB_DUALTIMER); 299 object_initialize_child(obj, "s32kwatchdog", &s->s32kwatchdog, 300 TYPE_CMSDK_APB_WATCHDOG); 301 object_initialize_child(obj, "nswatchdog", &s->nswatchdog, 302 TYPE_CMSDK_APB_WATCHDOG); 303 object_initialize_child(obj, "swatchdog", &s->swatchdog, 304 TYPE_CMSDK_APB_WATCHDOG); 305 object_initialize_child(obj, "armsse-sysctl", &s->sysctl, 306 TYPE_IOTKIT_SYSCTL); 307 object_initialize_child(obj, "armsse-sysinfo", &s->sysinfo, 308 TYPE_IOTKIT_SYSINFO); 309 if (info->has_mhus) { 310 object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); 311 object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); 312 } 313 if (info->has_ppus) { 314 for (i = 0; i < info->num_cpus; i++) { 315 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 316 int ppuidx = CPU0CORE_PPU + i; 317 318 object_initialize_child(obj, name, &s->ppu[ppuidx], 319 TYPE_UNIMPLEMENTED_DEVICE); 320 g_free(name); 321 } 322 object_initialize_child(obj, "DBG_PPU", &s->ppu[DBG_PPU], 323 TYPE_UNIMPLEMENTED_DEVICE); 324 for (i = 0; i < info->sram_banks; i++) { 325 char *name = g_strdup_printf("RAM%d_PPU", i); 326 int ppuidx = RAM0_PPU + i; 327 328 object_initialize_child(obj, name, &s->ppu[ppuidx], 329 TYPE_UNIMPLEMENTED_DEVICE); 330 g_free(name); 331 } 332 } 333 if (info->has_cachectrl) { 334 for (i = 0; i < info->num_cpus; i++) { 335 char *name = g_strdup_printf("cachectrl%d", i); 336 337 object_initialize_child(obj, name, &s->cachectrl[i], 338 TYPE_UNIMPLEMENTED_DEVICE); 339 g_free(name); 340 } 341 } 342 if (info->has_cpusecctrl) { 343 for (i = 0; i < info->num_cpus; i++) { 344 char *name = g_strdup_printf("cpusecctrl%d", i); 345 346 object_initialize_child(obj, name, &s->cpusecctrl[i], 347 TYPE_UNIMPLEMENTED_DEVICE); 348 g_free(name); 349 } 350 } 351 if (info->has_cpuid) { 352 for (i = 0; i < info->num_cpus; i++) { 353 char *name = g_strdup_printf("cpuid%d", i); 354 355 object_initialize_child(obj, name, &s->cpuid[i], 356 TYPE_ARMSSE_CPUID); 357 g_free(name); 358 } 359 } 360 object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ); 361 object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, 362 TYPE_OR_IRQ); 363 object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter, 364 TYPE_SPLIT_IRQ); 365 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 366 char *name = g_strdup_printf("ppc-irq-splitter-%d", i); 367 SplitIRQ *splitter = &s->ppc_irq_splitter[i]; 368 369 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 370 g_free(name); 371 } 372 if (info->num_cpus > 1) { 373 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 374 if (irq_is_common[i]) { 375 char *name = g_strdup_printf("cpu-irq-splitter%d", i); 376 SplitIRQ *splitter = &s->cpu_irq_splitter[i]; 377 378 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 379 g_free(name); 380 } 381 } 382 } 383 } 384 385 static void armsse_exp_irq(void *opaque, int n, int level) 386 { 387 qemu_irq *irqarray = opaque; 388 389 qemu_set_irq(irqarray[n], level); 390 } 391 392 static void armsse_mpcexp_status(void *opaque, int n, int level) 393 { 394 ARMSSE *s = ARM_SSE(opaque); 395 qemu_set_irq(s->mpcexp_status_in[n], level); 396 } 397 398 static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno) 399 { 400 /* 401 * Return a qemu_irq which can be used to signal IRQ n to 402 * all CPUs in the SSE. 403 */ 404 ARMSSEClass *asc = ARM_SSE_GET_CLASS(s); 405 const ARMSSEInfo *info = asc->info; 406 407 assert(irq_is_common[irqno]); 408 409 if (info->num_cpus == 1) { 410 /* Only one CPU -- just connect directly to it */ 411 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); 412 } else { 413 /* Connect to the splitter which feeds all CPUs */ 414 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); 415 } 416 } 417 418 static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) 419 { 420 /* Map a PPU unimplemented device stub */ 421 DeviceState *dev = DEVICE(&s->ppu[ppuidx]); 422 423 qdev_prop_set_string(dev, "name", name); 424 qdev_prop_set_uint64(dev, "size", 0x1000); 425 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 426 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); 427 } 428 429 static void armsse_realize(DeviceState *dev, Error **errp) 430 { 431 ARMSSE *s = ARM_SSE(dev); 432 ARMSSEClass *asc = ARM_SSE_GET_CLASS(dev); 433 const ARMSSEInfo *info = asc->info; 434 int i; 435 MemoryRegion *mr; 436 Error *err = NULL; 437 SysBusDevice *sbd_apb_ppc0; 438 SysBusDevice *sbd_secctl; 439 DeviceState *dev_apb_ppc0; 440 DeviceState *dev_apb_ppc1; 441 DeviceState *dev_secctl; 442 DeviceState *dev_splitter; 443 uint32_t addr_width_max; 444 445 if (!s->board_memory) { 446 error_setg(errp, "memory property was not set"); 447 return; 448 } 449 450 if (!s->mainclk_frq) { 451 error_setg(errp, "MAINCLK property was not set"); 452 return; 453 } 454 455 assert(info->num_cpus <= SSE_MAX_CPUS); 456 457 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ 458 assert(is_power_of_2(info->sram_banks)); 459 addr_width_max = 24 - ctz32(info->sram_banks); 460 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { 461 error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d", 462 addr_width_max); 463 return; 464 } 465 466 /* Handling of which devices should be available only to secure 467 * code is usually done differently for M profile than for A profile. 468 * Instead of putting some devices only into the secure address space, 469 * devices exist in both address spaces but with hard-wired security 470 * permissions that will cause the CPU to fault for non-secure accesses. 471 * 472 * The ARMSSE has an IDAU (Implementation Defined Access Unit), 473 * which specifies hard-wired security permissions for different 474 * areas of the physical address space. For the ARMSSE IDAU, the 475 * top 4 bits of the physical address are the IDAU region ID, and 476 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS 477 * region, otherwise it is an S region. 478 * 479 * The various devices and RAMs are generally all mapped twice, 480 * once into a region that the IDAU defines as secure and once 481 * into a non-secure region. They sit behind either a Memory 482 * Protection Controller (for RAM) or a Peripheral Protection 483 * Controller (for devices), which allow a more fine grained 484 * configuration of whether non-secure accesses are permitted. 485 * 486 * (The other place that guest software can configure security 487 * permissions is in the architected SAU (Security Attribution 488 * Unit), which is entirely inside the CPU. The IDAU can upgrade 489 * the security attributes for a region to more restrictive than 490 * the SAU specifies, but cannot downgrade them.) 491 * 492 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff 493 * 0x20000000..0x2007ffff 32KB FPGA block RAM 494 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff 495 * 0x40000000..0x4000ffff base peripheral region 1 496 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) 497 * 0x40020000..0x4002ffff system control element peripherals 498 * 0x40080000..0x400fffff base peripheral region 2 499 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff 500 */ 501 502 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); 503 504 for (i = 0; i < info->num_cpus; i++) { 505 DeviceState *cpudev = DEVICE(&s->armv7m[i]); 506 Object *cpuobj = OBJECT(&s->armv7m[i]); 507 int j; 508 char *gpioname; 509 510 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32); 511 /* 512 * In real hardware the initial Secure VTOR is set from the INITSVTOR* 513 * registers in the IoT Kit System Control Register block. In QEMU 514 * we set the initial value here, and also the reset value of the 515 * sysctl register, from this object's QOM init-svtor property. 516 * If the guest changes the INITSVTOR* registers at runtime then the 517 * code in iotkit-sysctl.c will update the CPU init-svtor property 518 * (which will then take effect on the next CPU warm-reset). 519 * 520 * Note that typically a board using the SSE-200 will have a system 521 * control processor whose boot firmware initializes the INITSVTOR* 522 * registers before powering up the CPUs. QEMU doesn't emulate 523 * the control processor, so instead we behave in the way that the 524 * firmware does: the initial value should be set by the board code 525 * (using the init-svtor property on the ARMSSE object) to match 526 * whatever its firmware does. 527 */ 528 qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); 529 /* 530 * CPUs start powered down if the corresponding bit in the CPUWAIT 531 * register is 1. In real hardware the CPUWAIT register reset value is 532 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and 533 * CPUWAIT1_RST parameters), but since all the boards we care about 534 * start CPU0 and leave CPU1 powered off, we hard-code that in 535 * info->cpuwait_rst for now. We can add QOM properties for this 536 * later if necessary. 537 */ 538 if (extract32(info->cpuwait_rst, i, 1)) { 539 if (!object_property_set_bool(cpuobj, "start-powered-off", true, 540 errp)) { 541 return; 542 } 543 } 544 if (!s->cpu_fpu[i]) { 545 if (!object_property_set_bool(cpuobj, "vfp", false, errp)) { 546 return; 547 } 548 } 549 if (!s->cpu_dsp[i]) { 550 if (!object_property_set_bool(cpuobj, "dsp", false, errp)) { 551 return; 552 } 553 } 554 555 if (i > 0) { 556 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 557 &s->container_alias[i - 1], -1); 558 } else { 559 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 560 &s->container, -1); 561 } 562 object_property_set_link(cpuobj, "memory", 563 OBJECT(&s->cpu_container[i]), &error_abort); 564 object_property_set_link(cpuobj, "idau", OBJECT(s), &error_abort); 565 if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj), errp)) { 566 return; 567 } 568 /* 569 * The cluster must be realized after the armv7m container, as 570 * the container's CPU object is only created on realize, and the 571 * CPU must exist and have been parented into the cluster before 572 * the cluster is realized. 573 */ 574 if (!qdev_realize(DEVICE(&s->cluster[i]), NULL, errp)) { 575 return; 576 } 577 578 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ 579 s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); 580 for (j = 0; j < s->exp_numirq; j++) { 581 s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32); 582 } 583 if (i == 0) { 584 gpioname = g_strdup("EXP_IRQ"); 585 } else { 586 gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i); 587 } 588 qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq, 589 s->exp_irqs[i], 590 gpioname, s->exp_numirq); 591 g_free(gpioname); 592 } 593 594 /* Wire up the splitters that connect common IRQs to all CPUs */ 595 if (info->num_cpus > 1) { 596 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 597 if (irq_is_common[i]) { 598 Object *splitter = OBJECT(&s->cpu_irq_splitter[i]); 599 DeviceState *devs = DEVICE(splitter); 600 int cpunum; 601 602 if (!object_property_set_int(splitter, "num-lines", 603 info->num_cpus, errp)) { 604 return; 605 } 606 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 607 return; 608 } 609 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 610 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 611 612 qdev_connect_gpio_out(devs, cpunum, 613 qdev_get_gpio_in(cpudev, i)); 614 } 615 } 616 } 617 } 618 619 /* Set up the big aliases first */ 620 make_alias(s, &s->alias1, &s->container, "alias 1", 621 0x10000000, 0x10000000, 0x00000000); 622 make_alias(s, &s->alias2, &s->container, 623 "alias 2", 0x30000000, 0x10000000, 0x20000000); 624 /* The 0x50000000..0x5fffffff region is not a pure alias: it has 625 * a few extra devices that only appear there (generally the 626 * control interfaces for the protection controllers). 627 * We implement this by mapping those devices over the top of this 628 * alias MR at a higher priority. Some of the devices in this range 629 * are per-CPU, so we must put this alias in the per-cpu containers. 630 */ 631 for (i = 0; i < info->num_cpus; i++) { 632 make_alias(s, &s->alias3[i], &s->cpu_container[i], 633 "alias 3", 0x50000000, 0x10000000, 0x40000000); 634 } 635 636 /* Security controller */ 637 if (!sysbus_realize(SYS_BUS_DEVICE(&s->secctl), errp)) { 638 return; 639 } 640 sbd_secctl = SYS_BUS_DEVICE(&s->secctl); 641 dev_secctl = DEVICE(&s->secctl); 642 sysbus_mmio_map(sbd_secctl, 0, 0x50080000); 643 sysbus_mmio_map(sbd_secctl, 1, 0x40080000); 644 645 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); 646 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); 647 648 /* The sec_resp_cfg output from the security controller must be split into 649 * multiple lines, one for each of the PPCs within the ARMSSE and one 650 * that will be an output from the ARMSSE to the system. 651 */ 652 if (!object_property_set_int(OBJECT(&s->sec_resp_splitter), 653 "num-lines", 3, errp)) { 654 return; 655 } 656 if (!qdev_realize(DEVICE(&s->sec_resp_splitter), NULL, errp)) { 657 return; 658 } 659 dev_splitter = DEVICE(&s->sec_resp_splitter); 660 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, 661 qdev_get_gpio_in(dev_splitter, 0)); 662 663 /* Each SRAM bank lives behind its own Memory Protection Controller */ 664 for (i = 0; i < info->sram_banks; i++) { 665 char *ramname = g_strdup_printf("armsse.sram%d", i); 666 SysBusDevice *sbd_mpc; 667 uint32_t sram_bank_size = 1 << s->sram_addr_width; 668 669 memory_region_init_ram(&s->sram[i], NULL, ramname, 670 sram_bank_size, &err); 671 g_free(ramname); 672 if (err) { 673 error_propagate(errp, err); 674 return; 675 } 676 object_property_set_link(OBJECT(&s->mpc[i]), "downstream", 677 OBJECT(&s->sram[i]), &error_abort); 678 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mpc[i]), errp)) { 679 return; 680 } 681 /* Map the upstream end of the MPC into the right place... */ 682 sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); 683 memory_region_add_subregion(&s->container, 684 0x20000000 + i * sram_bank_size, 685 sysbus_mmio_get_region(sbd_mpc, 1)); 686 /* ...and its register interface */ 687 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, 688 sysbus_mmio_get_region(sbd_mpc, 0)); 689 } 690 691 /* We must OR together lines from the MPC splitters to go to the NVIC */ 692 if (!object_property_set_int(OBJECT(&s->mpc_irq_orgate), "num-lines", 693 IOTS_NUM_EXP_MPC + info->sram_banks, 694 errp)) { 695 return; 696 } 697 if (!qdev_realize(DEVICE(&s->mpc_irq_orgate), NULL, errp)) { 698 return; 699 } 700 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, 701 armsse_get_common_irq_in(s, 9)); 702 703 /* Devices behind APB PPC0: 704 * 0x40000000: timer0 705 * 0x40001000: timer1 706 * 0x40002000: dual timer 707 * 0x40003000: MHU0 (SSE-200 only) 708 * 0x40004000: MHU1 (SSE-200 only) 709 * We must configure and realize each downstream device and connect 710 * it to the appropriate PPC port; then we can realize the PPC and 711 * map its upstream ends to the right place in the container. 712 */ 713 qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); 714 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { 715 return; 716 } 717 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, 718 armsse_get_common_irq_in(s, 3)); 719 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); 720 object_property_set_link(OBJECT(&s->apb_ppc0), "port[0]", OBJECT(mr), 721 &error_abort); 722 723 qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); 724 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { 725 return; 726 } 727 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, 728 armsse_get_common_irq_in(s, 4)); 729 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); 730 object_property_set_link(OBJECT(&s->apb_ppc0), "port[1]", OBJECT(mr), 731 &error_abort); 732 733 qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); 734 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { 735 return; 736 } 737 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dualtimer), 0, 738 armsse_get_common_irq_in(s, 5)); 739 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); 740 object_property_set_link(OBJECT(&s->apb_ppc0), "port[2]", OBJECT(mr), 741 &error_abort); 742 743 if (info->has_mhus) { 744 /* 745 * An SSE-200 with only one CPU should have only one MHU created, 746 * with the region where the second MHU usually is being RAZ/WI. 747 * We don't implement that SSE-200 config; if we want to support 748 * it then this code needs to be enhanced to handle creating the 749 * RAZ/WI region instead of the second MHU. 750 */ 751 assert(info->num_cpus == ARRAY_SIZE(s->mhu)); 752 753 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { 754 char *port; 755 int cpunum; 756 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]); 757 758 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mhu[i]), errp)) { 759 return; 760 } 761 port = g_strdup_printf("port[%d]", i + 3); 762 mr = sysbus_mmio_get_region(mhu_sbd, 0); 763 object_property_set_link(OBJECT(&s->apb_ppc0), port, OBJECT(mr), 764 &error_abort); 765 g_free(port); 766 767 /* 768 * Each MHU has an irq line for each CPU: 769 * MHU 0 irq line 0 -> CPU 0 IRQ 6 770 * MHU 0 irq line 1 -> CPU 1 IRQ 6 771 * MHU 1 irq line 0 -> CPU 0 IRQ 7 772 * MHU 1 irq line 1 -> CPU 1 IRQ 7 773 */ 774 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 775 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 776 777 sysbus_connect_irq(mhu_sbd, cpunum, 778 qdev_get_gpio_in(cpudev, 6 + i)); 779 } 780 } 781 } 782 783 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc0), errp)) { 784 return; 785 } 786 787 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); 788 dev_apb_ppc0 = DEVICE(&s->apb_ppc0); 789 790 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); 791 memory_region_add_subregion(&s->container, 0x40000000, mr); 792 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); 793 memory_region_add_subregion(&s->container, 0x40001000, mr); 794 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); 795 memory_region_add_subregion(&s->container, 0x40002000, mr); 796 if (info->has_mhus) { 797 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3); 798 memory_region_add_subregion(&s->container, 0x40003000, mr); 799 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4); 800 memory_region_add_subregion(&s->container, 0x40004000, mr); 801 } 802 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { 803 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, 804 qdev_get_gpio_in_named(dev_apb_ppc0, 805 "cfg_nonsec", i)); 806 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, 807 qdev_get_gpio_in_named(dev_apb_ppc0, 808 "cfg_ap", i)); 809 } 810 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, 811 qdev_get_gpio_in_named(dev_apb_ppc0, 812 "irq_enable", 0)); 813 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, 814 qdev_get_gpio_in_named(dev_apb_ppc0, 815 "irq_clear", 0)); 816 qdev_connect_gpio_out(dev_splitter, 0, 817 qdev_get_gpio_in_named(dev_apb_ppc0, 818 "cfg_sec_resp", 0)); 819 820 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external 821 * ones) are sent individually to the security controller, and also 822 * ORed together to give a single combined PPC interrupt to the NVIC. 823 */ 824 if (!object_property_set_int(OBJECT(&s->ppc_irq_orgate), 825 "num-lines", NUM_PPCS, errp)) { 826 return; 827 } 828 if (!qdev_realize(DEVICE(&s->ppc_irq_orgate), NULL, errp)) { 829 return; 830 } 831 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, 832 armsse_get_common_irq_in(s, 10)); 833 834 /* 835 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): 836 * private per-CPU region (all these devices are SSE-200 only): 837 * 0x50010000: L1 icache control registers 838 * 0x50011000: CPUSECCTRL (CPU local security control registers) 839 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block 840 */ 841 if (info->has_cachectrl) { 842 for (i = 0; i < info->num_cpus; i++) { 843 char *name = g_strdup_printf("cachectrl%d", i); 844 MemoryRegion *mr; 845 846 qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); 847 g_free(name); 848 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); 849 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cachectrl[i]), errp)) { 850 return; 851 } 852 853 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); 854 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); 855 } 856 } 857 if (info->has_cpusecctrl) { 858 for (i = 0; i < info->num_cpus; i++) { 859 char *name = g_strdup_printf("CPUSECCTRL%d", i); 860 MemoryRegion *mr; 861 862 qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); 863 g_free(name); 864 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); 865 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpusecctrl[i]), errp)) { 866 return; 867 } 868 869 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); 870 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); 871 } 872 } 873 if (info->has_cpuid) { 874 for (i = 0; i < info->num_cpus; i++) { 875 MemoryRegion *mr; 876 877 qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); 878 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpuid[i]), errp)) { 879 return; 880 } 881 882 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); 883 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); 884 } 885 } 886 887 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */ 888 /* Devices behind APB PPC1: 889 * 0x4002f000: S32K timer 890 */ 891 qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); 892 if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { 893 return; 894 } 895 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, 896 armsse_get_common_irq_in(s, 2)); 897 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); 898 object_property_set_link(OBJECT(&s->apb_ppc1), "port[0]", OBJECT(mr), 899 &error_abort); 900 901 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc1), errp)) { 902 return; 903 } 904 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); 905 memory_region_add_subregion(&s->container, 0x4002f000, mr); 906 907 dev_apb_ppc1 = DEVICE(&s->apb_ppc1); 908 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, 909 qdev_get_gpio_in_named(dev_apb_ppc1, 910 "cfg_nonsec", 0)); 911 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, 912 qdev_get_gpio_in_named(dev_apb_ppc1, 913 "cfg_ap", 0)); 914 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, 915 qdev_get_gpio_in_named(dev_apb_ppc1, 916 "irq_enable", 0)); 917 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, 918 qdev_get_gpio_in_named(dev_apb_ppc1, 919 "irq_clear", 0)); 920 qdev_connect_gpio_out(dev_splitter, 1, 921 qdev_get_gpio_in_named(dev_apb_ppc1, 922 "cfg_sec_resp", 0)); 923 924 if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION", 925 info->sys_version, errp)) { 926 return; 927 } 928 if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG", 929 armsse_sys_config_value(s, info), errp)) { 930 return; 931 } 932 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), errp)) { 933 return; 934 } 935 /* System information registers */ 936 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); 937 /* System control registers */ 938 object_property_set_int(OBJECT(&s->sysctl), "SYS_VERSION", 939 info->sys_version, &error_abort); 940 object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST", 941 info->cpuwait_rst, &error_abort); 942 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST", 943 s->init_svtor, &error_abort); 944 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST", 945 s->init_svtor, &error_abort); 946 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysctl), errp)) { 947 return; 948 } 949 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); 950 951 if (info->has_ppus) { 952 /* CPUnCORE_PPU for each CPU */ 953 for (i = 0; i < info->num_cpus; i++) { 954 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 955 956 map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); 957 /* 958 * We don't support CPU debug so don't create the 959 * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. 960 */ 961 g_free(name); 962 } 963 map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); 964 965 for (i = 0; i < info->sram_banks; i++) { 966 char *name = g_strdup_printf("RAM%d_PPU", i); 967 968 map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); 969 g_free(name); 970 } 971 } 972 973 /* This OR gate wires together outputs from the secure watchdogs to NMI */ 974 if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2, 975 errp)) { 976 return; 977 } 978 if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) { 979 return; 980 } 981 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, 982 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); 983 984 qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); 985 if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { 986 return; 987 } 988 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 989 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 0)); 990 sysbus_mmio_map(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 0x5002e000); 991 992 /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ 993 994 qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); 995 if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { 996 return; 997 } 998 sysbus_connect_irq(SYS_BUS_DEVICE(&s->nswatchdog), 0, 999 armsse_get_common_irq_in(s, 1)); 1000 sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); 1001 1002 qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); 1003 if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { 1004 return; 1005 } 1006 sysbus_connect_irq(SYS_BUS_DEVICE(&s->swatchdog), 0, 1007 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 1)); 1008 sysbus_mmio_map(SYS_BUS_DEVICE(&s->swatchdog), 0, 0x50081000); 1009 1010 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 1011 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); 1012 1013 if (!object_property_set_int(splitter, "num-lines", 2, errp)) { 1014 return; 1015 } 1016 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1017 return; 1018 } 1019 } 1020 1021 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { 1022 char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); 1023 1024 armsse_forward_ppc(s, ppcname, i); 1025 g_free(ppcname); 1026 } 1027 1028 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { 1029 char *ppcname = g_strdup_printf("apb_ppcexp%d", i); 1030 1031 armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); 1032 g_free(ppcname); 1033 } 1034 1035 for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { 1036 /* Wire up IRQ splitter for internal PPCs */ 1037 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); 1038 char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", 1039 i - NUM_EXTERNAL_PPCS); 1040 TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; 1041 1042 qdev_connect_gpio_out(devs, 0, 1043 qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); 1044 qdev_connect_gpio_out(devs, 1, 1045 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); 1046 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, 1047 qdev_get_gpio_in(devs, 0)); 1048 g_free(gpioname); 1049 } 1050 1051 /* Wire up the splitters for the MPC IRQs */ 1052 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 1053 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 1054 DeviceState *dev_splitter = DEVICE(splitter); 1055 1056 if (!object_property_set_int(OBJECT(splitter), "num-lines", 2, 1057 errp)) { 1058 return; 1059 } 1060 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1061 return; 1062 } 1063 1064 if (i < IOTS_NUM_EXP_MPC) { 1065 /* Splitter input is from GPIO input line */ 1066 s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0); 1067 qdev_connect_gpio_out(dev_splitter, 0, 1068 qdev_get_gpio_in_named(dev_secctl, 1069 "mpcexp_status", i)); 1070 } else { 1071 /* Splitter input is from our own MPC */ 1072 qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]), 1073 "irq", 0, 1074 qdev_get_gpio_in(dev_splitter, 0)); 1075 qdev_connect_gpio_out(dev_splitter, 0, 1076 qdev_get_gpio_in_named(dev_secctl, 1077 "mpc_status", 1078 i - IOTS_NUM_EXP_MPC)); 1079 } 1080 1081 qdev_connect_gpio_out(dev_splitter, 1, 1082 qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i)); 1083 } 1084 /* Create GPIO inputs which will pass the line state for our 1085 * mpcexp_irq inputs to the correct splitter devices. 1086 */ 1087 qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status", 1088 IOTS_NUM_EXP_MPC); 1089 1090 armsse_forward_sec_resp_cfg(s); 1091 1092 /* Forward the MSC related signals */ 1093 qdev_pass_gpios(dev_secctl, dev, "mscexp_status"); 1094 qdev_pass_gpios(dev_secctl, dev, "mscexp_clear"); 1095 qdev_pass_gpios(dev_secctl, dev, "mscexp_ns"); 1096 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, 1097 armsse_get_common_irq_in(s, 11)); 1098 1099 /* 1100 * Expose our container region to the board model; this corresponds 1101 * to the AHB Slave Expansion ports which allow bus master devices 1102 * (eg DMA controllers) in the board model to make transactions into 1103 * devices in the ARMSSE. 1104 */ 1105 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); 1106 1107 system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; 1108 } 1109 1110 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, 1111 int *iregion, bool *exempt, bool *ns, bool *nsc) 1112 { 1113 /* 1114 * For ARMSSE systems the IDAU responses are simple logical functions 1115 * of the address bits. The NSC attribute is guest-adjustable via the 1116 * NSCCFG register in the security controller. 1117 */ 1118 ARMSSE *s = ARM_SSE(ii); 1119 int region = extract32(address, 28, 4); 1120 1121 *ns = !(region & 1); 1122 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); 1123 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1124 *exempt = (address & 0xeff00000) == 0xe0000000; 1125 *iregion = region; 1126 } 1127 1128 static const VMStateDescription armsse_vmstate = { 1129 .name = "iotkit", 1130 .version_id = 1, 1131 .minimum_version_id = 1, 1132 .fields = (VMStateField[]) { 1133 VMSTATE_UINT32(nsccfg, ARMSSE), 1134 VMSTATE_END_OF_LIST() 1135 } 1136 }; 1137 1138 static void armsse_reset(DeviceState *dev) 1139 { 1140 ARMSSE *s = ARM_SSE(dev); 1141 1142 s->nsccfg = 0; 1143 } 1144 1145 static void armsse_class_init(ObjectClass *klass, void *data) 1146 { 1147 DeviceClass *dc = DEVICE_CLASS(klass); 1148 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); 1149 ARMSSEClass *asc = ARM_SSE_CLASS(klass); 1150 const ARMSSEInfo *info = data; 1151 1152 dc->realize = armsse_realize; 1153 dc->vmsd = &armsse_vmstate; 1154 device_class_set_props(dc, info->props); 1155 dc->reset = armsse_reset; 1156 iic->check = armsse_idau_check; 1157 asc->info = info; 1158 } 1159 1160 static const TypeInfo armsse_info = { 1161 .name = TYPE_ARM_SSE, 1162 .parent = TYPE_SYS_BUS_DEVICE, 1163 .instance_size = sizeof(ARMSSE), 1164 .class_size = sizeof(ARMSSEClass), 1165 .instance_init = armsse_init, 1166 .abstract = true, 1167 .interfaces = (InterfaceInfo[]) { 1168 { TYPE_IDAU_INTERFACE }, 1169 { } 1170 } 1171 }; 1172 1173 static void armsse_register_types(void) 1174 { 1175 int i; 1176 1177 type_register_static(&armsse_info); 1178 1179 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) { 1180 TypeInfo ti = { 1181 .name = armsse_variants[i].name, 1182 .parent = TYPE_ARM_SSE, 1183 .class_init = armsse_class_init, 1184 .class_data = (void *)&armsse_variants[i], 1185 }; 1186 type_register(&ti); 1187 } 1188 } 1189 1190 type_init(armsse_register_types); 1191