1 /* 2 * Arm SSE (Subsystems for Embedded): IoTKit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qemu/bitops.h" 16 #include "qapi/error.h" 17 #include "trace.h" 18 #include "hw/sysbus.h" 19 #include "migration/vmstate.h" 20 #include "hw/registerfields.h" 21 #include "hw/arm/armsse.h" 22 #include "hw/arm/boot.h" 23 #include "hw/irq.h" 24 #include "hw/qdev-clock.h" 25 26 /* Format of the System Information block SYS_CONFIG register */ 27 typedef enum SysConfigFormat { 28 IoTKitFormat, 29 SSE200Format, 30 } SysConfigFormat; 31 32 struct ARMSSEInfo { 33 const char *name; 34 int sram_banks; 35 int num_cpus; 36 uint32_t sys_version; 37 uint32_t cpuwait_rst; 38 SysConfigFormat sys_config_format; 39 bool has_mhus; 40 bool has_ppus; 41 bool has_cachectrl; 42 bool has_cpusecctrl; 43 bool has_cpuid; 44 Property *props; 45 }; 46 47 static Property iotkit_properties[] = { 48 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 49 MemoryRegion *), 50 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 51 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 52 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 53 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), 54 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), 55 DEFINE_PROP_END_OF_LIST() 56 }; 57 58 static Property armsse_properties[] = { 59 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 60 MemoryRegion *), 61 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 62 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 63 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 64 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), 65 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), 66 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), 67 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), 68 DEFINE_PROP_END_OF_LIST() 69 }; 70 71 static const ARMSSEInfo armsse_variants[] = { 72 { 73 .name = TYPE_IOTKIT, 74 .sram_banks = 1, 75 .num_cpus = 1, 76 .sys_version = 0x41743, 77 .cpuwait_rst = 0, 78 .sys_config_format = IoTKitFormat, 79 .has_mhus = false, 80 .has_ppus = false, 81 .has_cachectrl = false, 82 .has_cpusecctrl = false, 83 .has_cpuid = false, 84 .props = iotkit_properties, 85 }, 86 { 87 .name = TYPE_SSE200, 88 .sram_banks = 4, 89 .num_cpus = 2, 90 .sys_version = 0x22041743, 91 .cpuwait_rst = 2, 92 .sys_config_format = SSE200Format, 93 .has_mhus = true, 94 .has_ppus = true, 95 .has_cachectrl = true, 96 .has_cpusecctrl = true, 97 .has_cpuid = true, 98 .props = armsse_properties, 99 }, 100 }; 101 102 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) 103 { 104 /* Return the SYS_CONFIG value for this SSE */ 105 uint32_t sys_config; 106 107 switch (info->sys_config_format) { 108 case IoTKitFormat: 109 sys_config = 0; 110 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 111 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); 112 break; 113 case SSE200Format: 114 sys_config = 0; 115 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 116 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 117 sys_config = deposit32(sys_config, 24, 4, 2); 118 if (info->num_cpus > 1) { 119 sys_config = deposit32(sys_config, 10, 1, 1); 120 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1); 121 sys_config = deposit32(sys_config, 28, 4, 2); 122 } 123 break; 124 default: 125 g_assert_not_reached(); 126 } 127 return sys_config; 128 } 129 130 /* Clock frequency in HZ of the 32KHz "slow clock" */ 131 #define S32KCLK (32 * 1000) 132 133 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ 134 static bool irq_is_common[32] = { 135 [0 ... 5] = true, 136 /* 6, 7: per-CPU MHU interrupts */ 137 [8 ... 12] = true, 138 /* 13: per-CPU icache interrupt */ 139 /* 14: reserved */ 140 [15 ... 20] = true, 141 /* 21: reserved */ 142 [22 ... 26] = true, 143 /* 27: reserved */ 144 /* 28, 29: per-CPU CTI interrupts */ 145 /* 30, 31: reserved */ 146 }; 147 148 /* 149 * Create an alias region in @container of @size bytes starting at @base 150 * which mirrors the memory starting at @orig. 151 */ 152 static void make_alias(ARMSSE *s, MemoryRegion *mr, MemoryRegion *container, 153 const char *name, hwaddr base, hwaddr size, hwaddr orig) 154 { 155 memory_region_init_alias(mr, NULL, name, container, orig, size); 156 /* The alias is even lower priority than unimplemented_device regions */ 157 memory_region_add_subregion_overlap(container, base, mr, -1500); 158 } 159 160 static void irq_status_forwarder(void *opaque, int n, int level) 161 { 162 qemu_irq destirq = opaque; 163 164 qemu_set_irq(destirq, level); 165 } 166 167 static void nsccfg_handler(void *opaque, int n, int level) 168 { 169 ARMSSE *s = ARM_SSE(opaque); 170 171 s->nsccfg = level; 172 } 173 174 static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) 175 { 176 /* Each of the 4 AHB and 4 APB PPCs that might be present in a 177 * system using the ARMSSE has a collection of control lines which 178 * are provided by the security controller and which we want to 179 * expose as control lines on the ARMSSE device itself, so the 180 * code using the ARMSSE can wire them up to the PPCs. 181 */ 182 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; 183 DeviceState *armssedev = DEVICE(s); 184 DeviceState *dev_secctl = DEVICE(&s->secctl); 185 DeviceState *dev_splitter = DEVICE(splitter); 186 char *name; 187 188 name = g_strdup_printf("%s_nonsec", ppcname); 189 qdev_pass_gpios(dev_secctl, armssedev, name); 190 g_free(name); 191 name = g_strdup_printf("%s_ap", ppcname); 192 qdev_pass_gpios(dev_secctl, armssedev, name); 193 g_free(name); 194 name = g_strdup_printf("%s_irq_enable", ppcname); 195 qdev_pass_gpios(dev_secctl, armssedev, name); 196 g_free(name); 197 name = g_strdup_printf("%s_irq_clear", ppcname); 198 qdev_pass_gpios(dev_secctl, armssedev, name); 199 g_free(name); 200 201 /* irq_status is a little more tricky, because we need to 202 * split it so we can send it both to the security controller 203 * and to our OR gate for the NVIC interrupt line. 204 * Connect up the splitter's outputs, and create a GPIO input 205 * which will pass the line state to the input splitter. 206 */ 207 name = g_strdup_printf("%s_irq_status", ppcname); 208 qdev_connect_gpio_out(dev_splitter, 0, 209 qdev_get_gpio_in_named(dev_secctl, 210 name, 0)); 211 qdev_connect_gpio_out(dev_splitter, 1, 212 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); 213 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); 214 qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder, 215 s->irq_status_in[ppcnum], name, 1); 216 g_free(name); 217 } 218 219 static void armsse_forward_sec_resp_cfg(ARMSSE *s) 220 { 221 /* Forward the 3rd output from the splitter device as a 222 * named GPIO output of the armsse object. 223 */ 224 DeviceState *dev = DEVICE(s); 225 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); 226 227 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); 228 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, 229 s->sec_resp_cfg, 1); 230 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); 231 } 232 233 static void armsse_mainclk_update(void *opaque) 234 { 235 ARMSSE *s = ARM_SSE(opaque); 236 /* 237 * Set system_clock_scale from our Clock input; this is what 238 * controls the tick rate of the CPU SysTick timer. 239 */ 240 system_clock_scale = clock_ticks_to_ns(s->mainclk, 1); 241 } 242 243 static void armsse_init(Object *obj) 244 { 245 ARMSSE *s = ARM_SSE(obj); 246 ARMSSEClass *asc = ARM_SSE_GET_CLASS(obj); 247 const ARMSSEInfo *info = asc->info; 248 int i; 249 250 assert(info->sram_banks <= MAX_SRAM_BANKS); 251 assert(info->num_cpus <= SSE_MAX_CPUS); 252 253 s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", 254 armsse_mainclk_update, s); 255 s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL); 256 257 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); 258 259 for (i = 0; i < info->num_cpus; i++) { 260 /* 261 * We put each CPU in its own cluster as they are logically 262 * distinct and may be configured differently. 263 */ 264 char *name; 265 266 name = g_strdup_printf("cluster%d", i); 267 object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER); 268 qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); 269 g_free(name); 270 271 name = g_strdup_printf("armv7m%d", i); 272 object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i], 273 TYPE_ARMV7M); 274 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", 275 ARM_CPU_TYPE_NAME("cortex-m33")); 276 g_free(name); 277 name = g_strdup_printf("arm-sse-cpu-container%d", i); 278 memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); 279 g_free(name); 280 if (i > 0) { 281 name = g_strdup_printf("arm-sse-container-alias%d", i); 282 memory_region_init_alias(&s->container_alias[i - 1], obj, 283 name, &s->container, 0, UINT64_MAX); 284 g_free(name); 285 } 286 } 287 288 object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL); 289 object_initialize_child(obj, "apb-ppc0", &s->apb_ppc0, TYPE_TZ_PPC); 290 object_initialize_child(obj, "apb-ppc1", &s->apb_ppc1, TYPE_TZ_PPC); 291 for (i = 0; i < info->sram_banks; i++) { 292 char *name = g_strdup_printf("mpc%d", i); 293 object_initialize_child(obj, name, &s->mpc[i], TYPE_TZ_MPC); 294 g_free(name); 295 } 296 object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate, 297 TYPE_OR_IRQ); 298 299 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 300 char *name = g_strdup_printf("mpc-irq-splitter-%d", i); 301 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 302 303 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 304 g_free(name); 305 } 306 object_initialize_child(obj, "timer0", &s->timer0, TYPE_CMSDK_APB_TIMER); 307 object_initialize_child(obj, "timer1", &s->timer1, TYPE_CMSDK_APB_TIMER); 308 object_initialize_child(obj, "s32ktimer", &s->s32ktimer, 309 TYPE_CMSDK_APB_TIMER); 310 object_initialize_child(obj, "dualtimer", &s->dualtimer, 311 TYPE_CMSDK_APB_DUALTIMER); 312 object_initialize_child(obj, "s32kwatchdog", &s->s32kwatchdog, 313 TYPE_CMSDK_APB_WATCHDOG); 314 object_initialize_child(obj, "nswatchdog", &s->nswatchdog, 315 TYPE_CMSDK_APB_WATCHDOG); 316 object_initialize_child(obj, "swatchdog", &s->swatchdog, 317 TYPE_CMSDK_APB_WATCHDOG); 318 object_initialize_child(obj, "armsse-sysctl", &s->sysctl, 319 TYPE_IOTKIT_SYSCTL); 320 object_initialize_child(obj, "armsse-sysinfo", &s->sysinfo, 321 TYPE_IOTKIT_SYSINFO); 322 if (info->has_mhus) { 323 object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); 324 object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); 325 } 326 if (info->has_ppus) { 327 for (i = 0; i < info->num_cpus; i++) { 328 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 329 int ppuidx = CPU0CORE_PPU + i; 330 331 object_initialize_child(obj, name, &s->ppu[ppuidx], 332 TYPE_UNIMPLEMENTED_DEVICE); 333 g_free(name); 334 } 335 object_initialize_child(obj, "DBG_PPU", &s->ppu[DBG_PPU], 336 TYPE_UNIMPLEMENTED_DEVICE); 337 for (i = 0; i < info->sram_banks; i++) { 338 char *name = g_strdup_printf("RAM%d_PPU", i); 339 int ppuidx = RAM0_PPU + i; 340 341 object_initialize_child(obj, name, &s->ppu[ppuidx], 342 TYPE_UNIMPLEMENTED_DEVICE); 343 g_free(name); 344 } 345 } 346 if (info->has_cachectrl) { 347 for (i = 0; i < info->num_cpus; i++) { 348 char *name = g_strdup_printf("cachectrl%d", i); 349 350 object_initialize_child(obj, name, &s->cachectrl[i], 351 TYPE_UNIMPLEMENTED_DEVICE); 352 g_free(name); 353 } 354 } 355 if (info->has_cpusecctrl) { 356 for (i = 0; i < info->num_cpus; i++) { 357 char *name = g_strdup_printf("cpusecctrl%d", i); 358 359 object_initialize_child(obj, name, &s->cpusecctrl[i], 360 TYPE_UNIMPLEMENTED_DEVICE); 361 g_free(name); 362 } 363 } 364 if (info->has_cpuid) { 365 for (i = 0; i < info->num_cpus; i++) { 366 char *name = g_strdup_printf("cpuid%d", i); 367 368 object_initialize_child(obj, name, &s->cpuid[i], 369 TYPE_ARMSSE_CPUID); 370 g_free(name); 371 } 372 } 373 object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ); 374 object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, 375 TYPE_OR_IRQ); 376 object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter, 377 TYPE_SPLIT_IRQ); 378 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 379 char *name = g_strdup_printf("ppc-irq-splitter-%d", i); 380 SplitIRQ *splitter = &s->ppc_irq_splitter[i]; 381 382 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 383 g_free(name); 384 } 385 if (info->num_cpus > 1) { 386 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 387 if (irq_is_common[i]) { 388 char *name = g_strdup_printf("cpu-irq-splitter%d", i); 389 SplitIRQ *splitter = &s->cpu_irq_splitter[i]; 390 391 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 392 g_free(name); 393 } 394 } 395 } 396 } 397 398 static void armsse_exp_irq(void *opaque, int n, int level) 399 { 400 qemu_irq *irqarray = opaque; 401 402 qemu_set_irq(irqarray[n], level); 403 } 404 405 static void armsse_mpcexp_status(void *opaque, int n, int level) 406 { 407 ARMSSE *s = ARM_SSE(opaque); 408 qemu_set_irq(s->mpcexp_status_in[n], level); 409 } 410 411 static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno) 412 { 413 /* 414 * Return a qemu_irq which can be used to signal IRQ n to 415 * all CPUs in the SSE. 416 */ 417 ARMSSEClass *asc = ARM_SSE_GET_CLASS(s); 418 const ARMSSEInfo *info = asc->info; 419 420 assert(irq_is_common[irqno]); 421 422 if (info->num_cpus == 1) { 423 /* Only one CPU -- just connect directly to it */ 424 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); 425 } else { 426 /* Connect to the splitter which feeds all CPUs */ 427 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); 428 } 429 } 430 431 static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) 432 { 433 /* Map a PPU unimplemented device stub */ 434 DeviceState *dev = DEVICE(&s->ppu[ppuidx]); 435 436 qdev_prop_set_string(dev, "name", name); 437 qdev_prop_set_uint64(dev, "size", 0x1000); 438 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 439 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); 440 } 441 442 static void armsse_realize(DeviceState *dev, Error **errp) 443 { 444 ARMSSE *s = ARM_SSE(dev); 445 ARMSSEClass *asc = ARM_SSE_GET_CLASS(dev); 446 const ARMSSEInfo *info = asc->info; 447 int i; 448 MemoryRegion *mr; 449 Error *err = NULL; 450 SysBusDevice *sbd_apb_ppc0; 451 SysBusDevice *sbd_secctl; 452 DeviceState *dev_apb_ppc0; 453 DeviceState *dev_apb_ppc1; 454 DeviceState *dev_secctl; 455 DeviceState *dev_splitter; 456 uint32_t addr_width_max; 457 458 if (!s->board_memory) { 459 error_setg(errp, "memory property was not set"); 460 return; 461 } 462 463 if (!clock_has_source(s->mainclk)) { 464 error_setg(errp, "MAINCLK clock was not connected"); 465 } 466 if (!clock_has_source(s->s32kclk)) { 467 error_setg(errp, "S32KCLK clock was not connected"); 468 } 469 470 assert(info->num_cpus <= SSE_MAX_CPUS); 471 472 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ 473 assert(is_power_of_2(info->sram_banks)); 474 addr_width_max = 24 - ctz32(info->sram_banks); 475 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { 476 error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d", 477 addr_width_max); 478 return; 479 } 480 481 /* Handling of which devices should be available only to secure 482 * code is usually done differently for M profile than for A profile. 483 * Instead of putting some devices only into the secure address space, 484 * devices exist in both address spaces but with hard-wired security 485 * permissions that will cause the CPU to fault for non-secure accesses. 486 * 487 * The ARMSSE has an IDAU (Implementation Defined Access Unit), 488 * which specifies hard-wired security permissions for different 489 * areas of the physical address space. For the ARMSSE IDAU, the 490 * top 4 bits of the physical address are the IDAU region ID, and 491 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS 492 * region, otherwise it is an S region. 493 * 494 * The various devices and RAMs are generally all mapped twice, 495 * once into a region that the IDAU defines as secure and once 496 * into a non-secure region. They sit behind either a Memory 497 * Protection Controller (for RAM) or a Peripheral Protection 498 * Controller (for devices), which allow a more fine grained 499 * configuration of whether non-secure accesses are permitted. 500 * 501 * (The other place that guest software can configure security 502 * permissions is in the architected SAU (Security Attribution 503 * Unit), which is entirely inside the CPU. The IDAU can upgrade 504 * the security attributes for a region to more restrictive than 505 * the SAU specifies, but cannot downgrade them.) 506 * 507 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff 508 * 0x20000000..0x2007ffff 32KB FPGA block RAM 509 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff 510 * 0x40000000..0x4000ffff base peripheral region 1 511 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) 512 * 0x40020000..0x4002ffff system control element peripherals 513 * 0x40080000..0x400fffff base peripheral region 2 514 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff 515 */ 516 517 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); 518 519 for (i = 0; i < info->num_cpus; i++) { 520 DeviceState *cpudev = DEVICE(&s->armv7m[i]); 521 Object *cpuobj = OBJECT(&s->armv7m[i]); 522 int j; 523 char *gpioname; 524 525 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32); 526 /* 527 * In real hardware the initial Secure VTOR is set from the INITSVTOR* 528 * registers in the IoT Kit System Control Register block. In QEMU 529 * we set the initial value here, and also the reset value of the 530 * sysctl register, from this object's QOM init-svtor property. 531 * If the guest changes the INITSVTOR* registers at runtime then the 532 * code in iotkit-sysctl.c will update the CPU init-svtor property 533 * (which will then take effect on the next CPU warm-reset). 534 * 535 * Note that typically a board using the SSE-200 will have a system 536 * control processor whose boot firmware initializes the INITSVTOR* 537 * registers before powering up the CPUs. QEMU doesn't emulate 538 * the control processor, so instead we behave in the way that the 539 * firmware does: the initial value should be set by the board code 540 * (using the init-svtor property on the ARMSSE object) to match 541 * whatever its firmware does. 542 */ 543 qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); 544 /* 545 * CPUs start powered down if the corresponding bit in the CPUWAIT 546 * register is 1. In real hardware the CPUWAIT register reset value is 547 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and 548 * CPUWAIT1_RST parameters), but since all the boards we care about 549 * start CPU0 and leave CPU1 powered off, we hard-code that in 550 * info->cpuwait_rst for now. We can add QOM properties for this 551 * later if necessary. 552 */ 553 if (extract32(info->cpuwait_rst, i, 1)) { 554 if (!object_property_set_bool(cpuobj, "start-powered-off", true, 555 errp)) { 556 return; 557 } 558 } 559 if (!s->cpu_fpu[i]) { 560 if (!object_property_set_bool(cpuobj, "vfp", false, errp)) { 561 return; 562 } 563 } 564 if (!s->cpu_dsp[i]) { 565 if (!object_property_set_bool(cpuobj, "dsp", false, errp)) { 566 return; 567 } 568 } 569 570 if (i > 0) { 571 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 572 &s->container_alias[i - 1], -1); 573 } else { 574 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 575 &s->container, -1); 576 } 577 object_property_set_link(cpuobj, "memory", 578 OBJECT(&s->cpu_container[i]), &error_abort); 579 object_property_set_link(cpuobj, "idau", OBJECT(s), &error_abort); 580 if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj), errp)) { 581 return; 582 } 583 /* 584 * The cluster must be realized after the armv7m container, as 585 * the container's CPU object is only created on realize, and the 586 * CPU must exist and have been parented into the cluster before 587 * the cluster is realized. 588 */ 589 if (!qdev_realize(DEVICE(&s->cluster[i]), NULL, errp)) { 590 return; 591 } 592 593 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ 594 s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); 595 for (j = 0; j < s->exp_numirq; j++) { 596 s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32); 597 } 598 if (i == 0) { 599 gpioname = g_strdup("EXP_IRQ"); 600 } else { 601 gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i); 602 } 603 qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq, 604 s->exp_irqs[i], 605 gpioname, s->exp_numirq); 606 g_free(gpioname); 607 } 608 609 /* Wire up the splitters that connect common IRQs to all CPUs */ 610 if (info->num_cpus > 1) { 611 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 612 if (irq_is_common[i]) { 613 Object *splitter = OBJECT(&s->cpu_irq_splitter[i]); 614 DeviceState *devs = DEVICE(splitter); 615 int cpunum; 616 617 if (!object_property_set_int(splitter, "num-lines", 618 info->num_cpus, errp)) { 619 return; 620 } 621 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 622 return; 623 } 624 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 625 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 626 627 qdev_connect_gpio_out(devs, cpunum, 628 qdev_get_gpio_in(cpudev, i)); 629 } 630 } 631 } 632 } 633 634 /* Set up the big aliases first */ 635 make_alias(s, &s->alias1, &s->container, "alias 1", 636 0x10000000, 0x10000000, 0x00000000); 637 make_alias(s, &s->alias2, &s->container, 638 "alias 2", 0x30000000, 0x10000000, 0x20000000); 639 /* The 0x50000000..0x5fffffff region is not a pure alias: it has 640 * a few extra devices that only appear there (generally the 641 * control interfaces for the protection controllers). 642 * We implement this by mapping those devices over the top of this 643 * alias MR at a higher priority. Some of the devices in this range 644 * are per-CPU, so we must put this alias in the per-cpu containers. 645 */ 646 for (i = 0; i < info->num_cpus; i++) { 647 make_alias(s, &s->alias3[i], &s->cpu_container[i], 648 "alias 3", 0x50000000, 0x10000000, 0x40000000); 649 } 650 651 /* Security controller */ 652 if (!sysbus_realize(SYS_BUS_DEVICE(&s->secctl), errp)) { 653 return; 654 } 655 sbd_secctl = SYS_BUS_DEVICE(&s->secctl); 656 dev_secctl = DEVICE(&s->secctl); 657 sysbus_mmio_map(sbd_secctl, 0, 0x50080000); 658 sysbus_mmio_map(sbd_secctl, 1, 0x40080000); 659 660 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); 661 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); 662 663 /* The sec_resp_cfg output from the security controller must be split into 664 * multiple lines, one for each of the PPCs within the ARMSSE and one 665 * that will be an output from the ARMSSE to the system. 666 */ 667 if (!object_property_set_int(OBJECT(&s->sec_resp_splitter), 668 "num-lines", 3, errp)) { 669 return; 670 } 671 if (!qdev_realize(DEVICE(&s->sec_resp_splitter), NULL, errp)) { 672 return; 673 } 674 dev_splitter = DEVICE(&s->sec_resp_splitter); 675 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, 676 qdev_get_gpio_in(dev_splitter, 0)); 677 678 /* Each SRAM bank lives behind its own Memory Protection Controller */ 679 for (i = 0; i < info->sram_banks; i++) { 680 char *ramname = g_strdup_printf("armsse.sram%d", i); 681 SysBusDevice *sbd_mpc; 682 uint32_t sram_bank_size = 1 << s->sram_addr_width; 683 684 memory_region_init_ram(&s->sram[i], NULL, ramname, 685 sram_bank_size, &err); 686 g_free(ramname); 687 if (err) { 688 error_propagate(errp, err); 689 return; 690 } 691 object_property_set_link(OBJECT(&s->mpc[i]), "downstream", 692 OBJECT(&s->sram[i]), &error_abort); 693 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mpc[i]), errp)) { 694 return; 695 } 696 /* Map the upstream end of the MPC into the right place... */ 697 sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); 698 memory_region_add_subregion(&s->container, 699 0x20000000 + i * sram_bank_size, 700 sysbus_mmio_get_region(sbd_mpc, 1)); 701 /* ...and its register interface */ 702 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, 703 sysbus_mmio_get_region(sbd_mpc, 0)); 704 } 705 706 /* We must OR together lines from the MPC splitters to go to the NVIC */ 707 if (!object_property_set_int(OBJECT(&s->mpc_irq_orgate), "num-lines", 708 IOTS_NUM_EXP_MPC + info->sram_banks, 709 errp)) { 710 return; 711 } 712 if (!qdev_realize(DEVICE(&s->mpc_irq_orgate), NULL, errp)) { 713 return; 714 } 715 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, 716 armsse_get_common_irq_in(s, 9)); 717 718 /* Devices behind APB PPC0: 719 * 0x40000000: timer0 720 * 0x40001000: timer1 721 * 0x40002000: dual timer 722 * 0x40003000: MHU0 (SSE-200 only) 723 * 0x40004000: MHU1 (SSE-200 only) 724 * We must configure and realize each downstream device and connect 725 * it to the appropriate PPC port; then we can realize the PPC and 726 * map its upstream ends to the right place in the container. 727 */ 728 qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); 729 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { 730 return; 731 } 732 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, 733 armsse_get_common_irq_in(s, 3)); 734 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); 735 object_property_set_link(OBJECT(&s->apb_ppc0), "port[0]", OBJECT(mr), 736 &error_abort); 737 738 qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); 739 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { 740 return; 741 } 742 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, 743 armsse_get_common_irq_in(s, 4)); 744 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); 745 object_property_set_link(OBJECT(&s->apb_ppc0), "port[1]", OBJECT(mr), 746 &error_abort); 747 748 qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); 749 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { 750 return; 751 } 752 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dualtimer), 0, 753 armsse_get_common_irq_in(s, 5)); 754 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); 755 object_property_set_link(OBJECT(&s->apb_ppc0), "port[2]", OBJECT(mr), 756 &error_abort); 757 758 if (info->has_mhus) { 759 /* 760 * An SSE-200 with only one CPU should have only one MHU created, 761 * with the region where the second MHU usually is being RAZ/WI. 762 * We don't implement that SSE-200 config; if we want to support 763 * it then this code needs to be enhanced to handle creating the 764 * RAZ/WI region instead of the second MHU. 765 */ 766 assert(info->num_cpus == ARRAY_SIZE(s->mhu)); 767 768 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { 769 char *port; 770 int cpunum; 771 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]); 772 773 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mhu[i]), errp)) { 774 return; 775 } 776 port = g_strdup_printf("port[%d]", i + 3); 777 mr = sysbus_mmio_get_region(mhu_sbd, 0); 778 object_property_set_link(OBJECT(&s->apb_ppc0), port, OBJECT(mr), 779 &error_abort); 780 g_free(port); 781 782 /* 783 * Each MHU has an irq line for each CPU: 784 * MHU 0 irq line 0 -> CPU 0 IRQ 6 785 * MHU 0 irq line 1 -> CPU 1 IRQ 6 786 * MHU 1 irq line 0 -> CPU 0 IRQ 7 787 * MHU 1 irq line 1 -> CPU 1 IRQ 7 788 */ 789 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 790 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 791 792 sysbus_connect_irq(mhu_sbd, cpunum, 793 qdev_get_gpio_in(cpudev, 6 + i)); 794 } 795 } 796 } 797 798 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc0), errp)) { 799 return; 800 } 801 802 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); 803 dev_apb_ppc0 = DEVICE(&s->apb_ppc0); 804 805 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); 806 memory_region_add_subregion(&s->container, 0x40000000, mr); 807 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); 808 memory_region_add_subregion(&s->container, 0x40001000, mr); 809 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); 810 memory_region_add_subregion(&s->container, 0x40002000, mr); 811 if (info->has_mhus) { 812 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3); 813 memory_region_add_subregion(&s->container, 0x40003000, mr); 814 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4); 815 memory_region_add_subregion(&s->container, 0x40004000, mr); 816 } 817 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { 818 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, 819 qdev_get_gpio_in_named(dev_apb_ppc0, 820 "cfg_nonsec", i)); 821 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, 822 qdev_get_gpio_in_named(dev_apb_ppc0, 823 "cfg_ap", i)); 824 } 825 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, 826 qdev_get_gpio_in_named(dev_apb_ppc0, 827 "irq_enable", 0)); 828 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, 829 qdev_get_gpio_in_named(dev_apb_ppc0, 830 "irq_clear", 0)); 831 qdev_connect_gpio_out(dev_splitter, 0, 832 qdev_get_gpio_in_named(dev_apb_ppc0, 833 "cfg_sec_resp", 0)); 834 835 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external 836 * ones) are sent individually to the security controller, and also 837 * ORed together to give a single combined PPC interrupt to the NVIC. 838 */ 839 if (!object_property_set_int(OBJECT(&s->ppc_irq_orgate), 840 "num-lines", NUM_PPCS, errp)) { 841 return; 842 } 843 if (!qdev_realize(DEVICE(&s->ppc_irq_orgate), NULL, errp)) { 844 return; 845 } 846 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, 847 armsse_get_common_irq_in(s, 10)); 848 849 /* 850 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): 851 * private per-CPU region (all these devices are SSE-200 only): 852 * 0x50010000: L1 icache control registers 853 * 0x50011000: CPUSECCTRL (CPU local security control registers) 854 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block 855 */ 856 if (info->has_cachectrl) { 857 for (i = 0; i < info->num_cpus; i++) { 858 char *name = g_strdup_printf("cachectrl%d", i); 859 MemoryRegion *mr; 860 861 qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); 862 g_free(name); 863 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); 864 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cachectrl[i]), errp)) { 865 return; 866 } 867 868 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); 869 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); 870 } 871 } 872 if (info->has_cpusecctrl) { 873 for (i = 0; i < info->num_cpus; i++) { 874 char *name = g_strdup_printf("CPUSECCTRL%d", i); 875 MemoryRegion *mr; 876 877 qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); 878 g_free(name); 879 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); 880 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpusecctrl[i]), errp)) { 881 return; 882 } 883 884 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); 885 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); 886 } 887 } 888 if (info->has_cpuid) { 889 for (i = 0; i < info->num_cpus; i++) { 890 MemoryRegion *mr; 891 892 qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); 893 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpuid[i]), errp)) { 894 return; 895 } 896 897 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); 898 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); 899 } 900 } 901 902 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */ 903 /* Devices behind APB PPC1: 904 * 0x4002f000: S32K timer 905 */ 906 qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); 907 if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { 908 return; 909 } 910 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, 911 armsse_get_common_irq_in(s, 2)); 912 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); 913 object_property_set_link(OBJECT(&s->apb_ppc1), "port[0]", OBJECT(mr), 914 &error_abort); 915 916 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc1), errp)) { 917 return; 918 } 919 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); 920 memory_region_add_subregion(&s->container, 0x4002f000, mr); 921 922 dev_apb_ppc1 = DEVICE(&s->apb_ppc1); 923 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, 924 qdev_get_gpio_in_named(dev_apb_ppc1, 925 "cfg_nonsec", 0)); 926 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, 927 qdev_get_gpio_in_named(dev_apb_ppc1, 928 "cfg_ap", 0)); 929 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, 930 qdev_get_gpio_in_named(dev_apb_ppc1, 931 "irq_enable", 0)); 932 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, 933 qdev_get_gpio_in_named(dev_apb_ppc1, 934 "irq_clear", 0)); 935 qdev_connect_gpio_out(dev_splitter, 1, 936 qdev_get_gpio_in_named(dev_apb_ppc1, 937 "cfg_sec_resp", 0)); 938 939 if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION", 940 info->sys_version, errp)) { 941 return; 942 } 943 if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG", 944 armsse_sys_config_value(s, info), errp)) { 945 return; 946 } 947 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), errp)) { 948 return; 949 } 950 /* System information registers */ 951 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); 952 /* System control registers */ 953 object_property_set_int(OBJECT(&s->sysctl), "SYS_VERSION", 954 info->sys_version, &error_abort); 955 object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST", 956 info->cpuwait_rst, &error_abort); 957 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST", 958 s->init_svtor, &error_abort); 959 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST", 960 s->init_svtor, &error_abort); 961 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysctl), errp)) { 962 return; 963 } 964 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); 965 966 if (info->has_ppus) { 967 /* CPUnCORE_PPU for each CPU */ 968 for (i = 0; i < info->num_cpus; i++) { 969 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 970 971 map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); 972 /* 973 * We don't support CPU debug so don't create the 974 * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. 975 */ 976 g_free(name); 977 } 978 map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); 979 980 for (i = 0; i < info->sram_banks; i++) { 981 char *name = g_strdup_printf("RAM%d_PPU", i); 982 983 map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); 984 g_free(name); 985 } 986 } 987 988 /* This OR gate wires together outputs from the secure watchdogs to NMI */ 989 if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2, 990 errp)) { 991 return; 992 } 993 if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) { 994 return; 995 } 996 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, 997 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); 998 999 qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); 1000 if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { 1001 return; 1002 } 1003 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 1004 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 0)); 1005 sysbus_mmio_map(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 0x5002e000); 1006 1007 /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ 1008 1009 qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); 1010 if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { 1011 return; 1012 } 1013 sysbus_connect_irq(SYS_BUS_DEVICE(&s->nswatchdog), 0, 1014 armsse_get_common_irq_in(s, 1)); 1015 sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); 1016 1017 qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); 1018 if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { 1019 return; 1020 } 1021 sysbus_connect_irq(SYS_BUS_DEVICE(&s->swatchdog), 0, 1022 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 1)); 1023 sysbus_mmio_map(SYS_BUS_DEVICE(&s->swatchdog), 0, 0x50081000); 1024 1025 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 1026 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); 1027 1028 if (!object_property_set_int(splitter, "num-lines", 2, errp)) { 1029 return; 1030 } 1031 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1032 return; 1033 } 1034 } 1035 1036 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { 1037 char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); 1038 1039 armsse_forward_ppc(s, ppcname, i); 1040 g_free(ppcname); 1041 } 1042 1043 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { 1044 char *ppcname = g_strdup_printf("apb_ppcexp%d", i); 1045 1046 armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); 1047 g_free(ppcname); 1048 } 1049 1050 for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { 1051 /* Wire up IRQ splitter for internal PPCs */ 1052 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); 1053 char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", 1054 i - NUM_EXTERNAL_PPCS); 1055 TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; 1056 1057 qdev_connect_gpio_out(devs, 0, 1058 qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); 1059 qdev_connect_gpio_out(devs, 1, 1060 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); 1061 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, 1062 qdev_get_gpio_in(devs, 0)); 1063 g_free(gpioname); 1064 } 1065 1066 /* Wire up the splitters for the MPC IRQs */ 1067 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 1068 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 1069 DeviceState *dev_splitter = DEVICE(splitter); 1070 1071 if (!object_property_set_int(OBJECT(splitter), "num-lines", 2, 1072 errp)) { 1073 return; 1074 } 1075 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1076 return; 1077 } 1078 1079 if (i < IOTS_NUM_EXP_MPC) { 1080 /* Splitter input is from GPIO input line */ 1081 s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0); 1082 qdev_connect_gpio_out(dev_splitter, 0, 1083 qdev_get_gpio_in_named(dev_secctl, 1084 "mpcexp_status", i)); 1085 } else { 1086 /* Splitter input is from our own MPC */ 1087 qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]), 1088 "irq", 0, 1089 qdev_get_gpio_in(dev_splitter, 0)); 1090 qdev_connect_gpio_out(dev_splitter, 0, 1091 qdev_get_gpio_in_named(dev_secctl, 1092 "mpc_status", 1093 i - IOTS_NUM_EXP_MPC)); 1094 } 1095 1096 qdev_connect_gpio_out(dev_splitter, 1, 1097 qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i)); 1098 } 1099 /* Create GPIO inputs which will pass the line state for our 1100 * mpcexp_irq inputs to the correct splitter devices. 1101 */ 1102 qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status", 1103 IOTS_NUM_EXP_MPC); 1104 1105 armsse_forward_sec_resp_cfg(s); 1106 1107 /* Forward the MSC related signals */ 1108 qdev_pass_gpios(dev_secctl, dev, "mscexp_status"); 1109 qdev_pass_gpios(dev_secctl, dev, "mscexp_clear"); 1110 qdev_pass_gpios(dev_secctl, dev, "mscexp_ns"); 1111 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, 1112 armsse_get_common_irq_in(s, 11)); 1113 1114 /* 1115 * Expose our container region to the board model; this corresponds 1116 * to the AHB Slave Expansion ports which allow bus master devices 1117 * (eg DMA controllers) in the board model to make transactions into 1118 * devices in the ARMSSE. 1119 */ 1120 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); 1121 1122 /* Set initial system_clock_scale from MAINCLK */ 1123 armsse_mainclk_update(s); 1124 } 1125 1126 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, 1127 int *iregion, bool *exempt, bool *ns, bool *nsc) 1128 { 1129 /* 1130 * For ARMSSE systems the IDAU responses are simple logical functions 1131 * of the address bits. The NSC attribute is guest-adjustable via the 1132 * NSCCFG register in the security controller. 1133 */ 1134 ARMSSE *s = ARM_SSE(ii); 1135 int region = extract32(address, 28, 4); 1136 1137 *ns = !(region & 1); 1138 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); 1139 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1140 *exempt = (address & 0xeff00000) == 0xe0000000; 1141 *iregion = region; 1142 } 1143 1144 static const VMStateDescription armsse_vmstate = { 1145 .name = "iotkit", 1146 .version_id = 2, 1147 .minimum_version_id = 2, 1148 .fields = (VMStateField[]) { 1149 VMSTATE_CLOCK(mainclk, ARMSSE), 1150 VMSTATE_CLOCK(s32kclk, ARMSSE), 1151 VMSTATE_UINT32(nsccfg, ARMSSE), 1152 VMSTATE_END_OF_LIST() 1153 } 1154 }; 1155 1156 static void armsse_reset(DeviceState *dev) 1157 { 1158 ARMSSE *s = ARM_SSE(dev); 1159 1160 s->nsccfg = 0; 1161 } 1162 1163 static void armsse_class_init(ObjectClass *klass, void *data) 1164 { 1165 DeviceClass *dc = DEVICE_CLASS(klass); 1166 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); 1167 ARMSSEClass *asc = ARM_SSE_CLASS(klass); 1168 const ARMSSEInfo *info = data; 1169 1170 dc->realize = armsse_realize; 1171 dc->vmsd = &armsse_vmstate; 1172 device_class_set_props(dc, info->props); 1173 dc->reset = armsse_reset; 1174 iic->check = armsse_idau_check; 1175 asc->info = info; 1176 } 1177 1178 static const TypeInfo armsse_info = { 1179 .name = TYPE_ARM_SSE, 1180 .parent = TYPE_SYS_BUS_DEVICE, 1181 .instance_size = sizeof(ARMSSE), 1182 .class_size = sizeof(ARMSSEClass), 1183 .instance_init = armsse_init, 1184 .abstract = true, 1185 .interfaces = (InterfaceInfo[]) { 1186 { TYPE_IDAU_INTERFACE }, 1187 { } 1188 } 1189 }; 1190 1191 static void armsse_register_types(void) 1192 { 1193 int i; 1194 1195 type_register_static(&armsse_info); 1196 1197 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) { 1198 TypeInfo ti = { 1199 .name = armsse_variants[i].name, 1200 .parent = TYPE_ARM_SSE, 1201 .class_init = armsse_class_init, 1202 .class_data = (void *)&armsse_variants[i], 1203 }; 1204 type_register(&ti); 1205 } 1206 } 1207 1208 type_init(armsse_register_types); 1209