1 /* 2 * Arm SSE (Subsystems for Embedded): IoTKit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qemu/bitops.h" 16 #include "qapi/error.h" 17 #include "trace.h" 18 #include "hw/sysbus.h" 19 #include "hw/registerfields.h" 20 #include "hw/arm/armsse.h" 21 #include "hw/arm/boot.h" 22 #include "hw/irq.h" 23 24 /* Format of the System Information block SYS_CONFIG register */ 25 typedef enum SysConfigFormat { 26 IoTKitFormat, 27 SSE200Format, 28 } SysConfigFormat; 29 30 struct ARMSSEInfo { 31 const char *name; 32 int sram_banks; 33 int num_cpus; 34 uint32_t sys_version; 35 uint32_t cpuwait_rst; 36 SysConfigFormat sys_config_format; 37 bool has_mhus; 38 bool has_ppus; 39 bool has_cachectrl; 40 bool has_cpusecctrl; 41 bool has_cpuid; 42 Property *props; 43 }; 44 45 static Property iotkit_properties[] = { 46 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 47 MemoryRegion *), 48 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 49 DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), 50 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 51 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 52 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), 53 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), 54 DEFINE_PROP_END_OF_LIST() 55 }; 56 57 static Property armsse_properties[] = { 58 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 59 MemoryRegion *), 60 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 61 DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), 62 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 63 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 64 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), 65 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), 66 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), 67 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), 68 DEFINE_PROP_END_OF_LIST() 69 }; 70 71 static const ARMSSEInfo armsse_variants[] = { 72 { 73 .name = TYPE_IOTKIT, 74 .sram_banks = 1, 75 .num_cpus = 1, 76 .sys_version = 0x41743, 77 .cpuwait_rst = 0, 78 .sys_config_format = IoTKitFormat, 79 .has_mhus = false, 80 .has_ppus = false, 81 .has_cachectrl = false, 82 .has_cpusecctrl = false, 83 .has_cpuid = false, 84 .props = iotkit_properties, 85 }, 86 { 87 .name = TYPE_SSE200, 88 .sram_banks = 4, 89 .num_cpus = 2, 90 .sys_version = 0x22041743, 91 .cpuwait_rst = 2, 92 .sys_config_format = SSE200Format, 93 .has_mhus = true, 94 .has_ppus = true, 95 .has_cachectrl = true, 96 .has_cpusecctrl = true, 97 .has_cpuid = true, 98 .props = armsse_properties, 99 }, 100 }; 101 102 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) 103 { 104 /* Return the SYS_CONFIG value for this SSE */ 105 uint32_t sys_config; 106 107 switch (info->sys_config_format) { 108 case IoTKitFormat: 109 sys_config = 0; 110 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 111 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); 112 break; 113 case SSE200Format: 114 sys_config = 0; 115 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 116 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 117 sys_config = deposit32(sys_config, 24, 4, 2); 118 if (info->num_cpus > 1) { 119 sys_config = deposit32(sys_config, 10, 1, 1); 120 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1); 121 sys_config = deposit32(sys_config, 28, 4, 2); 122 } 123 break; 124 default: 125 g_assert_not_reached(); 126 } 127 return sys_config; 128 } 129 130 /* Clock frequency in HZ of the 32KHz "slow clock" */ 131 #define S32KCLK (32 * 1000) 132 133 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ 134 static bool irq_is_common[32] = { 135 [0 ... 5] = true, 136 /* 6, 7: per-CPU MHU interrupts */ 137 [8 ... 12] = true, 138 /* 13: per-CPU icache interrupt */ 139 /* 14: reserved */ 140 [15 ... 20] = true, 141 /* 21: reserved */ 142 [22 ... 26] = true, 143 /* 27: reserved */ 144 /* 28, 29: per-CPU CTI interrupts */ 145 /* 30, 31: reserved */ 146 }; 147 148 /* 149 * Create an alias region in @container of @size bytes starting at @base 150 * which mirrors the memory starting at @orig. 151 */ 152 static void make_alias(ARMSSE *s, MemoryRegion *mr, MemoryRegion *container, 153 const char *name, hwaddr base, hwaddr size, hwaddr orig) 154 { 155 memory_region_init_alias(mr, NULL, name, container, orig, size); 156 /* The alias is even lower priority than unimplemented_device regions */ 157 memory_region_add_subregion_overlap(container, base, mr, -1500); 158 } 159 160 static void irq_status_forwarder(void *opaque, int n, int level) 161 { 162 qemu_irq destirq = opaque; 163 164 qemu_set_irq(destirq, level); 165 } 166 167 static void nsccfg_handler(void *opaque, int n, int level) 168 { 169 ARMSSE *s = ARMSSE(opaque); 170 171 s->nsccfg = level; 172 } 173 174 static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) 175 { 176 /* Each of the 4 AHB and 4 APB PPCs that might be present in a 177 * system using the ARMSSE has a collection of control lines which 178 * are provided by the security controller and which we want to 179 * expose as control lines on the ARMSSE device itself, so the 180 * code using the ARMSSE can wire them up to the PPCs. 181 */ 182 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; 183 DeviceState *armssedev = DEVICE(s); 184 DeviceState *dev_secctl = DEVICE(&s->secctl); 185 DeviceState *dev_splitter = DEVICE(splitter); 186 char *name; 187 188 name = g_strdup_printf("%s_nonsec", ppcname); 189 qdev_pass_gpios(dev_secctl, armssedev, name); 190 g_free(name); 191 name = g_strdup_printf("%s_ap", ppcname); 192 qdev_pass_gpios(dev_secctl, armssedev, name); 193 g_free(name); 194 name = g_strdup_printf("%s_irq_enable", ppcname); 195 qdev_pass_gpios(dev_secctl, armssedev, name); 196 g_free(name); 197 name = g_strdup_printf("%s_irq_clear", ppcname); 198 qdev_pass_gpios(dev_secctl, armssedev, name); 199 g_free(name); 200 201 /* irq_status is a little more tricky, because we need to 202 * split it so we can send it both to the security controller 203 * and to our OR gate for the NVIC interrupt line. 204 * Connect up the splitter's outputs, and create a GPIO input 205 * which will pass the line state to the input splitter. 206 */ 207 name = g_strdup_printf("%s_irq_status", ppcname); 208 qdev_connect_gpio_out(dev_splitter, 0, 209 qdev_get_gpio_in_named(dev_secctl, 210 name, 0)); 211 qdev_connect_gpio_out(dev_splitter, 1, 212 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); 213 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); 214 qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder, 215 s->irq_status_in[ppcnum], name, 1); 216 g_free(name); 217 } 218 219 static void armsse_forward_sec_resp_cfg(ARMSSE *s) 220 { 221 /* Forward the 3rd output from the splitter device as a 222 * named GPIO output of the armsse object. 223 */ 224 DeviceState *dev = DEVICE(s); 225 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); 226 227 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); 228 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, 229 s->sec_resp_cfg, 1); 230 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); 231 } 232 233 static void armsse_init(Object *obj) 234 { 235 ARMSSE *s = ARMSSE(obj); 236 ARMSSEClass *asc = ARMSSE_GET_CLASS(obj); 237 const ARMSSEInfo *info = asc->info; 238 int i; 239 240 assert(info->sram_banks <= MAX_SRAM_BANKS); 241 assert(info->num_cpus <= SSE_MAX_CPUS); 242 243 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); 244 245 for (i = 0; i < info->num_cpus; i++) { 246 /* 247 * We put each CPU in its own cluster as they are logically 248 * distinct and may be configured differently. 249 */ 250 char *name; 251 252 name = g_strdup_printf("cluster%d", i); 253 object_initialize_child(obj, name, &s->cluster[i], 254 sizeof(s->cluster[i]), TYPE_CPU_CLUSTER, 255 &error_abort, NULL); 256 qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); 257 g_free(name); 258 259 name = g_strdup_printf("armv7m%d", i); 260 sysbus_init_child_obj(OBJECT(&s->cluster[i]), name, 261 &s->armv7m[i], sizeof(s->armv7m), TYPE_ARMV7M); 262 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", 263 ARM_CPU_TYPE_NAME("cortex-m33")); 264 g_free(name); 265 name = g_strdup_printf("arm-sse-cpu-container%d", i); 266 memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); 267 g_free(name); 268 if (i > 0) { 269 name = g_strdup_printf("arm-sse-container-alias%d", i); 270 memory_region_init_alias(&s->container_alias[i - 1], obj, 271 name, &s->container, 0, UINT64_MAX); 272 g_free(name); 273 } 274 } 275 276 sysbus_init_child_obj(obj, "secctl", &s->secctl, sizeof(s->secctl), 277 TYPE_IOTKIT_SECCTL); 278 sysbus_init_child_obj(obj, "apb-ppc0", &s->apb_ppc0, sizeof(s->apb_ppc0), 279 TYPE_TZ_PPC); 280 sysbus_init_child_obj(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1), 281 TYPE_TZ_PPC); 282 for (i = 0; i < info->sram_banks; i++) { 283 char *name = g_strdup_printf("mpc%d", i); 284 sysbus_init_child_obj(obj, name, &s->mpc[i], 285 sizeof(s->mpc[i]), TYPE_TZ_MPC); 286 g_free(name); 287 } 288 object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate, 289 sizeof(s->mpc_irq_orgate), TYPE_OR_IRQ, 290 &error_abort, NULL); 291 292 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 293 char *name = g_strdup_printf("mpc-irq-splitter-%d", i); 294 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 295 296 object_initialize_child(obj, name, splitter, sizeof(*splitter), 297 TYPE_SPLIT_IRQ, &error_abort, NULL); 298 g_free(name); 299 } 300 sysbus_init_child_obj(obj, "timer0", &s->timer0, sizeof(s->timer0), 301 TYPE_CMSDK_APB_TIMER); 302 sysbus_init_child_obj(obj, "timer1", &s->timer1, sizeof(s->timer1), 303 TYPE_CMSDK_APB_TIMER); 304 sysbus_init_child_obj(obj, "s32ktimer", &s->s32ktimer, sizeof(s->s32ktimer), 305 TYPE_CMSDK_APB_TIMER); 306 sysbus_init_child_obj(obj, "dualtimer", &s->dualtimer, sizeof(s->dualtimer), 307 TYPE_CMSDK_APB_DUALTIMER); 308 sysbus_init_child_obj(obj, "s32kwatchdog", &s->s32kwatchdog, 309 sizeof(s->s32kwatchdog), TYPE_CMSDK_APB_WATCHDOG); 310 sysbus_init_child_obj(obj, "nswatchdog", &s->nswatchdog, 311 sizeof(s->nswatchdog), TYPE_CMSDK_APB_WATCHDOG); 312 sysbus_init_child_obj(obj, "swatchdog", &s->swatchdog, 313 sizeof(s->swatchdog), TYPE_CMSDK_APB_WATCHDOG); 314 sysbus_init_child_obj(obj, "armsse-sysctl", &s->sysctl, 315 sizeof(s->sysctl), TYPE_IOTKIT_SYSCTL); 316 sysbus_init_child_obj(obj, "armsse-sysinfo", &s->sysinfo, 317 sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO); 318 if (info->has_mhus) { 319 sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]), 320 TYPE_ARMSSE_MHU); 321 sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]), 322 TYPE_ARMSSE_MHU); 323 } 324 if (info->has_ppus) { 325 for (i = 0; i < info->num_cpus; i++) { 326 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 327 int ppuidx = CPU0CORE_PPU + i; 328 329 sysbus_init_child_obj(obj, name, &s->ppu[ppuidx], 330 sizeof(s->ppu[ppuidx]), 331 TYPE_UNIMPLEMENTED_DEVICE); 332 g_free(name); 333 } 334 sysbus_init_child_obj(obj, "DBG_PPU", &s->ppu[DBG_PPU], 335 sizeof(s->ppu[DBG_PPU]), 336 TYPE_UNIMPLEMENTED_DEVICE); 337 for (i = 0; i < info->sram_banks; i++) { 338 char *name = g_strdup_printf("RAM%d_PPU", i); 339 int ppuidx = RAM0_PPU + i; 340 341 sysbus_init_child_obj(obj, name, &s->ppu[ppuidx], 342 sizeof(s->ppu[ppuidx]), 343 TYPE_UNIMPLEMENTED_DEVICE); 344 g_free(name); 345 } 346 } 347 if (info->has_cachectrl) { 348 for (i = 0; i < info->num_cpus; i++) { 349 char *name = g_strdup_printf("cachectrl%d", i); 350 351 sysbus_init_child_obj(obj, name, &s->cachectrl[i], 352 sizeof(s->cachectrl[i]), 353 TYPE_UNIMPLEMENTED_DEVICE); 354 g_free(name); 355 } 356 } 357 if (info->has_cpusecctrl) { 358 for (i = 0; i < info->num_cpus; i++) { 359 char *name = g_strdup_printf("cpusecctrl%d", i); 360 361 sysbus_init_child_obj(obj, name, &s->cpusecctrl[i], 362 sizeof(s->cpusecctrl[i]), 363 TYPE_UNIMPLEMENTED_DEVICE); 364 g_free(name); 365 } 366 } 367 if (info->has_cpuid) { 368 for (i = 0; i < info->num_cpus; i++) { 369 char *name = g_strdup_printf("cpuid%d", i); 370 371 sysbus_init_child_obj(obj, name, &s->cpuid[i], 372 sizeof(s->cpuid[i]), 373 TYPE_ARMSSE_CPUID); 374 g_free(name); 375 } 376 } 377 object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, 378 sizeof(s->nmi_orgate), TYPE_OR_IRQ, 379 &error_abort, NULL); 380 object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, 381 sizeof(s->ppc_irq_orgate), TYPE_OR_IRQ, 382 &error_abort, NULL); 383 object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter, 384 sizeof(s->sec_resp_splitter), TYPE_SPLIT_IRQ, 385 &error_abort, NULL); 386 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 387 char *name = g_strdup_printf("ppc-irq-splitter-%d", i); 388 SplitIRQ *splitter = &s->ppc_irq_splitter[i]; 389 390 object_initialize_child(obj, name, splitter, sizeof(*splitter), 391 TYPE_SPLIT_IRQ, &error_abort, NULL); 392 g_free(name); 393 } 394 if (info->num_cpus > 1) { 395 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 396 if (irq_is_common[i]) { 397 char *name = g_strdup_printf("cpu-irq-splitter%d", i); 398 SplitIRQ *splitter = &s->cpu_irq_splitter[i]; 399 400 object_initialize_child(obj, name, splitter, sizeof(*splitter), 401 TYPE_SPLIT_IRQ, &error_abort, NULL); 402 g_free(name); 403 } 404 } 405 } 406 } 407 408 static void armsse_exp_irq(void *opaque, int n, int level) 409 { 410 qemu_irq *irqarray = opaque; 411 412 qemu_set_irq(irqarray[n], level); 413 } 414 415 static void armsse_mpcexp_status(void *opaque, int n, int level) 416 { 417 ARMSSE *s = ARMSSE(opaque); 418 qemu_set_irq(s->mpcexp_status_in[n], level); 419 } 420 421 static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno) 422 { 423 /* 424 * Return a qemu_irq which can be used to signal IRQ n to 425 * all CPUs in the SSE. 426 */ 427 ARMSSEClass *asc = ARMSSE_GET_CLASS(s); 428 const ARMSSEInfo *info = asc->info; 429 430 assert(irq_is_common[irqno]); 431 432 if (info->num_cpus == 1) { 433 /* Only one CPU -- just connect directly to it */ 434 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); 435 } else { 436 /* Connect to the splitter which feeds all CPUs */ 437 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); 438 } 439 } 440 441 static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) 442 { 443 /* Map a PPU unimplemented device stub */ 444 DeviceState *dev = DEVICE(&s->ppu[ppuidx]); 445 446 qdev_prop_set_string(dev, "name", name); 447 qdev_prop_set_uint64(dev, "size", 0x1000); 448 qdev_init_nofail(dev); 449 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); 450 } 451 452 static void armsse_realize(DeviceState *dev, Error **errp) 453 { 454 ARMSSE *s = ARMSSE(dev); 455 ARMSSEClass *asc = ARMSSE_GET_CLASS(dev); 456 const ARMSSEInfo *info = asc->info; 457 int i; 458 MemoryRegion *mr; 459 Error *err = NULL; 460 SysBusDevice *sbd_apb_ppc0; 461 SysBusDevice *sbd_secctl; 462 DeviceState *dev_apb_ppc0; 463 DeviceState *dev_apb_ppc1; 464 DeviceState *dev_secctl; 465 DeviceState *dev_splitter; 466 uint32_t addr_width_max; 467 468 if (!s->board_memory) { 469 error_setg(errp, "memory property was not set"); 470 return; 471 } 472 473 if (!s->mainclk_frq) { 474 error_setg(errp, "MAINCLK property was not set"); 475 return; 476 } 477 478 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ 479 assert(is_power_of_2(info->sram_banks)); 480 addr_width_max = 24 - ctz32(info->sram_banks); 481 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { 482 error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d", 483 addr_width_max); 484 return; 485 } 486 487 /* Handling of which devices should be available only to secure 488 * code is usually done differently for M profile than for A profile. 489 * Instead of putting some devices only into the secure address space, 490 * devices exist in both address spaces but with hard-wired security 491 * permissions that will cause the CPU to fault for non-secure accesses. 492 * 493 * The ARMSSE has an IDAU (Implementation Defined Access Unit), 494 * which specifies hard-wired security permissions for different 495 * areas of the physical address space. For the ARMSSE IDAU, the 496 * top 4 bits of the physical address are the IDAU region ID, and 497 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS 498 * region, otherwise it is an S region. 499 * 500 * The various devices and RAMs are generally all mapped twice, 501 * once into a region that the IDAU defines as secure and once 502 * into a non-secure region. They sit behind either a Memory 503 * Protection Controller (for RAM) or a Peripheral Protection 504 * Controller (for devices), which allow a more fine grained 505 * configuration of whether non-secure accesses are permitted. 506 * 507 * (The other place that guest software can configure security 508 * permissions is in the architected SAU (Security Attribution 509 * Unit), which is entirely inside the CPU. The IDAU can upgrade 510 * the security attributes for a region to more restrictive than 511 * the SAU specifies, but cannot downgrade them.) 512 * 513 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff 514 * 0x20000000..0x2007ffff 32KB FPGA block RAM 515 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff 516 * 0x40000000..0x4000ffff base peripheral region 1 517 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) 518 * 0x40020000..0x4002ffff system control element peripherals 519 * 0x40080000..0x400fffff base peripheral region 2 520 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff 521 */ 522 523 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); 524 525 for (i = 0; i < info->num_cpus; i++) { 526 DeviceState *cpudev = DEVICE(&s->armv7m[i]); 527 Object *cpuobj = OBJECT(&s->armv7m[i]); 528 int j; 529 char *gpioname; 530 531 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32); 532 /* 533 * In real hardware the initial Secure VTOR is set from the INITSVTOR* 534 * registers in the IoT Kit System Control Register block. In QEMU 535 * we set the initial value here, and also the reset value of the 536 * sysctl register, from this object's QOM init-svtor property. 537 * If the guest changes the INITSVTOR* registers at runtime then the 538 * code in iotkit-sysctl.c will update the CPU init-svtor property 539 * (which will then take effect on the next CPU warm-reset). 540 * 541 * Note that typically a board using the SSE-200 will have a system 542 * control processor whose boot firmware initializes the INITSVTOR* 543 * registers before powering up the CPUs. QEMU doesn't emulate 544 * the control processor, so instead we behave in the way that the 545 * firmware does: the initial value should be set by the board code 546 * (using the init-svtor property on the ARMSSE object) to match 547 * whatever its firmware does. 548 */ 549 qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); 550 /* 551 * CPUs start powered down if the corresponding bit in the CPUWAIT 552 * register is 1. In real hardware the CPUWAIT register reset value is 553 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and 554 * CPUWAIT1_RST parameters), but since all the boards we care about 555 * start CPU0 and leave CPU1 powered off, we hard-code that in 556 * info->cpuwait_rst for now. We can add QOM properties for this 557 * later if necessary. 558 */ 559 if (extract32(info->cpuwait_rst, i, 1)) { 560 object_property_set_bool(cpuobj, true, "start-powered-off", &err); 561 if (err) { 562 error_propagate(errp, err); 563 return; 564 } 565 } 566 if (!s->cpu_fpu[i]) { 567 object_property_set_bool(cpuobj, false, "vfp", &err); 568 if (err) { 569 error_propagate(errp, err); 570 return; 571 } 572 } 573 if (!s->cpu_dsp[i]) { 574 object_property_set_bool(cpuobj, false, "dsp", &err); 575 if (err) { 576 error_propagate(errp, err); 577 return; 578 } 579 } 580 581 if (i > 0) { 582 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 583 &s->container_alias[i - 1], -1); 584 } else { 585 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 586 &s->container, -1); 587 } 588 object_property_set_link(cpuobj, OBJECT(&s->cpu_container[i]), 589 "memory", &err); 590 if (err) { 591 error_propagate(errp, err); 592 return; 593 } 594 object_property_set_link(cpuobj, OBJECT(s), "idau", &err); 595 if (err) { 596 error_propagate(errp, err); 597 return; 598 } 599 object_property_set_bool(cpuobj, true, "realized", &err); 600 if (err) { 601 error_propagate(errp, err); 602 return; 603 } 604 /* 605 * The cluster must be realized after the armv7m container, as 606 * the container's CPU object is only created on realize, and the 607 * CPU must exist and have been parented into the cluster before 608 * the cluster is realized. 609 */ 610 object_property_set_bool(OBJECT(&s->cluster[i]), 611 true, "realized", &err); 612 if (err) { 613 error_propagate(errp, err); 614 return; 615 } 616 617 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ 618 s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); 619 for (j = 0; j < s->exp_numirq; j++) { 620 s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32); 621 } 622 if (i == 0) { 623 gpioname = g_strdup("EXP_IRQ"); 624 } else { 625 gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i); 626 } 627 qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq, 628 s->exp_irqs[i], 629 gpioname, s->exp_numirq); 630 g_free(gpioname); 631 } 632 633 /* Wire up the splitters that connect common IRQs to all CPUs */ 634 if (info->num_cpus > 1) { 635 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 636 if (irq_is_common[i]) { 637 Object *splitter = OBJECT(&s->cpu_irq_splitter[i]); 638 DeviceState *devs = DEVICE(splitter); 639 int cpunum; 640 641 object_property_set_int(splitter, info->num_cpus, 642 "num-lines", &err); 643 if (err) { 644 error_propagate(errp, err); 645 return; 646 } 647 object_property_set_bool(splitter, true, "realized", &err); 648 if (err) { 649 error_propagate(errp, err); 650 return; 651 } 652 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 653 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 654 655 qdev_connect_gpio_out(devs, cpunum, 656 qdev_get_gpio_in(cpudev, i)); 657 } 658 } 659 } 660 } 661 662 /* Set up the big aliases first */ 663 make_alias(s, &s->alias1, &s->container, "alias 1", 664 0x10000000, 0x10000000, 0x00000000); 665 make_alias(s, &s->alias2, &s->container, 666 "alias 2", 0x30000000, 0x10000000, 0x20000000); 667 /* The 0x50000000..0x5fffffff region is not a pure alias: it has 668 * a few extra devices that only appear there (generally the 669 * control interfaces for the protection controllers). 670 * We implement this by mapping those devices over the top of this 671 * alias MR at a higher priority. Some of the devices in this range 672 * are per-CPU, so we must put this alias in the per-cpu containers. 673 */ 674 for (i = 0; i < info->num_cpus; i++) { 675 make_alias(s, &s->alias3[i], &s->cpu_container[i], 676 "alias 3", 0x50000000, 0x10000000, 0x40000000); 677 } 678 679 /* Security controller */ 680 object_property_set_bool(OBJECT(&s->secctl), true, "realized", &err); 681 if (err) { 682 error_propagate(errp, err); 683 return; 684 } 685 sbd_secctl = SYS_BUS_DEVICE(&s->secctl); 686 dev_secctl = DEVICE(&s->secctl); 687 sysbus_mmio_map(sbd_secctl, 0, 0x50080000); 688 sysbus_mmio_map(sbd_secctl, 1, 0x40080000); 689 690 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); 691 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); 692 693 /* The sec_resp_cfg output from the security controller must be split into 694 * multiple lines, one for each of the PPCs within the ARMSSE and one 695 * that will be an output from the ARMSSE to the system. 696 */ 697 object_property_set_int(OBJECT(&s->sec_resp_splitter), 3, 698 "num-lines", &err); 699 if (err) { 700 error_propagate(errp, err); 701 return; 702 } 703 object_property_set_bool(OBJECT(&s->sec_resp_splitter), true, 704 "realized", &err); 705 if (err) { 706 error_propagate(errp, err); 707 return; 708 } 709 dev_splitter = DEVICE(&s->sec_resp_splitter); 710 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, 711 qdev_get_gpio_in(dev_splitter, 0)); 712 713 /* Each SRAM bank lives behind its own Memory Protection Controller */ 714 for (i = 0; i < info->sram_banks; i++) { 715 char *ramname = g_strdup_printf("armsse.sram%d", i); 716 SysBusDevice *sbd_mpc; 717 uint32_t sram_bank_size = 1 << s->sram_addr_width; 718 719 memory_region_init_ram(&s->sram[i], NULL, ramname, 720 sram_bank_size, &err); 721 g_free(ramname); 722 if (err) { 723 error_propagate(errp, err); 724 return; 725 } 726 object_property_set_link(OBJECT(&s->mpc[i]), OBJECT(&s->sram[i]), 727 "downstream", &err); 728 if (err) { 729 error_propagate(errp, err); 730 return; 731 } 732 object_property_set_bool(OBJECT(&s->mpc[i]), true, "realized", &err); 733 if (err) { 734 error_propagate(errp, err); 735 return; 736 } 737 /* Map the upstream end of the MPC into the right place... */ 738 sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); 739 memory_region_add_subregion(&s->container, 740 0x20000000 + i * sram_bank_size, 741 sysbus_mmio_get_region(sbd_mpc, 1)); 742 /* ...and its register interface */ 743 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, 744 sysbus_mmio_get_region(sbd_mpc, 0)); 745 } 746 747 /* We must OR together lines from the MPC splitters to go to the NVIC */ 748 object_property_set_int(OBJECT(&s->mpc_irq_orgate), 749 IOTS_NUM_EXP_MPC + info->sram_banks, 750 "num-lines", &err); 751 if (err) { 752 error_propagate(errp, err); 753 return; 754 } 755 object_property_set_bool(OBJECT(&s->mpc_irq_orgate), true, 756 "realized", &err); 757 if (err) { 758 error_propagate(errp, err); 759 return; 760 } 761 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, 762 armsse_get_common_irq_in(s, 9)); 763 764 /* Devices behind APB PPC0: 765 * 0x40000000: timer0 766 * 0x40001000: timer1 767 * 0x40002000: dual timer 768 * 0x40003000: MHU0 (SSE-200 only) 769 * 0x40004000: MHU1 (SSE-200 only) 770 * We must configure and realize each downstream device and connect 771 * it to the appropriate PPC port; then we can realize the PPC and 772 * map its upstream ends to the right place in the container. 773 */ 774 qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); 775 object_property_set_bool(OBJECT(&s->timer0), true, "realized", &err); 776 if (err) { 777 error_propagate(errp, err); 778 return; 779 } 780 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, 781 armsse_get_common_irq_in(s, 3)); 782 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); 783 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[0]", &err); 784 if (err) { 785 error_propagate(errp, err); 786 return; 787 } 788 789 qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); 790 object_property_set_bool(OBJECT(&s->timer1), true, "realized", &err); 791 if (err) { 792 error_propagate(errp, err); 793 return; 794 } 795 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, 796 armsse_get_common_irq_in(s, 4)); 797 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); 798 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[1]", &err); 799 if (err) { 800 error_propagate(errp, err); 801 return; 802 } 803 804 805 qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); 806 object_property_set_bool(OBJECT(&s->dualtimer), true, "realized", &err); 807 if (err) { 808 error_propagate(errp, err); 809 return; 810 } 811 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dualtimer), 0, 812 armsse_get_common_irq_in(s, 5)); 813 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); 814 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[2]", &err); 815 if (err) { 816 error_propagate(errp, err); 817 return; 818 } 819 820 if (info->has_mhus) { 821 /* 822 * An SSE-200 with only one CPU should have only one MHU created, 823 * with the region where the second MHU usually is being RAZ/WI. 824 * We don't implement that SSE-200 config; if we want to support 825 * it then this code needs to be enhanced to handle creating the 826 * RAZ/WI region instead of the second MHU. 827 */ 828 assert(info->num_cpus == ARRAY_SIZE(s->mhu)); 829 830 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { 831 char *port; 832 int cpunum; 833 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]); 834 835 object_property_set_bool(OBJECT(&s->mhu[i]), true, 836 "realized", &err); 837 if (err) { 838 error_propagate(errp, err); 839 return; 840 } 841 port = g_strdup_printf("port[%d]", i + 3); 842 mr = sysbus_mmio_get_region(mhu_sbd, 0); 843 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), 844 port, &err); 845 g_free(port); 846 if (err) { 847 error_propagate(errp, err); 848 return; 849 } 850 851 /* 852 * Each MHU has an irq line for each CPU: 853 * MHU 0 irq line 0 -> CPU 0 IRQ 6 854 * MHU 0 irq line 1 -> CPU 1 IRQ 6 855 * MHU 1 irq line 0 -> CPU 0 IRQ 7 856 * MHU 1 irq line 1 -> CPU 1 IRQ 7 857 */ 858 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 859 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 860 861 sysbus_connect_irq(mhu_sbd, cpunum, 862 qdev_get_gpio_in(cpudev, 6 + i)); 863 } 864 } 865 } 866 867 object_property_set_bool(OBJECT(&s->apb_ppc0), true, "realized", &err); 868 if (err) { 869 error_propagate(errp, err); 870 return; 871 } 872 873 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); 874 dev_apb_ppc0 = DEVICE(&s->apb_ppc0); 875 876 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); 877 memory_region_add_subregion(&s->container, 0x40000000, mr); 878 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); 879 memory_region_add_subregion(&s->container, 0x40001000, mr); 880 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); 881 memory_region_add_subregion(&s->container, 0x40002000, mr); 882 if (info->has_mhus) { 883 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3); 884 memory_region_add_subregion(&s->container, 0x40003000, mr); 885 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4); 886 memory_region_add_subregion(&s->container, 0x40004000, mr); 887 } 888 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { 889 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, 890 qdev_get_gpio_in_named(dev_apb_ppc0, 891 "cfg_nonsec", i)); 892 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, 893 qdev_get_gpio_in_named(dev_apb_ppc0, 894 "cfg_ap", i)); 895 } 896 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, 897 qdev_get_gpio_in_named(dev_apb_ppc0, 898 "irq_enable", 0)); 899 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, 900 qdev_get_gpio_in_named(dev_apb_ppc0, 901 "irq_clear", 0)); 902 qdev_connect_gpio_out(dev_splitter, 0, 903 qdev_get_gpio_in_named(dev_apb_ppc0, 904 "cfg_sec_resp", 0)); 905 906 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external 907 * ones) are sent individually to the security controller, and also 908 * ORed together to give a single combined PPC interrupt to the NVIC. 909 */ 910 object_property_set_int(OBJECT(&s->ppc_irq_orgate), 911 NUM_PPCS, "num-lines", &err); 912 if (err) { 913 error_propagate(errp, err); 914 return; 915 } 916 object_property_set_bool(OBJECT(&s->ppc_irq_orgate), true, 917 "realized", &err); 918 if (err) { 919 error_propagate(errp, err); 920 return; 921 } 922 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, 923 armsse_get_common_irq_in(s, 10)); 924 925 /* 926 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): 927 * private per-CPU region (all these devices are SSE-200 only): 928 * 0x50010000: L1 icache control registers 929 * 0x50011000: CPUSECCTRL (CPU local security control registers) 930 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block 931 */ 932 if (info->has_cachectrl) { 933 for (i = 0; i < info->num_cpus; i++) { 934 char *name = g_strdup_printf("cachectrl%d", i); 935 MemoryRegion *mr; 936 937 qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); 938 g_free(name); 939 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); 940 object_property_set_bool(OBJECT(&s->cachectrl[i]), true, 941 "realized", &err); 942 if (err) { 943 error_propagate(errp, err); 944 return; 945 } 946 947 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); 948 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); 949 } 950 } 951 if (info->has_cpusecctrl) { 952 for (i = 0; i < info->num_cpus; i++) { 953 char *name = g_strdup_printf("CPUSECCTRL%d", i); 954 MemoryRegion *mr; 955 956 qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); 957 g_free(name); 958 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); 959 object_property_set_bool(OBJECT(&s->cpusecctrl[i]), true, 960 "realized", &err); 961 if (err) { 962 error_propagate(errp, err); 963 return; 964 } 965 966 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); 967 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); 968 } 969 } 970 if (info->has_cpuid) { 971 for (i = 0; i < info->num_cpus; i++) { 972 MemoryRegion *mr; 973 974 qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); 975 object_property_set_bool(OBJECT(&s->cpuid[i]), true, 976 "realized", &err); 977 if (err) { 978 error_propagate(errp, err); 979 return; 980 } 981 982 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); 983 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); 984 } 985 } 986 987 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */ 988 /* Devices behind APB PPC1: 989 * 0x4002f000: S32K timer 990 */ 991 qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); 992 object_property_set_bool(OBJECT(&s->s32ktimer), true, "realized", &err); 993 if (err) { 994 error_propagate(errp, err); 995 return; 996 } 997 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, 998 armsse_get_common_irq_in(s, 2)); 999 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); 1000 object_property_set_link(OBJECT(&s->apb_ppc1), OBJECT(mr), "port[0]", &err); 1001 if (err) { 1002 error_propagate(errp, err); 1003 return; 1004 } 1005 1006 object_property_set_bool(OBJECT(&s->apb_ppc1), true, "realized", &err); 1007 if (err) { 1008 error_propagate(errp, err); 1009 return; 1010 } 1011 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); 1012 memory_region_add_subregion(&s->container, 0x4002f000, mr); 1013 1014 dev_apb_ppc1 = DEVICE(&s->apb_ppc1); 1015 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, 1016 qdev_get_gpio_in_named(dev_apb_ppc1, 1017 "cfg_nonsec", 0)); 1018 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, 1019 qdev_get_gpio_in_named(dev_apb_ppc1, 1020 "cfg_ap", 0)); 1021 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, 1022 qdev_get_gpio_in_named(dev_apb_ppc1, 1023 "irq_enable", 0)); 1024 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, 1025 qdev_get_gpio_in_named(dev_apb_ppc1, 1026 "irq_clear", 0)); 1027 qdev_connect_gpio_out(dev_splitter, 1, 1028 qdev_get_gpio_in_named(dev_apb_ppc1, 1029 "cfg_sec_resp", 0)); 1030 1031 object_property_set_int(OBJECT(&s->sysinfo), info->sys_version, 1032 "SYS_VERSION", &err); 1033 if (err) { 1034 error_propagate(errp, err); 1035 return; 1036 } 1037 object_property_set_int(OBJECT(&s->sysinfo), 1038 armsse_sys_config_value(s, info), 1039 "SYS_CONFIG", &err); 1040 if (err) { 1041 error_propagate(errp, err); 1042 return; 1043 } 1044 object_property_set_bool(OBJECT(&s->sysinfo), true, "realized", &err); 1045 if (err) { 1046 error_propagate(errp, err); 1047 return; 1048 } 1049 /* System information registers */ 1050 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); 1051 /* System control registers */ 1052 object_property_set_int(OBJECT(&s->sysctl), info->sys_version, 1053 "SYS_VERSION", &err); 1054 object_property_set_int(OBJECT(&s->sysctl), info->cpuwait_rst, 1055 "CPUWAIT_RST", &err); 1056 object_property_set_int(OBJECT(&s->sysctl), s->init_svtor, 1057 "INITSVTOR0_RST", &err); 1058 object_property_set_int(OBJECT(&s->sysctl), s->init_svtor, 1059 "INITSVTOR1_RST", &err); 1060 object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err); 1061 if (err) { 1062 error_propagate(errp, err); 1063 return; 1064 } 1065 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); 1066 1067 if (info->has_ppus) { 1068 /* CPUnCORE_PPU for each CPU */ 1069 for (i = 0; i < info->num_cpus; i++) { 1070 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 1071 1072 map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); 1073 /* 1074 * We don't support CPU debug so don't create the 1075 * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. 1076 */ 1077 g_free(name); 1078 } 1079 map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); 1080 1081 for (i = 0; i < info->sram_banks; i++) { 1082 char *name = g_strdup_printf("RAM%d_PPU", i); 1083 1084 map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); 1085 g_free(name); 1086 } 1087 } 1088 1089 /* This OR gate wires together outputs from the secure watchdogs to NMI */ 1090 object_property_set_int(OBJECT(&s->nmi_orgate), 2, "num-lines", &err); 1091 if (err) { 1092 error_propagate(errp, err); 1093 return; 1094 } 1095 object_property_set_bool(OBJECT(&s->nmi_orgate), true, "realized", &err); 1096 if (err) { 1097 error_propagate(errp, err); 1098 return; 1099 } 1100 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, 1101 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); 1102 1103 qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); 1104 object_property_set_bool(OBJECT(&s->s32kwatchdog), true, "realized", &err); 1105 if (err) { 1106 error_propagate(errp, err); 1107 return; 1108 } 1109 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 1110 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 0)); 1111 sysbus_mmio_map(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 0x5002e000); 1112 1113 /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ 1114 1115 qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); 1116 object_property_set_bool(OBJECT(&s->nswatchdog), true, "realized", &err); 1117 if (err) { 1118 error_propagate(errp, err); 1119 return; 1120 } 1121 sysbus_connect_irq(SYS_BUS_DEVICE(&s->nswatchdog), 0, 1122 armsse_get_common_irq_in(s, 1)); 1123 sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); 1124 1125 qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); 1126 object_property_set_bool(OBJECT(&s->swatchdog), true, "realized", &err); 1127 if (err) { 1128 error_propagate(errp, err); 1129 return; 1130 } 1131 sysbus_connect_irq(SYS_BUS_DEVICE(&s->swatchdog), 0, 1132 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 1)); 1133 sysbus_mmio_map(SYS_BUS_DEVICE(&s->swatchdog), 0, 0x50081000); 1134 1135 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 1136 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); 1137 1138 object_property_set_int(splitter, 2, "num-lines", &err); 1139 if (err) { 1140 error_propagate(errp, err); 1141 return; 1142 } 1143 object_property_set_bool(splitter, true, "realized", &err); 1144 if (err) { 1145 error_propagate(errp, err); 1146 return; 1147 } 1148 } 1149 1150 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { 1151 char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); 1152 1153 armsse_forward_ppc(s, ppcname, i); 1154 g_free(ppcname); 1155 } 1156 1157 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { 1158 char *ppcname = g_strdup_printf("apb_ppcexp%d", i); 1159 1160 armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); 1161 g_free(ppcname); 1162 } 1163 1164 for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { 1165 /* Wire up IRQ splitter for internal PPCs */ 1166 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); 1167 char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", 1168 i - NUM_EXTERNAL_PPCS); 1169 TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; 1170 1171 qdev_connect_gpio_out(devs, 0, 1172 qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); 1173 qdev_connect_gpio_out(devs, 1, 1174 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); 1175 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, 1176 qdev_get_gpio_in(devs, 0)); 1177 g_free(gpioname); 1178 } 1179 1180 /* Wire up the splitters for the MPC IRQs */ 1181 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 1182 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 1183 DeviceState *dev_splitter = DEVICE(splitter); 1184 1185 object_property_set_int(OBJECT(splitter), 2, "num-lines", &err); 1186 if (err) { 1187 error_propagate(errp, err); 1188 return; 1189 } 1190 object_property_set_bool(OBJECT(splitter), true, "realized", &err); 1191 if (err) { 1192 error_propagate(errp, err); 1193 return; 1194 } 1195 1196 if (i < IOTS_NUM_EXP_MPC) { 1197 /* Splitter input is from GPIO input line */ 1198 s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0); 1199 qdev_connect_gpio_out(dev_splitter, 0, 1200 qdev_get_gpio_in_named(dev_secctl, 1201 "mpcexp_status", i)); 1202 } else { 1203 /* Splitter input is from our own MPC */ 1204 qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]), 1205 "irq", 0, 1206 qdev_get_gpio_in(dev_splitter, 0)); 1207 qdev_connect_gpio_out(dev_splitter, 0, 1208 qdev_get_gpio_in_named(dev_secctl, 1209 "mpc_status", 0)); 1210 } 1211 1212 qdev_connect_gpio_out(dev_splitter, 1, 1213 qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i)); 1214 } 1215 /* Create GPIO inputs which will pass the line state for our 1216 * mpcexp_irq inputs to the correct splitter devices. 1217 */ 1218 qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status", 1219 IOTS_NUM_EXP_MPC); 1220 1221 armsse_forward_sec_resp_cfg(s); 1222 1223 /* Forward the MSC related signals */ 1224 qdev_pass_gpios(dev_secctl, dev, "mscexp_status"); 1225 qdev_pass_gpios(dev_secctl, dev, "mscexp_clear"); 1226 qdev_pass_gpios(dev_secctl, dev, "mscexp_ns"); 1227 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, 1228 armsse_get_common_irq_in(s, 11)); 1229 1230 /* 1231 * Expose our container region to the board model; this corresponds 1232 * to the AHB Slave Expansion ports which allow bus master devices 1233 * (eg DMA controllers) in the board model to make transactions into 1234 * devices in the ARMSSE. 1235 */ 1236 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); 1237 1238 system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; 1239 } 1240 1241 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, 1242 int *iregion, bool *exempt, bool *ns, bool *nsc) 1243 { 1244 /* 1245 * For ARMSSE systems the IDAU responses are simple logical functions 1246 * of the address bits. The NSC attribute is guest-adjustable via the 1247 * NSCCFG register in the security controller. 1248 */ 1249 ARMSSE *s = ARMSSE(ii); 1250 int region = extract32(address, 28, 4); 1251 1252 *ns = !(region & 1); 1253 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); 1254 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1255 *exempt = (address & 0xeff00000) == 0xe0000000; 1256 *iregion = region; 1257 } 1258 1259 static const VMStateDescription armsse_vmstate = { 1260 .name = "iotkit", 1261 .version_id = 1, 1262 .minimum_version_id = 1, 1263 .fields = (VMStateField[]) { 1264 VMSTATE_UINT32(nsccfg, ARMSSE), 1265 VMSTATE_END_OF_LIST() 1266 } 1267 }; 1268 1269 static void armsse_reset(DeviceState *dev) 1270 { 1271 ARMSSE *s = ARMSSE(dev); 1272 1273 s->nsccfg = 0; 1274 } 1275 1276 static void armsse_class_init(ObjectClass *klass, void *data) 1277 { 1278 DeviceClass *dc = DEVICE_CLASS(klass); 1279 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); 1280 ARMSSEClass *asc = ARMSSE_CLASS(klass); 1281 const ARMSSEInfo *info = data; 1282 1283 dc->realize = armsse_realize; 1284 dc->vmsd = &armsse_vmstate; 1285 dc->props = info->props; 1286 dc->reset = armsse_reset; 1287 iic->check = armsse_idau_check; 1288 asc->info = info; 1289 } 1290 1291 static const TypeInfo armsse_info = { 1292 .name = TYPE_ARMSSE, 1293 .parent = TYPE_SYS_BUS_DEVICE, 1294 .instance_size = sizeof(ARMSSE), 1295 .instance_init = armsse_init, 1296 .abstract = true, 1297 .interfaces = (InterfaceInfo[]) { 1298 { TYPE_IDAU_INTERFACE }, 1299 { } 1300 } 1301 }; 1302 1303 static void armsse_register_types(void) 1304 { 1305 int i; 1306 1307 type_register_static(&armsse_info); 1308 1309 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) { 1310 TypeInfo ti = { 1311 .name = armsse_variants[i].name, 1312 .parent = TYPE_ARMSSE, 1313 .class_init = armsse_class_init, 1314 .class_data = (void *)&armsse_variants[i], 1315 }; 1316 type_register(&ti); 1317 } 1318 } 1319 1320 type_init(armsse_register_types); 1321