1 /* 2 * Arm SSE (Subsystems for Embedded): IoTKit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qemu/bitops.h" 16 #include "qapi/error.h" 17 #include "trace.h" 18 #include "hw/sysbus.h" 19 #include "migration/vmstate.h" 20 #include "hw/registerfields.h" 21 #include "hw/arm/armsse.h" 22 #include "hw/arm/armsse-version.h" 23 #include "hw/arm/boot.h" 24 #include "hw/irq.h" 25 #include "hw/qdev-clock.h" 26 27 struct ARMSSEInfo { 28 const char *name; 29 uint32_t sse_version; 30 int sram_banks; 31 int num_cpus; 32 uint32_t sys_version; 33 uint32_t iidr; 34 uint32_t cpuwait_rst; 35 bool has_mhus; 36 bool has_ppus; 37 bool has_cachectrl; 38 bool has_cpusecctrl; 39 bool has_cpuid; 40 Property *props; 41 }; 42 43 static Property iotkit_properties[] = { 44 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 45 MemoryRegion *), 46 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 47 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 48 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 49 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), 50 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), 51 DEFINE_PROP_END_OF_LIST() 52 }; 53 54 static Property armsse_properties[] = { 55 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 56 MemoryRegion *), 57 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 58 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 59 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 60 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), 61 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), 62 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), 63 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), 64 DEFINE_PROP_END_OF_LIST() 65 }; 66 67 static const ARMSSEInfo armsse_variants[] = { 68 { 69 .name = TYPE_IOTKIT, 70 .sse_version = ARMSSE_IOTKIT, 71 .sram_banks = 1, 72 .num_cpus = 1, 73 .sys_version = 0x41743, 74 .iidr = 0, 75 .cpuwait_rst = 0, 76 .has_mhus = false, 77 .has_ppus = false, 78 .has_cachectrl = false, 79 .has_cpusecctrl = false, 80 .has_cpuid = false, 81 .props = iotkit_properties, 82 }, 83 { 84 .name = TYPE_SSE200, 85 .sse_version = ARMSSE_SSE200, 86 .sram_banks = 4, 87 .num_cpus = 2, 88 .sys_version = 0x22041743, 89 .iidr = 0, 90 .cpuwait_rst = 2, 91 .has_mhus = true, 92 .has_ppus = true, 93 .has_cachectrl = true, 94 .has_cpusecctrl = true, 95 .has_cpuid = true, 96 .props = armsse_properties, 97 }, 98 }; 99 100 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) 101 { 102 /* Return the SYS_CONFIG value for this SSE */ 103 uint32_t sys_config; 104 105 switch (info->sse_version) { 106 case ARMSSE_IOTKIT: 107 sys_config = 0; 108 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 109 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); 110 break; 111 case ARMSSE_SSE200: 112 sys_config = 0; 113 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 114 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 115 sys_config = deposit32(sys_config, 24, 4, 2); 116 if (info->num_cpus > 1) { 117 sys_config = deposit32(sys_config, 10, 1, 1); 118 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1); 119 sys_config = deposit32(sys_config, 28, 4, 2); 120 } 121 break; 122 case ARMSSE_SSE300: 123 sys_config = 0; 124 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 125 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 126 sys_config = deposit32(sys_config, 16, 3, 3); /* CPU0 = Cortex-M55 */ 127 break; 128 default: 129 g_assert_not_reached(); 130 } 131 return sys_config; 132 } 133 134 /* Clock frequency in HZ of the 32KHz "slow clock" */ 135 #define S32KCLK (32 * 1000) 136 137 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ 138 static bool irq_is_common[32] = { 139 [0 ... 5] = true, 140 /* 6, 7: per-CPU MHU interrupts */ 141 [8 ... 12] = true, 142 /* 13: per-CPU icache interrupt */ 143 /* 14: reserved */ 144 [15 ... 20] = true, 145 /* 21: reserved */ 146 [22 ... 26] = true, 147 /* 27: reserved */ 148 /* 28, 29: per-CPU CTI interrupts */ 149 /* 30, 31: reserved */ 150 }; 151 152 /* 153 * Create an alias region in @container of @size bytes starting at @base 154 * which mirrors the memory starting at @orig. 155 */ 156 static void make_alias(ARMSSE *s, MemoryRegion *mr, MemoryRegion *container, 157 const char *name, hwaddr base, hwaddr size, hwaddr orig) 158 { 159 memory_region_init_alias(mr, NULL, name, container, orig, size); 160 /* The alias is even lower priority than unimplemented_device regions */ 161 memory_region_add_subregion_overlap(container, base, mr, -1500); 162 } 163 164 static void irq_status_forwarder(void *opaque, int n, int level) 165 { 166 qemu_irq destirq = opaque; 167 168 qemu_set_irq(destirq, level); 169 } 170 171 static void nsccfg_handler(void *opaque, int n, int level) 172 { 173 ARMSSE *s = ARM_SSE(opaque); 174 175 s->nsccfg = level; 176 } 177 178 static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) 179 { 180 /* Each of the 4 AHB and 4 APB PPCs that might be present in a 181 * system using the ARMSSE has a collection of control lines which 182 * are provided by the security controller and which we want to 183 * expose as control lines on the ARMSSE device itself, so the 184 * code using the ARMSSE can wire them up to the PPCs. 185 */ 186 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; 187 DeviceState *armssedev = DEVICE(s); 188 DeviceState *dev_secctl = DEVICE(&s->secctl); 189 DeviceState *dev_splitter = DEVICE(splitter); 190 char *name; 191 192 name = g_strdup_printf("%s_nonsec", ppcname); 193 qdev_pass_gpios(dev_secctl, armssedev, name); 194 g_free(name); 195 name = g_strdup_printf("%s_ap", ppcname); 196 qdev_pass_gpios(dev_secctl, armssedev, name); 197 g_free(name); 198 name = g_strdup_printf("%s_irq_enable", ppcname); 199 qdev_pass_gpios(dev_secctl, armssedev, name); 200 g_free(name); 201 name = g_strdup_printf("%s_irq_clear", ppcname); 202 qdev_pass_gpios(dev_secctl, armssedev, name); 203 g_free(name); 204 205 /* irq_status is a little more tricky, because we need to 206 * split it so we can send it both to the security controller 207 * and to our OR gate for the NVIC interrupt line. 208 * Connect up the splitter's outputs, and create a GPIO input 209 * which will pass the line state to the input splitter. 210 */ 211 name = g_strdup_printf("%s_irq_status", ppcname); 212 qdev_connect_gpio_out(dev_splitter, 0, 213 qdev_get_gpio_in_named(dev_secctl, 214 name, 0)); 215 qdev_connect_gpio_out(dev_splitter, 1, 216 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); 217 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); 218 qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder, 219 s->irq_status_in[ppcnum], name, 1); 220 g_free(name); 221 } 222 223 static void armsse_forward_sec_resp_cfg(ARMSSE *s) 224 { 225 /* Forward the 3rd output from the splitter device as a 226 * named GPIO output of the armsse object. 227 */ 228 DeviceState *dev = DEVICE(s); 229 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); 230 231 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); 232 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, 233 s->sec_resp_cfg, 1); 234 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); 235 } 236 237 static void armsse_mainclk_update(void *opaque, ClockEvent event) 238 { 239 ARMSSE *s = ARM_SSE(opaque); 240 241 /* 242 * Set system_clock_scale from our Clock input; this is what 243 * controls the tick rate of the CPU SysTick timer. 244 */ 245 system_clock_scale = clock_ticks_to_ns(s->mainclk, 1); 246 } 247 248 static void armsse_init(Object *obj) 249 { 250 ARMSSE *s = ARM_SSE(obj); 251 ARMSSEClass *asc = ARM_SSE_GET_CLASS(obj); 252 const ARMSSEInfo *info = asc->info; 253 int i; 254 255 assert(info->sram_banks <= MAX_SRAM_BANKS); 256 assert(info->num_cpus <= SSE_MAX_CPUS); 257 258 s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", 259 armsse_mainclk_update, s, ClockUpdate); 260 s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0); 261 262 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); 263 264 for (i = 0; i < info->num_cpus; i++) { 265 /* 266 * We put each CPU in its own cluster as they are logically 267 * distinct and may be configured differently. 268 */ 269 char *name; 270 271 name = g_strdup_printf("cluster%d", i); 272 object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER); 273 qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); 274 g_free(name); 275 276 name = g_strdup_printf("armv7m%d", i); 277 object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i], 278 TYPE_ARMV7M); 279 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", 280 ARM_CPU_TYPE_NAME("cortex-m33")); 281 g_free(name); 282 name = g_strdup_printf("arm-sse-cpu-container%d", i); 283 memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); 284 g_free(name); 285 if (i > 0) { 286 name = g_strdup_printf("arm-sse-container-alias%d", i); 287 memory_region_init_alias(&s->container_alias[i - 1], obj, 288 name, &s->container, 0, UINT64_MAX); 289 g_free(name); 290 } 291 } 292 293 object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL); 294 object_initialize_child(obj, "apb-ppc0", &s->apb_ppc0, TYPE_TZ_PPC); 295 object_initialize_child(obj, "apb-ppc1", &s->apb_ppc1, TYPE_TZ_PPC); 296 for (i = 0; i < info->sram_banks; i++) { 297 char *name = g_strdup_printf("mpc%d", i); 298 object_initialize_child(obj, name, &s->mpc[i], TYPE_TZ_MPC); 299 g_free(name); 300 } 301 object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate, 302 TYPE_OR_IRQ); 303 304 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 305 char *name = g_strdup_printf("mpc-irq-splitter-%d", i); 306 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 307 308 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 309 g_free(name); 310 } 311 object_initialize_child(obj, "timer0", &s->timer0, TYPE_CMSDK_APB_TIMER); 312 object_initialize_child(obj, "timer1", &s->timer1, TYPE_CMSDK_APB_TIMER); 313 object_initialize_child(obj, "s32ktimer", &s->s32ktimer, 314 TYPE_CMSDK_APB_TIMER); 315 object_initialize_child(obj, "dualtimer", &s->dualtimer, 316 TYPE_CMSDK_APB_DUALTIMER); 317 object_initialize_child(obj, "s32kwatchdog", &s->s32kwatchdog, 318 TYPE_CMSDK_APB_WATCHDOG); 319 object_initialize_child(obj, "nswatchdog", &s->nswatchdog, 320 TYPE_CMSDK_APB_WATCHDOG); 321 object_initialize_child(obj, "swatchdog", &s->swatchdog, 322 TYPE_CMSDK_APB_WATCHDOG); 323 object_initialize_child(obj, "armsse-sysctl", &s->sysctl, 324 TYPE_IOTKIT_SYSCTL); 325 object_initialize_child(obj, "armsse-sysinfo", &s->sysinfo, 326 TYPE_IOTKIT_SYSINFO); 327 if (info->has_mhus) { 328 object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); 329 object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); 330 } 331 if (info->has_ppus) { 332 for (i = 0; i < info->num_cpus; i++) { 333 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 334 int ppuidx = CPU0CORE_PPU + i; 335 336 object_initialize_child(obj, name, &s->ppu[ppuidx], 337 TYPE_UNIMPLEMENTED_DEVICE); 338 g_free(name); 339 } 340 object_initialize_child(obj, "DBG_PPU", &s->ppu[DBG_PPU], 341 TYPE_UNIMPLEMENTED_DEVICE); 342 for (i = 0; i < info->sram_banks; i++) { 343 char *name = g_strdup_printf("RAM%d_PPU", i); 344 int ppuidx = RAM0_PPU + i; 345 346 object_initialize_child(obj, name, &s->ppu[ppuidx], 347 TYPE_UNIMPLEMENTED_DEVICE); 348 g_free(name); 349 } 350 } 351 if (info->has_cachectrl) { 352 for (i = 0; i < info->num_cpus; i++) { 353 char *name = g_strdup_printf("cachectrl%d", i); 354 355 object_initialize_child(obj, name, &s->cachectrl[i], 356 TYPE_UNIMPLEMENTED_DEVICE); 357 g_free(name); 358 } 359 } 360 if (info->has_cpusecctrl) { 361 for (i = 0; i < info->num_cpus; i++) { 362 char *name = g_strdup_printf("cpusecctrl%d", i); 363 364 object_initialize_child(obj, name, &s->cpusecctrl[i], 365 TYPE_UNIMPLEMENTED_DEVICE); 366 g_free(name); 367 } 368 } 369 if (info->has_cpuid) { 370 for (i = 0; i < info->num_cpus; i++) { 371 char *name = g_strdup_printf("cpuid%d", i); 372 373 object_initialize_child(obj, name, &s->cpuid[i], 374 TYPE_ARMSSE_CPUID); 375 g_free(name); 376 } 377 } 378 object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ); 379 object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, 380 TYPE_OR_IRQ); 381 object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter, 382 TYPE_SPLIT_IRQ); 383 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 384 char *name = g_strdup_printf("ppc-irq-splitter-%d", i); 385 SplitIRQ *splitter = &s->ppc_irq_splitter[i]; 386 387 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 388 g_free(name); 389 } 390 if (info->num_cpus > 1) { 391 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 392 if (irq_is_common[i]) { 393 char *name = g_strdup_printf("cpu-irq-splitter%d", i); 394 SplitIRQ *splitter = &s->cpu_irq_splitter[i]; 395 396 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 397 g_free(name); 398 } 399 } 400 } 401 } 402 403 static void armsse_exp_irq(void *opaque, int n, int level) 404 { 405 qemu_irq *irqarray = opaque; 406 407 qemu_set_irq(irqarray[n], level); 408 } 409 410 static void armsse_mpcexp_status(void *opaque, int n, int level) 411 { 412 ARMSSE *s = ARM_SSE(opaque); 413 qemu_set_irq(s->mpcexp_status_in[n], level); 414 } 415 416 static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno) 417 { 418 /* 419 * Return a qemu_irq which can be used to signal IRQ n to 420 * all CPUs in the SSE. 421 */ 422 ARMSSEClass *asc = ARM_SSE_GET_CLASS(s); 423 const ARMSSEInfo *info = asc->info; 424 425 assert(irq_is_common[irqno]); 426 427 if (info->num_cpus == 1) { 428 /* Only one CPU -- just connect directly to it */ 429 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); 430 } else { 431 /* Connect to the splitter which feeds all CPUs */ 432 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); 433 } 434 } 435 436 static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) 437 { 438 /* Map a PPU unimplemented device stub */ 439 DeviceState *dev = DEVICE(&s->ppu[ppuidx]); 440 441 qdev_prop_set_string(dev, "name", name); 442 qdev_prop_set_uint64(dev, "size", 0x1000); 443 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 444 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); 445 } 446 447 static void armsse_realize(DeviceState *dev, Error **errp) 448 { 449 ARMSSE *s = ARM_SSE(dev); 450 ARMSSEClass *asc = ARM_SSE_GET_CLASS(dev); 451 const ARMSSEInfo *info = asc->info; 452 int i; 453 MemoryRegion *mr; 454 Error *err = NULL; 455 SysBusDevice *sbd_apb_ppc0; 456 SysBusDevice *sbd_secctl; 457 DeviceState *dev_apb_ppc0; 458 DeviceState *dev_apb_ppc1; 459 DeviceState *dev_secctl; 460 DeviceState *dev_splitter; 461 uint32_t addr_width_max; 462 463 if (!s->board_memory) { 464 error_setg(errp, "memory property was not set"); 465 return; 466 } 467 468 if (!clock_has_source(s->mainclk)) { 469 error_setg(errp, "MAINCLK clock was not connected"); 470 } 471 if (!clock_has_source(s->s32kclk)) { 472 error_setg(errp, "S32KCLK clock was not connected"); 473 } 474 475 assert(info->num_cpus <= SSE_MAX_CPUS); 476 477 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ 478 assert(is_power_of_2(info->sram_banks)); 479 addr_width_max = 24 - ctz32(info->sram_banks); 480 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { 481 error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d", 482 addr_width_max); 483 return; 484 } 485 486 /* Handling of which devices should be available only to secure 487 * code is usually done differently for M profile than for A profile. 488 * Instead of putting some devices only into the secure address space, 489 * devices exist in both address spaces but with hard-wired security 490 * permissions that will cause the CPU to fault for non-secure accesses. 491 * 492 * The ARMSSE has an IDAU (Implementation Defined Access Unit), 493 * which specifies hard-wired security permissions for different 494 * areas of the physical address space. For the ARMSSE IDAU, the 495 * top 4 bits of the physical address are the IDAU region ID, and 496 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS 497 * region, otherwise it is an S region. 498 * 499 * The various devices and RAMs are generally all mapped twice, 500 * once into a region that the IDAU defines as secure and once 501 * into a non-secure region. They sit behind either a Memory 502 * Protection Controller (for RAM) or a Peripheral Protection 503 * Controller (for devices), which allow a more fine grained 504 * configuration of whether non-secure accesses are permitted. 505 * 506 * (The other place that guest software can configure security 507 * permissions is in the architected SAU (Security Attribution 508 * Unit), which is entirely inside the CPU. The IDAU can upgrade 509 * the security attributes for a region to more restrictive than 510 * the SAU specifies, but cannot downgrade them.) 511 * 512 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff 513 * 0x20000000..0x2007ffff 32KB FPGA block RAM 514 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff 515 * 0x40000000..0x4000ffff base peripheral region 1 516 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) 517 * 0x40020000..0x4002ffff system control element peripherals 518 * 0x40080000..0x400fffff base peripheral region 2 519 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff 520 */ 521 522 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); 523 524 for (i = 0; i < info->num_cpus; i++) { 525 DeviceState *cpudev = DEVICE(&s->armv7m[i]); 526 Object *cpuobj = OBJECT(&s->armv7m[i]); 527 int j; 528 char *gpioname; 529 530 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32); 531 /* 532 * In real hardware the initial Secure VTOR is set from the INITSVTOR* 533 * registers in the IoT Kit System Control Register block. In QEMU 534 * we set the initial value here, and also the reset value of the 535 * sysctl register, from this object's QOM init-svtor property. 536 * If the guest changes the INITSVTOR* registers at runtime then the 537 * code in iotkit-sysctl.c will update the CPU init-svtor property 538 * (which will then take effect on the next CPU warm-reset). 539 * 540 * Note that typically a board using the SSE-200 will have a system 541 * control processor whose boot firmware initializes the INITSVTOR* 542 * registers before powering up the CPUs. QEMU doesn't emulate 543 * the control processor, so instead we behave in the way that the 544 * firmware does: the initial value should be set by the board code 545 * (using the init-svtor property on the ARMSSE object) to match 546 * whatever its firmware does. 547 */ 548 qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); 549 /* 550 * CPUs start powered down if the corresponding bit in the CPUWAIT 551 * register is 1. In real hardware the CPUWAIT register reset value is 552 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and 553 * CPUWAIT1_RST parameters), but since all the boards we care about 554 * start CPU0 and leave CPU1 powered off, we hard-code that in 555 * info->cpuwait_rst for now. We can add QOM properties for this 556 * later if necessary. 557 */ 558 if (extract32(info->cpuwait_rst, i, 1)) { 559 if (!object_property_set_bool(cpuobj, "start-powered-off", true, 560 errp)) { 561 return; 562 } 563 } 564 if (!s->cpu_fpu[i]) { 565 if (!object_property_set_bool(cpuobj, "vfp", false, errp)) { 566 return; 567 } 568 } 569 if (!s->cpu_dsp[i]) { 570 if (!object_property_set_bool(cpuobj, "dsp", false, errp)) { 571 return; 572 } 573 } 574 575 if (i > 0) { 576 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 577 &s->container_alias[i - 1], -1); 578 } else { 579 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 580 &s->container, -1); 581 } 582 object_property_set_link(cpuobj, "memory", 583 OBJECT(&s->cpu_container[i]), &error_abort); 584 object_property_set_link(cpuobj, "idau", OBJECT(s), &error_abort); 585 if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj), errp)) { 586 return; 587 } 588 /* 589 * The cluster must be realized after the armv7m container, as 590 * the container's CPU object is only created on realize, and the 591 * CPU must exist and have been parented into the cluster before 592 * the cluster is realized. 593 */ 594 if (!qdev_realize(DEVICE(&s->cluster[i]), NULL, errp)) { 595 return; 596 } 597 598 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ 599 s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); 600 for (j = 0; j < s->exp_numirq; j++) { 601 s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32); 602 } 603 if (i == 0) { 604 gpioname = g_strdup("EXP_IRQ"); 605 } else { 606 gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i); 607 } 608 qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq, 609 s->exp_irqs[i], 610 gpioname, s->exp_numirq); 611 g_free(gpioname); 612 } 613 614 /* Wire up the splitters that connect common IRQs to all CPUs */ 615 if (info->num_cpus > 1) { 616 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 617 if (irq_is_common[i]) { 618 Object *splitter = OBJECT(&s->cpu_irq_splitter[i]); 619 DeviceState *devs = DEVICE(splitter); 620 int cpunum; 621 622 if (!object_property_set_int(splitter, "num-lines", 623 info->num_cpus, errp)) { 624 return; 625 } 626 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 627 return; 628 } 629 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 630 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 631 632 qdev_connect_gpio_out(devs, cpunum, 633 qdev_get_gpio_in(cpudev, i)); 634 } 635 } 636 } 637 } 638 639 /* Set up the big aliases first */ 640 make_alias(s, &s->alias1, &s->container, "alias 1", 641 0x10000000, 0x10000000, 0x00000000); 642 make_alias(s, &s->alias2, &s->container, 643 "alias 2", 0x30000000, 0x10000000, 0x20000000); 644 /* The 0x50000000..0x5fffffff region is not a pure alias: it has 645 * a few extra devices that only appear there (generally the 646 * control interfaces for the protection controllers). 647 * We implement this by mapping those devices over the top of this 648 * alias MR at a higher priority. Some of the devices in this range 649 * are per-CPU, so we must put this alias in the per-cpu containers. 650 */ 651 for (i = 0; i < info->num_cpus; i++) { 652 make_alias(s, &s->alias3[i], &s->cpu_container[i], 653 "alias 3", 0x50000000, 0x10000000, 0x40000000); 654 } 655 656 /* Security controller */ 657 object_property_set_int(OBJECT(&s->secctl), "sse-version", 658 info->sse_version, &error_abort); 659 if (!sysbus_realize(SYS_BUS_DEVICE(&s->secctl), errp)) { 660 return; 661 } 662 sbd_secctl = SYS_BUS_DEVICE(&s->secctl); 663 dev_secctl = DEVICE(&s->secctl); 664 sysbus_mmio_map(sbd_secctl, 0, 0x50080000); 665 sysbus_mmio_map(sbd_secctl, 1, 0x40080000); 666 667 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); 668 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); 669 670 /* The sec_resp_cfg output from the security controller must be split into 671 * multiple lines, one for each of the PPCs within the ARMSSE and one 672 * that will be an output from the ARMSSE to the system. 673 */ 674 if (!object_property_set_int(OBJECT(&s->sec_resp_splitter), 675 "num-lines", 3, errp)) { 676 return; 677 } 678 if (!qdev_realize(DEVICE(&s->sec_resp_splitter), NULL, errp)) { 679 return; 680 } 681 dev_splitter = DEVICE(&s->sec_resp_splitter); 682 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, 683 qdev_get_gpio_in(dev_splitter, 0)); 684 685 /* Each SRAM bank lives behind its own Memory Protection Controller */ 686 for (i = 0; i < info->sram_banks; i++) { 687 char *ramname = g_strdup_printf("armsse.sram%d", i); 688 SysBusDevice *sbd_mpc; 689 uint32_t sram_bank_size = 1 << s->sram_addr_width; 690 691 memory_region_init_ram(&s->sram[i], NULL, ramname, 692 sram_bank_size, &err); 693 g_free(ramname); 694 if (err) { 695 error_propagate(errp, err); 696 return; 697 } 698 object_property_set_link(OBJECT(&s->mpc[i]), "downstream", 699 OBJECT(&s->sram[i]), &error_abort); 700 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mpc[i]), errp)) { 701 return; 702 } 703 /* Map the upstream end of the MPC into the right place... */ 704 sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); 705 memory_region_add_subregion(&s->container, 706 0x20000000 + i * sram_bank_size, 707 sysbus_mmio_get_region(sbd_mpc, 1)); 708 /* ...and its register interface */ 709 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, 710 sysbus_mmio_get_region(sbd_mpc, 0)); 711 } 712 713 /* We must OR together lines from the MPC splitters to go to the NVIC */ 714 if (!object_property_set_int(OBJECT(&s->mpc_irq_orgate), "num-lines", 715 IOTS_NUM_EXP_MPC + info->sram_banks, 716 errp)) { 717 return; 718 } 719 if (!qdev_realize(DEVICE(&s->mpc_irq_orgate), NULL, errp)) { 720 return; 721 } 722 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, 723 armsse_get_common_irq_in(s, 9)); 724 725 /* Devices behind APB PPC0: 726 * 0x40000000: timer0 727 * 0x40001000: timer1 728 * 0x40002000: dual timer 729 * 0x40003000: MHU0 (SSE-200 only) 730 * 0x40004000: MHU1 (SSE-200 only) 731 * We must configure and realize each downstream device and connect 732 * it to the appropriate PPC port; then we can realize the PPC and 733 * map its upstream ends to the right place in the container. 734 */ 735 qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); 736 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { 737 return; 738 } 739 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, 740 armsse_get_common_irq_in(s, 3)); 741 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); 742 object_property_set_link(OBJECT(&s->apb_ppc0), "port[0]", OBJECT(mr), 743 &error_abort); 744 745 qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); 746 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { 747 return; 748 } 749 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, 750 armsse_get_common_irq_in(s, 4)); 751 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); 752 object_property_set_link(OBJECT(&s->apb_ppc0), "port[1]", OBJECT(mr), 753 &error_abort); 754 755 qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); 756 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { 757 return; 758 } 759 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dualtimer), 0, 760 armsse_get_common_irq_in(s, 5)); 761 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); 762 object_property_set_link(OBJECT(&s->apb_ppc0), "port[2]", OBJECT(mr), 763 &error_abort); 764 765 if (info->has_mhus) { 766 /* 767 * An SSE-200 with only one CPU should have only one MHU created, 768 * with the region where the second MHU usually is being RAZ/WI. 769 * We don't implement that SSE-200 config; if we want to support 770 * it then this code needs to be enhanced to handle creating the 771 * RAZ/WI region instead of the second MHU. 772 */ 773 assert(info->num_cpus == ARRAY_SIZE(s->mhu)); 774 775 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { 776 char *port; 777 int cpunum; 778 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]); 779 780 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mhu[i]), errp)) { 781 return; 782 } 783 port = g_strdup_printf("port[%d]", i + 3); 784 mr = sysbus_mmio_get_region(mhu_sbd, 0); 785 object_property_set_link(OBJECT(&s->apb_ppc0), port, OBJECT(mr), 786 &error_abort); 787 g_free(port); 788 789 /* 790 * Each MHU has an irq line for each CPU: 791 * MHU 0 irq line 0 -> CPU 0 IRQ 6 792 * MHU 0 irq line 1 -> CPU 1 IRQ 6 793 * MHU 1 irq line 0 -> CPU 0 IRQ 7 794 * MHU 1 irq line 1 -> CPU 1 IRQ 7 795 */ 796 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 797 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 798 799 sysbus_connect_irq(mhu_sbd, cpunum, 800 qdev_get_gpio_in(cpudev, 6 + i)); 801 } 802 } 803 } 804 805 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc0), errp)) { 806 return; 807 } 808 809 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); 810 dev_apb_ppc0 = DEVICE(&s->apb_ppc0); 811 812 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); 813 memory_region_add_subregion(&s->container, 0x40000000, mr); 814 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); 815 memory_region_add_subregion(&s->container, 0x40001000, mr); 816 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); 817 memory_region_add_subregion(&s->container, 0x40002000, mr); 818 if (info->has_mhus) { 819 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3); 820 memory_region_add_subregion(&s->container, 0x40003000, mr); 821 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4); 822 memory_region_add_subregion(&s->container, 0x40004000, mr); 823 } 824 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { 825 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, 826 qdev_get_gpio_in_named(dev_apb_ppc0, 827 "cfg_nonsec", i)); 828 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, 829 qdev_get_gpio_in_named(dev_apb_ppc0, 830 "cfg_ap", i)); 831 } 832 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, 833 qdev_get_gpio_in_named(dev_apb_ppc0, 834 "irq_enable", 0)); 835 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, 836 qdev_get_gpio_in_named(dev_apb_ppc0, 837 "irq_clear", 0)); 838 qdev_connect_gpio_out(dev_splitter, 0, 839 qdev_get_gpio_in_named(dev_apb_ppc0, 840 "cfg_sec_resp", 0)); 841 842 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external 843 * ones) are sent individually to the security controller, and also 844 * ORed together to give a single combined PPC interrupt to the NVIC. 845 */ 846 if (!object_property_set_int(OBJECT(&s->ppc_irq_orgate), 847 "num-lines", NUM_PPCS, errp)) { 848 return; 849 } 850 if (!qdev_realize(DEVICE(&s->ppc_irq_orgate), NULL, errp)) { 851 return; 852 } 853 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, 854 armsse_get_common_irq_in(s, 10)); 855 856 /* 857 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): 858 * private per-CPU region (all these devices are SSE-200 only): 859 * 0x50010000: L1 icache control registers 860 * 0x50011000: CPUSECCTRL (CPU local security control registers) 861 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block 862 */ 863 if (info->has_cachectrl) { 864 for (i = 0; i < info->num_cpus; i++) { 865 char *name = g_strdup_printf("cachectrl%d", i); 866 MemoryRegion *mr; 867 868 qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); 869 g_free(name); 870 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); 871 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cachectrl[i]), errp)) { 872 return; 873 } 874 875 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); 876 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); 877 } 878 } 879 if (info->has_cpusecctrl) { 880 for (i = 0; i < info->num_cpus; i++) { 881 char *name = g_strdup_printf("CPUSECCTRL%d", i); 882 MemoryRegion *mr; 883 884 qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); 885 g_free(name); 886 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); 887 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpusecctrl[i]), errp)) { 888 return; 889 } 890 891 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); 892 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); 893 } 894 } 895 if (info->has_cpuid) { 896 for (i = 0; i < info->num_cpus; i++) { 897 MemoryRegion *mr; 898 899 qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); 900 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpuid[i]), errp)) { 901 return; 902 } 903 904 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); 905 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); 906 } 907 } 908 909 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */ 910 /* Devices behind APB PPC1: 911 * 0x4002f000: S32K timer 912 */ 913 qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); 914 if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { 915 return; 916 } 917 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, 918 armsse_get_common_irq_in(s, 2)); 919 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); 920 object_property_set_link(OBJECT(&s->apb_ppc1), "port[0]", OBJECT(mr), 921 &error_abort); 922 923 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc1), errp)) { 924 return; 925 } 926 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); 927 memory_region_add_subregion(&s->container, 0x4002f000, mr); 928 929 dev_apb_ppc1 = DEVICE(&s->apb_ppc1); 930 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, 931 qdev_get_gpio_in_named(dev_apb_ppc1, 932 "cfg_nonsec", 0)); 933 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, 934 qdev_get_gpio_in_named(dev_apb_ppc1, 935 "cfg_ap", 0)); 936 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, 937 qdev_get_gpio_in_named(dev_apb_ppc1, 938 "irq_enable", 0)); 939 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, 940 qdev_get_gpio_in_named(dev_apb_ppc1, 941 "irq_clear", 0)); 942 qdev_connect_gpio_out(dev_splitter, 1, 943 qdev_get_gpio_in_named(dev_apb_ppc1, 944 "cfg_sec_resp", 0)); 945 946 if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION", 947 info->sys_version, errp)) { 948 return; 949 } 950 if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG", 951 armsse_sys_config_value(s, info), errp)) { 952 return; 953 } 954 object_property_set_int(OBJECT(&s->sysinfo), "sse-version", 955 info->sse_version, &error_abort); 956 object_property_set_int(OBJECT(&s->sysinfo), "IIDR", 957 info->iidr, &error_abort); 958 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), errp)) { 959 return; 960 } 961 /* System information registers */ 962 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); 963 /* System control registers */ 964 object_property_set_int(OBJECT(&s->sysctl), "sse-version", 965 info->sse_version, &error_abort); 966 object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST", 967 info->cpuwait_rst, &error_abort); 968 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST", 969 s->init_svtor, &error_abort); 970 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST", 971 s->init_svtor, &error_abort); 972 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysctl), errp)) { 973 return; 974 } 975 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); 976 977 if (info->has_ppus) { 978 /* CPUnCORE_PPU for each CPU */ 979 for (i = 0; i < info->num_cpus; i++) { 980 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 981 982 map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); 983 /* 984 * We don't support CPU debug so don't create the 985 * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. 986 */ 987 g_free(name); 988 } 989 map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); 990 991 for (i = 0; i < info->sram_banks; i++) { 992 char *name = g_strdup_printf("RAM%d_PPU", i); 993 994 map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); 995 g_free(name); 996 } 997 } 998 999 /* This OR gate wires together outputs from the secure watchdogs to NMI */ 1000 if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2, 1001 errp)) { 1002 return; 1003 } 1004 if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) { 1005 return; 1006 } 1007 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, 1008 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); 1009 1010 qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); 1011 if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { 1012 return; 1013 } 1014 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 1015 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 0)); 1016 sysbus_mmio_map(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 0x5002e000); 1017 1018 /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ 1019 1020 qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); 1021 if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { 1022 return; 1023 } 1024 sysbus_connect_irq(SYS_BUS_DEVICE(&s->nswatchdog), 0, 1025 armsse_get_common_irq_in(s, 1)); 1026 sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); 1027 1028 qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); 1029 if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { 1030 return; 1031 } 1032 sysbus_connect_irq(SYS_BUS_DEVICE(&s->swatchdog), 0, 1033 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 1)); 1034 sysbus_mmio_map(SYS_BUS_DEVICE(&s->swatchdog), 0, 0x50081000); 1035 1036 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 1037 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); 1038 1039 if (!object_property_set_int(splitter, "num-lines", 2, errp)) { 1040 return; 1041 } 1042 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1043 return; 1044 } 1045 } 1046 1047 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { 1048 char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); 1049 1050 armsse_forward_ppc(s, ppcname, i); 1051 g_free(ppcname); 1052 } 1053 1054 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { 1055 char *ppcname = g_strdup_printf("apb_ppcexp%d", i); 1056 1057 armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); 1058 g_free(ppcname); 1059 } 1060 1061 for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { 1062 /* Wire up IRQ splitter for internal PPCs */ 1063 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); 1064 char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", 1065 i - NUM_EXTERNAL_PPCS); 1066 TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; 1067 1068 qdev_connect_gpio_out(devs, 0, 1069 qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); 1070 qdev_connect_gpio_out(devs, 1, 1071 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); 1072 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, 1073 qdev_get_gpio_in(devs, 0)); 1074 g_free(gpioname); 1075 } 1076 1077 /* Wire up the splitters for the MPC IRQs */ 1078 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 1079 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 1080 DeviceState *dev_splitter = DEVICE(splitter); 1081 1082 if (!object_property_set_int(OBJECT(splitter), "num-lines", 2, 1083 errp)) { 1084 return; 1085 } 1086 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1087 return; 1088 } 1089 1090 if (i < IOTS_NUM_EXP_MPC) { 1091 /* Splitter input is from GPIO input line */ 1092 s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0); 1093 qdev_connect_gpio_out(dev_splitter, 0, 1094 qdev_get_gpio_in_named(dev_secctl, 1095 "mpcexp_status", i)); 1096 } else { 1097 /* Splitter input is from our own MPC */ 1098 qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]), 1099 "irq", 0, 1100 qdev_get_gpio_in(dev_splitter, 0)); 1101 qdev_connect_gpio_out(dev_splitter, 0, 1102 qdev_get_gpio_in_named(dev_secctl, 1103 "mpc_status", 1104 i - IOTS_NUM_EXP_MPC)); 1105 } 1106 1107 qdev_connect_gpio_out(dev_splitter, 1, 1108 qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i)); 1109 } 1110 /* Create GPIO inputs which will pass the line state for our 1111 * mpcexp_irq inputs to the correct splitter devices. 1112 */ 1113 qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status", 1114 IOTS_NUM_EXP_MPC); 1115 1116 armsse_forward_sec_resp_cfg(s); 1117 1118 /* Forward the MSC related signals */ 1119 qdev_pass_gpios(dev_secctl, dev, "mscexp_status"); 1120 qdev_pass_gpios(dev_secctl, dev, "mscexp_clear"); 1121 qdev_pass_gpios(dev_secctl, dev, "mscexp_ns"); 1122 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, 1123 armsse_get_common_irq_in(s, 11)); 1124 1125 /* 1126 * Expose our container region to the board model; this corresponds 1127 * to the AHB Slave Expansion ports which allow bus master devices 1128 * (eg DMA controllers) in the board model to make transactions into 1129 * devices in the ARMSSE. 1130 */ 1131 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); 1132 1133 /* Set initial system_clock_scale from MAINCLK */ 1134 armsse_mainclk_update(s, ClockUpdate); 1135 } 1136 1137 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, 1138 int *iregion, bool *exempt, bool *ns, bool *nsc) 1139 { 1140 /* 1141 * For ARMSSE systems the IDAU responses are simple logical functions 1142 * of the address bits. The NSC attribute is guest-adjustable via the 1143 * NSCCFG register in the security controller. 1144 */ 1145 ARMSSE *s = ARM_SSE(ii); 1146 int region = extract32(address, 28, 4); 1147 1148 *ns = !(region & 1); 1149 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); 1150 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1151 *exempt = (address & 0xeff00000) == 0xe0000000; 1152 *iregion = region; 1153 } 1154 1155 static const VMStateDescription armsse_vmstate = { 1156 .name = "iotkit", 1157 .version_id = 2, 1158 .minimum_version_id = 2, 1159 .fields = (VMStateField[]) { 1160 VMSTATE_CLOCK(mainclk, ARMSSE), 1161 VMSTATE_CLOCK(s32kclk, ARMSSE), 1162 VMSTATE_UINT32(nsccfg, ARMSSE), 1163 VMSTATE_END_OF_LIST() 1164 } 1165 }; 1166 1167 static void armsse_reset(DeviceState *dev) 1168 { 1169 ARMSSE *s = ARM_SSE(dev); 1170 1171 s->nsccfg = 0; 1172 } 1173 1174 static void armsse_class_init(ObjectClass *klass, void *data) 1175 { 1176 DeviceClass *dc = DEVICE_CLASS(klass); 1177 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); 1178 ARMSSEClass *asc = ARM_SSE_CLASS(klass); 1179 const ARMSSEInfo *info = data; 1180 1181 dc->realize = armsse_realize; 1182 dc->vmsd = &armsse_vmstate; 1183 device_class_set_props(dc, info->props); 1184 dc->reset = armsse_reset; 1185 iic->check = armsse_idau_check; 1186 asc->info = info; 1187 } 1188 1189 static const TypeInfo armsse_info = { 1190 .name = TYPE_ARM_SSE, 1191 .parent = TYPE_SYS_BUS_DEVICE, 1192 .instance_size = sizeof(ARMSSE), 1193 .class_size = sizeof(ARMSSEClass), 1194 .instance_init = armsse_init, 1195 .abstract = true, 1196 .interfaces = (InterfaceInfo[]) { 1197 { TYPE_IDAU_INTERFACE }, 1198 { } 1199 } 1200 }; 1201 1202 static void armsse_register_types(void) 1203 { 1204 int i; 1205 1206 type_register_static(&armsse_info); 1207 1208 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) { 1209 TypeInfo ti = { 1210 .name = armsse_variants[i].name, 1211 .parent = TYPE_ARM_SSE, 1212 .class_init = armsse_class_init, 1213 .class_data = (void *)&armsse_variants[i], 1214 }; 1215 type_register(&ti); 1216 } 1217 } 1218 1219 type_init(armsse_register_types); 1220