xref: /openbmc/qemu/hw/arm/allwinner-a10.c (revision fc8c745d)
1 /*
2  * Allwinner A10 SoC emulation
3  *
4  * Copyright (C) 2013 Li Guang
5  * Written by Li Guang <lig.fnst@cn.fujitsu.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15  * for more details.
16  */
17 
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "qemu/module.h"
21 #include "hw/sysbus.h"
22 #include "hw/arm/allwinner-a10.h"
23 #include "hw/misc/unimp.h"
24 #include "sysemu/sysemu.h"
25 #include "hw/boards.h"
26 #include "hw/usb/hcd-ohci.h"
27 
28 #define AW_A10_MMC0_BASE        0x01c0f000
29 #define AW_A10_PIC_REG_BASE     0x01c20400
30 #define AW_A10_PIT_REG_BASE     0x01c20c00
31 #define AW_A10_UART0_REG_BASE   0x01c28000
32 #define AW_A10_EMAC_BASE        0x01c0b000
33 #define AW_A10_EHCI_BASE        0x01c14000
34 #define AW_A10_OHCI_BASE        0x01c14400
35 #define AW_A10_SATA_BASE        0x01c18000
36 #define AW_A10_RTC_BASE         0x01c20d00
37 
38 static void aw_a10_init(Object *obj)
39 {
40     AwA10State *s = AW_A10(obj);
41 
42     object_initialize_child(obj, "cpu", &s->cpu,
43                             ARM_CPU_TYPE_NAME("cortex-a8"));
44 
45     object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC);
46 
47     object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
48 
49     object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
50 
51     object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
52 
53     if (machine_usb(current_machine)) {
54         int i;
55 
56         for (i = 0; i < AW_A10_NUM_USB; i++) {
57             object_initialize_child(obj, "ehci[*]", &s->ehci[i],
58                                     TYPE_PLATFORM_EHCI);
59             object_initialize_child(obj, "ohci[*]", &s->ohci[i],
60                                     TYPE_SYSBUS_OHCI);
61         }
62     }
63 
64     object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);
65 
66     object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I);
67 }
68 
69 static void aw_a10_realize(DeviceState *dev, Error **errp)
70 {
71     AwA10State *s = AW_A10(dev);
72     SysBusDevice *sysbusdev;
73 
74     if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
75         return;
76     }
77 
78     if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) {
79         return;
80     }
81     sysbusdev = SYS_BUS_DEVICE(&s->intc);
82     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
83     sysbus_connect_irq(sysbusdev, 0,
84                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
85     sysbus_connect_irq(sysbusdev, 1,
86                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
87     qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
88 
89     if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
90         return;
91     }
92     sysbusdev = SYS_BUS_DEVICE(&s->timer);
93     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
94     sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22));
95     sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23));
96     sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24));
97     sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25));
98     sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67));
99     sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68));
100 
101     memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
102                            &error_fatal);
103     memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
104     create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
105 
106     /* FIXME use qdev NIC properties instead of nd_table[] */
107     if (nd_table[0].used) {
108         qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
109         qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
110     }
111     if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) {
112         return;
113     }
114     sysbusdev = SYS_BUS_DEVICE(&s->emac);
115     sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
116     sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55));
117 
118     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
119         return;
120     }
121     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
122     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56));
123 
124     /* FIXME use a qdev chardev prop instead of serial_hd() */
125     serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
126                    qdev_get_gpio_in(dev, 1),
127                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
128 
129     if (machine_usb(current_machine)) {
130         int i;
131 
132         for (i = 0; i < AW_A10_NUM_USB; i++) {
133             char bus[16];
134 
135             sprintf(bus, "usb-bus.%d", i);
136 
137             object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable",
138                                      true, &error_fatal);
139             sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
140             sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
141                             AW_A10_EHCI_BASE + i * 0x8000);
142             sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
143                                qdev_get_gpio_in(dev, 39 + i));
144 
145             object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
146                                     &error_fatal);
147             sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
148             sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
149                             AW_A10_OHCI_BASE + i * 0x8000);
150             sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
151                                qdev_get_gpio_in(dev, 64 + i));
152         }
153     }
154 
155     /* SD/MMC */
156     object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
157                              OBJECT(get_system_memory()), &error_fatal);
158     sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
159     sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
160     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
161     object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
162                               "sd-bus");
163 
164     /* RTC */
165     sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
166     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
167 }
168 
169 static void aw_a10_class_init(ObjectClass *oc, void *data)
170 {
171     DeviceClass *dc = DEVICE_CLASS(oc);
172 
173     dc->realize = aw_a10_realize;
174     /* Reason: Uses serial_hds and nd_table in realize function */
175     dc->user_creatable = false;
176 }
177 
178 static const TypeInfo aw_a10_type_info = {
179     .name = TYPE_AW_A10,
180     .parent = TYPE_DEVICE,
181     .instance_size = sizeof(AwA10State),
182     .instance_init = aw_a10_init,
183     .class_init = aw_a10_class_init,
184 };
185 
186 static void aw_a10_register_types(void)
187 {
188     type_register_static(&aw_a10_type_info);
189 }
190 
191 type_init(aw_a10_register_types)
192