xref: /openbmc/qemu/hw/arm/allwinner-a10.c (revision c00506aa)
1 /*
2  * Allwinner A10 SoC emulation
3  *
4  * Copyright (C) 2013 Li Guang
5  * Written by Li Guang <lig.fnst@cn.fujitsu.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15  * for more details.
16  */
17 
18 #include "qemu/osdep.h"
19 #include "exec/address-spaces.h"
20 #include "qapi/error.h"
21 #include "qemu/module.h"
22 #include "cpu.h"
23 #include "hw/sysbus.h"
24 #include "hw/arm/allwinner-a10.h"
25 #include "hw/misc/unimp.h"
26 #include "sysemu/sysemu.h"
27 #include "hw/boards.h"
28 #include "hw/usb/hcd-ohci.h"
29 
30 #define AW_A10_MMC0_BASE        0x01c0f000
31 #define AW_A10_PIC_REG_BASE     0x01c20400
32 #define AW_A10_PIT_REG_BASE     0x01c20c00
33 #define AW_A10_UART0_REG_BASE   0x01c28000
34 #define AW_A10_EMAC_BASE        0x01c0b000
35 #define AW_A10_EHCI_BASE        0x01c14000
36 #define AW_A10_OHCI_BASE        0x01c14400
37 #define AW_A10_SATA_BASE        0x01c18000
38 #define AW_A10_RTC_BASE         0x01c20d00
39 
40 static void aw_a10_init(Object *obj)
41 {
42     AwA10State *s = AW_A10(obj);
43 
44     object_initialize_child(obj, "cpu", &s->cpu,
45                             ARM_CPU_TYPE_NAME("cortex-a8"));
46 
47     object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC);
48 
49     object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
50 
51     object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
52 
53     object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
54 
55     if (machine_usb(current_machine)) {
56         int i;
57 
58         for (i = 0; i < AW_A10_NUM_USB; i++) {
59             object_initialize_child(obj, "ehci[*]", &s->ehci[i],
60                                     TYPE_PLATFORM_EHCI);
61             object_initialize_child(obj, "ohci[*]", &s->ohci[i],
62                                     TYPE_SYSBUS_OHCI);
63         }
64     }
65 
66     object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);
67 
68     object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I);
69 }
70 
71 static void aw_a10_realize(DeviceState *dev, Error **errp)
72 {
73     AwA10State *s = AW_A10(dev);
74     SysBusDevice *sysbusdev;
75 
76     if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
77         return;
78     }
79 
80     if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) {
81         return;
82     }
83     sysbusdev = SYS_BUS_DEVICE(&s->intc);
84     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
85     sysbus_connect_irq(sysbusdev, 0,
86                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
87     sysbus_connect_irq(sysbusdev, 1,
88                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
89     qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
90 
91     if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
92         return;
93     }
94     sysbusdev = SYS_BUS_DEVICE(&s->timer);
95     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
96     sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22));
97     sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23));
98     sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24));
99     sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25));
100     sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67));
101     sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68));
102 
103     memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
104                            &error_fatal);
105     memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
106     create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
107 
108     /* FIXME use qdev NIC properties instead of nd_table[] */
109     if (nd_table[0].used) {
110         qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
111         qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
112     }
113     if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) {
114         return;
115     }
116     sysbusdev = SYS_BUS_DEVICE(&s->emac);
117     sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
118     sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55));
119 
120     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
121         return;
122     }
123     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
124     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56));
125 
126     /* FIXME use a qdev chardev prop instead of serial_hd() */
127     serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
128                    qdev_get_gpio_in(dev, 1),
129                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
130 
131     if (machine_usb(current_machine)) {
132         int i;
133 
134         for (i = 0; i < AW_A10_NUM_USB; i++) {
135             char bus[16];
136 
137             sprintf(bus, "usb-bus.%d", i);
138 
139             object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable",
140                                      true, &error_fatal);
141             sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
142             sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
143                             AW_A10_EHCI_BASE + i * 0x8000);
144             sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
145                                qdev_get_gpio_in(dev, 39 + i));
146 
147             object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
148                                     &error_fatal);
149             sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
150             sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
151                             AW_A10_OHCI_BASE + i * 0x8000);
152             sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
153                                qdev_get_gpio_in(dev, 64 + i));
154         }
155     }
156 
157     /* SD/MMC */
158     object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
159                              OBJECT(get_system_memory()), &error_fatal);
160     sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
161     sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
162     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
163     object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
164                               "sd-bus");
165 
166     /* RTC */
167     sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
168     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
169 }
170 
171 static void aw_a10_class_init(ObjectClass *oc, void *data)
172 {
173     DeviceClass *dc = DEVICE_CLASS(oc);
174 
175     dc->realize = aw_a10_realize;
176     /* Reason: Uses serial_hds and nd_table in realize function */
177     dc->user_creatable = false;
178 }
179 
180 static const TypeInfo aw_a10_type_info = {
181     .name = TYPE_AW_A10,
182     .parent = TYPE_DEVICE,
183     .instance_size = sizeof(AwA10State),
184     .instance_init = aw_a10_init,
185     .class_init = aw_a10_class_init,
186 };
187 
188 static void aw_a10_register_types(void)
189 {
190     type_register_static(&aw_a10_type_info);
191 }
192 
193 type_init(aw_a10_register_types)
194