1 /* 2 * Allwinner A10 SoC emulation 3 * 4 * Copyright (C) 2013 Li Guang 5 * Written by Li Guang <lig.fnst@cn.fujitsu.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "exec/address-spaces.h" 20 #include "qapi/error.h" 21 #include "qemu/module.h" 22 #include "cpu.h" 23 #include "hw/sysbus.h" 24 #include "hw/arm/allwinner-a10.h" 25 #include "hw/misc/unimp.h" 26 #include "sysemu/sysemu.h" 27 28 static void aw_a10_init(Object *obj) 29 { 30 AwA10State *s = AW_A10(obj); 31 32 object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), 33 "cortex-a8-" TYPE_ARM_CPU, &error_abort, NULL); 34 35 sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc), 36 TYPE_AW_A10_PIC); 37 38 sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), 39 TYPE_AW_A10_PIT); 40 41 sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), TYPE_AW_EMAC); 42 43 sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata), 44 TYPE_ALLWINNER_AHCI); 45 } 46 47 static void aw_a10_realize(DeviceState *dev, Error **errp) 48 { 49 AwA10State *s = AW_A10(dev); 50 SysBusDevice *sysbusdev; 51 uint8_t i; 52 qemu_irq fiq, irq; 53 Error *err = NULL; 54 55 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 56 if (err != NULL) { 57 error_propagate(errp, err); 58 return; 59 } 60 irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ); 61 fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ); 62 63 object_property_set_bool(OBJECT(&s->intc), true, "realized", &err); 64 if (err != NULL) { 65 error_propagate(errp, err); 66 return; 67 } 68 sysbusdev = SYS_BUS_DEVICE(&s->intc); 69 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE); 70 sysbus_connect_irq(sysbusdev, 0, irq); 71 sysbus_connect_irq(sysbusdev, 1, fiq); 72 for (i = 0; i < AW_A10_PIC_INT_NR; i++) { 73 s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i); 74 } 75 76 object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); 77 if (err != NULL) { 78 error_propagate(errp, err); 79 return; 80 } 81 sysbusdev = SYS_BUS_DEVICE(&s->timer); 82 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE); 83 sysbus_connect_irq(sysbusdev, 0, s->irq[22]); 84 sysbus_connect_irq(sysbusdev, 1, s->irq[23]); 85 sysbus_connect_irq(sysbusdev, 2, s->irq[24]); 86 sysbus_connect_irq(sysbusdev, 3, s->irq[25]); 87 sysbus_connect_irq(sysbusdev, 4, s->irq[67]); 88 sysbus_connect_irq(sysbusdev, 5, s->irq[68]); 89 90 memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB, 91 &error_fatal); 92 memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a); 93 create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB); 94 95 /* FIXME use qdev NIC properties instead of nd_table[] */ 96 if (nd_table[0].used) { 97 qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); 98 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); 99 } 100 object_property_set_bool(OBJECT(&s->emac), true, "realized", &err); 101 if (err != NULL) { 102 error_propagate(errp, err); 103 return; 104 } 105 sysbusdev = SYS_BUS_DEVICE(&s->emac); 106 sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE); 107 sysbus_connect_irq(sysbusdev, 0, s->irq[55]); 108 109 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 110 if (err) { 111 error_propagate(errp, err); 112 return; 113 } 114 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE); 115 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]); 116 117 /* FIXME use a qdev chardev prop instead of serial_hd() */ 118 serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1], 119 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 120 } 121 122 static void aw_a10_class_init(ObjectClass *oc, void *data) 123 { 124 DeviceClass *dc = DEVICE_CLASS(oc); 125 126 dc->realize = aw_a10_realize; 127 /* Reason: Uses serial_hds and nd_table in realize function */ 128 dc->user_creatable = false; 129 } 130 131 static const TypeInfo aw_a10_type_info = { 132 .name = TYPE_AW_A10, 133 .parent = TYPE_DEVICE, 134 .instance_size = sizeof(AwA10State), 135 .instance_init = aw_a10_init, 136 .class_init = aw_a10_class_init, 137 }; 138 139 static void aw_a10_register_types(void) 140 { 141 type_register_static(&aw_a10_type_info); 142 } 143 144 type_init(aw_a10_register_types) 145