1 /* 2 * Allwinner A10 SoC emulation 3 * 4 * Copyright (C) 2013 Li Guang 5 * Written by Li Guang <lig.fnst@cn.fujitsu.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "exec/address-spaces.h" 20 #include "qapi/error.h" 21 #include "qemu/module.h" 22 #include "cpu.h" 23 #include "hw/sysbus.h" 24 #include "hw/arm/allwinner-a10.h" 25 #include "hw/misc/unimp.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/boards.h" 28 #include "hw/usb/hcd-ohci.h" 29 30 #define AW_A10_MMC0_BASE 0x01c0f000 31 #define AW_A10_PIC_REG_BASE 0x01c20400 32 #define AW_A10_PIT_REG_BASE 0x01c20c00 33 #define AW_A10_UART0_REG_BASE 0x01c28000 34 #define AW_A10_EMAC_BASE 0x01c0b000 35 #define AW_A10_EHCI_BASE 0x01c14000 36 #define AW_A10_OHCI_BASE 0x01c14400 37 #define AW_A10_SATA_BASE 0x01c18000 38 #define AW_A10_RTC_BASE 0x01c20d00 39 40 static void aw_a10_init(Object *obj) 41 { 42 AwA10State *s = AW_A10(obj); 43 44 object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), 45 ARM_CPU_TYPE_NAME("cortex-a8"), 46 &error_abort, NULL); 47 48 sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc), 49 TYPE_AW_A10_PIC); 50 51 sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), 52 TYPE_AW_A10_PIT); 53 54 sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), TYPE_AW_EMAC); 55 56 sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata), 57 TYPE_ALLWINNER_AHCI); 58 59 if (machine_usb(current_machine)) { 60 int i; 61 62 for (i = 0; i < AW_A10_NUM_USB; i++) { 63 sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]), 64 sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI); 65 sysbus_init_child_obj(obj, "ohci[*]", OBJECT(&s->ohci[i]), 66 sizeof(s->ohci[i]), TYPE_SYSBUS_OHCI); 67 } 68 } 69 70 sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), 71 TYPE_AW_SDHOST_SUN4I); 72 73 sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc), 74 TYPE_AW_RTC_SUN4I); 75 } 76 77 static void aw_a10_realize(DeviceState *dev, Error **errp) 78 { 79 AwA10State *s = AW_A10(dev); 80 SysBusDevice *sysbusdev; 81 Error *err = NULL; 82 83 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 84 if (err != NULL) { 85 error_propagate(errp, err); 86 return; 87 } 88 89 object_property_set_bool(OBJECT(&s->intc), true, "realized", &err); 90 if (err != NULL) { 91 error_propagate(errp, err); 92 return; 93 } 94 sysbusdev = SYS_BUS_DEVICE(&s->intc); 95 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE); 96 sysbus_connect_irq(sysbusdev, 0, 97 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 98 sysbus_connect_irq(sysbusdev, 1, 99 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 100 qdev_pass_gpios(DEVICE(&s->intc), dev, NULL); 101 102 object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); 103 if (err != NULL) { 104 error_propagate(errp, err); 105 return; 106 } 107 sysbusdev = SYS_BUS_DEVICE(&s->timer); 108 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE); 109 sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22)); 110 sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23)); 111 sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24)); 112 sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25)); 113 sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67)); 114 sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68)); 115 116 memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB, 117 &error_fatal); 118 memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a); 119 create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB); 120 121 /* FIXME use qdev NIC properties instead of nd_table[] */ 122 if (nd_table[0].used) { 123 qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); 124 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); 125 } 126 object_property_set_bool(OBJECT(&s->emac), true, "realized", &err); 127 if (err != NULL) { 128 error_propagate(errp, err); 129 return; 130 } 131 sysbusdev = SYS_BUS_DEVICE(&s->emac); 132 sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE); 133 sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55)); 134 135 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 136 if (err) { 137 error_propagate(errp, err); 138 return; 139 } 140 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE); 141 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56)); 142 143 /* FIXME use a qdev chardev prop instead of serial_hd() */ 144 serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, 145 qdev_get_gpio_in(dev, 1), 146 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 147 148 if (machine_usb(current_machine)) { 149 int i; 150 151 for (i = 0; i < AW_A10_NUM_USB; i++) { 152 char bus[16]; 153 154 sprintf(bus, "usb-bus.%d", i); 155 156 object_property_set_bool(OBJECT(&s->ehci[i]), true, 157 "companion-enable", &error_fatal); 158 object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", 159 &error_fatal); 160 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 161 AW_A10_EHCI_BASE + i * 0x8000); 162 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 163 qdev_get_gpio_in(dev, 39 + i)); 164 165 object_property_set_str(OBJECT(&s->ohci[i]), bus, "masterbus", 166 &error_fatal); 167 object_property_set_bool(OBJECT(&s->ohci[i]), true, "realized", 168 &error_fatal); 169 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, 170 AW_A10_OHCI_BASE + i * 0x8000); 171 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0, 172 qdev_get_gpio_in(dev, 64 + i)); 173 } 174 } 175 176 /* SD/MMC */ 177 qdev_init_nofail(DEVICE(&s->mmc0)); 178 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE); 179 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32)); 180 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), 181 "sd-bus", &error_abort); 182 183 /* RTC */ 184 qdev_init_nofail(DEVICE(&s->rtc)); 185 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10); 186 } 187 188 static void aw_a10_class_init(ObjectClass *oc, void *data) 189 { 190 DeviceClass *dc = DEVICE_CLASS(oc); 191 192 dc->realize = aw_a10_realize; 193 /* Reason: Uses serial_hds and nd_table in realize function */ 194 dc->user_creatable = false; 195 } 196 197 static const TypeInfo aw_a10_type_info = { 198 .name = TYPE_AW_A10, 199 .parent = TYPE_DEVICE, 200 .instance_size = sizeof(AwA10State), 201 .instance_init = aw_a10_init, 202 .class_init = aw_a10_class_init, 203 }; 204 205 static void aw_a10_register_types(void) 206 { 207 type_register_static(&aw_a10_type_info); 208 } 209 210 type_init(aw_a10_register_types) 211