1 /* 2 * DEC 21272 (TSUNAMI/TYPHOON) chipset emulation. 3 * 4 * Written by Richard Henderson. 5 * 6 * This work is licensed under the GNU GPL license version 2 or later. 7 */ 8 9 #include "cpu.h" 10 #include "hw/hw.h" 11 #include "hw/devices.h" 12 #include "sysemu/sysemu.h" 13 #include "alpha_sys.h" 14 #include "exec/address-spaces.h" 15 16 17 #define TYPE_TYPHOON_PCI_HOST_BRIDGE "typhoon-pcihost" 18 19 typedef struct TyphoonCchip { 20 MemoryRegion region; 21 uint64_t misc; 22 uint64_t drir; 23 uint64_t dim[4]; 24 uint32_t iic[4]; 25 AlphaCPU *cpu[4]; 26 } TyphoonCchip; 27 28 typedef struct TyphoonWindow { 29 uint32_t base_addr; 30 uint32_t mask; 31 uint32_t translated_base_pfn; 32 } TyphoonWindow; 33 34 typedef struct TyphoonPchip { 35 MemoryRegion region; 36 MemoryRegion reg_iack; 37 MemoryRegion reg_mem; 38 MemoryRegion reg_io; 39 MemoryRegion reg_conf; 40 uint64_t ctl; 41 TyphoonWindow win[4]; 42 } TyphoonPchip; 43 44 #define TYPHOON_PCI_HOST_BRIDGE(obj) \ 45 OBJECT_CHECK(TyphoonState, (obj), TYPE_TYPHOON_PCI_HOST_BRIDGE) 46 47 typedef struct TyphoonState { 48 PCIHostState parent_obj; 49 50 TyphoonCchip cchip; 51 TyphoonPchip pchip; 52 MemoryRegion dchip_region; 53 MemoryRegion ram_region; 54 } TyphoonState; 55 56 /* Called when one of DRIR or DIM changes. */ 57 static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) 58 { 59 /* If there are any non-masked interrupts, tell the cpu. */ 60 if (cpu != NULL) { 61 CPUState *cs = CPU(cpu); 62 if (req) { 63 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 64 } else { 65 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 66 } 67 } 68 } 69 70 static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) 71 { 72 CPUState *cpu = current_cpu; 73 TyphoonState *s = opaque; 74 uint64_t ret = 0; 75 76 switch (addr) { 77 case 0x0000: 78 /* CSC: Cchip System Configuration Register. */ 79 /* All sorts of data here; probably the only thing relevant is 80 PIP<14> Pchip 1 Present = 0. */ 81 break; 82 83 case 0x0040: 84 /* MTR: Memory Timing Register. */ 85 /* All sorts of stuff related to real DRAM. */ 86 break; 87 88 case 0x0080: 89 /* MISC: Miscellaneous Register. */ 90 ret = s->cchip.misc | (cpu->cpu_index & 3); 91 break; 92 93 case 0x00c0: 94 /* MPD: Memory Presence Detect Register. */ 95 break; 96 97 case 0x0100: /* AAR0 */ 98 case 0x0140: /* AAR1 */ 99 case 0x0180: /* AAR2 */ 100 case 0x01c0: /* AAR3 */ 101 /* AAR: Array Address Register. */ 102 /* All sorts of information about DRAM. */ 103 break; 104 105 case 0x0200: 106 /* DIM0: Device Interrupt Mask Register, CPU0. */ 107 ret = s->cchip.dim[0]; 108 break; 109 case 0x0240: 110 /* DIM1: Device Interrupt Mask Register, CPU1. */ 111 ret = s->cchip.dim[1]; 112 break; 113 case 0x0280: 114 /* DIR0: Device Interrupt Request Register, CPU0. */ 115 ret = s->cchip.dim[0] & s->cchip.drir; 116 break; 117 case 0x02c0: 118 /* DIR1: Device Interrupt Request Register, CPU1. */ 119 ret = s->cchip.dim[1] & s->cchip.drir; 120 break; 121 case 0x0300: 122 /* DRIR: Device Raw Interrupt Request Register. */ 123 ret = s->cchip.drir; 124 break; 125 126 case 0x0340: 127 /* PRBEN: Probe Enable Register. */ 128 break; 129 130 case 0x0380: 131 /* IIC0: Interval Ignore Count Register, CPU0. */ 132 ret = s->cchip.iic[0]; 133 break; 134 case 0x03c0: 135 /* IIC1: Interval Ignore Count Register, CPU1. */ 136 ret = s->cchip.iic[1]; 137 break; 138 139 case 0x0400: /* MPR0 */ 140 case 0x0440: /* MPR1 */ 141 case 0x0480: /* MPR2 */ 142 case 0x04c0: /* MPR3 */ 143 /* MPR: Memory Programming Register. */ 144 break; 145 146 case 0x0580: 147 /* TTR: TIGbus Timing Register. */ 148 /* All sorts of stuff related to interrupt delivery timings. */ 149 break; 150 case 0x05c0: 151 /* TDR: TIGbug Device Timing Register. */ 152 break; 153 154 case 0x0600: 155 /* DIM2: Device Interrupt Mask Register, CPU2. */ 156 ret = s->cchip.dim[2]; 157 break; 158 case 0x0640: 159 /* DIM3: Device Interrupt Mask Register, CPU3. */ 160 ret = s->cchip.dim[3]; 161 break; 162 case 0x0680: 163 /* DIR2: Device Interrupt Request Register, CPU2. */ 164 ret = s->cchip.dim[2] & s->cchip.drir; 165 break; 166 case 0x06c0: 167 /* DIR3: Device Interrupt Request Register, CPU3. */ 168 ret = s->cchip.dim[3] & s->cchip.drir; 169 break; 170 171 case 0x0700: 172 /* IIC2: Interval Ignore Count Register, CPU2. */ 173 ret = s->cchip.iic[2]; 174 break; 175 case 0x0740: 176 /* IIC3: Interval Ignore Count Register, CPU3. */ 177 ret = s->cchip.iic[3]; 178 break; 179 180 case 0x0780: 181 /* PWR: Power Management Control. */ 182 break; 183 184 case 0x0c00: /* CMONCTLA */ 185 case 0x0c40: /* CMONCTLB */ 186 case 0x0c80: /* CMONCNT01 */ 187 case 0x0cc0: /* CMONCNT23 */ 188 break; 189 190 default: 191 cpu_unassigned_access(cpu, addr, false, false, 0, size); 192 return -1; 193 } 194 195 return ret; 196 } 197 198 static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size) 199 { 200 /* Skip this. It's all related to DRAM timing and setup. */ 201 return 0; 202 } 203 204 static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) 205 { 206 TyphoonState *s = opaque; 207 uint64_t ret = 0; 208 209 switch (addr) { 210 case 0x0000: 211 /* WSBA0: Window Space Base Address Register. */ 212 ret = s->pchip.win[0].base_addr; 213 break; 214 case 0x0040: 215 /* WSBA1 */ 216 ret = s->pchip.win[1].base_addr; 217 break; 218 case 0x0080: 219 /* WSBA2 */ 220 ret = s->pchip.win[2].base_addr; 221 break; 222 case 0x00c0: 223 /* WSBA3 */ 224 ret = s->pchip.win[3].base_addr; 225 break; 226 227 case 0x0100: 228 /* WSM0: Window Space Mask Register. */ 229 ret = s->pchip.win[0].mask; 230 break; 231 case 0x0140: 232 /* WSM1 */ 233 ret = s->pchip.win[1].mask; 234 break; 235 case 0x0180: 236 /* WSM2 */ 237 ret = s->pchip.win[2].mask; 238 break; 239 case 0x01c0: 240 /* WSM3 */ 241 ret = s->pchip.win[3].mask; 242 break; 243 244 case 0x0200: 245 /* TBA0: Translated Base Address Register. */ 246 ret = (uint64_t)s->pchip.win[0].translated_base_pfn << 10; 247 break; 248 case 0x0240: 249 /* TBA1 */ 250 ret = (uint64_t)s->pchip.win[1].translated_base_pfn << 10; 251 break; 252 case 0x0280: 253 /* TBA2 */ 254 ret = (uint64_t)s->pchip.win[2].translated_base_pfn << 10; 255 break; 256 case 0x02c0: 257 /* TBA3 */ 258 ret = (uint64_t)s->pchip.win[3].translated_base_pfn << 10; 259 break; 260 261 case 0x0300: 262 /* PCTL: Pchip Control Register. */ 263 ret = s->pchip.ctl; 264 break; 265 case 0x0340: 266 /* PLAT: Pchip Master Latency Register. */ 267 break; 268 case 0x03c0: 269 /* PERROR: Pchip Error Register. */ 270 break; 271 case 0x0400: 272 /* PERRMASK: Pchip Error Mask Register. */ 273 break; 274 case 0x0440: 275 /* PERRSET: Pchip Error Set Register. */ 276 break; 277 case 0x0480: 278 /* TLBIV: Translation Buffer Invalidate Virtual Register (WO). */ 279 break; 280 case 0x04c0: 281 /* TLBIA: Translation Buffer Invalidate All Register (WO). */ 282 break; 283 case 0x0500: /* PMONCTL */ 284 case 0x0540: /* PMONCNT */ 285 case 0x0800: /* SPRST */ 286 break; 287 288 default: 289 cpu_unassigned_access(current_cpu, addr, false, false, 0, size); 290 return -1; 291 } 292 293 return ret; 294 } 295 296 static void cchip_write(void *opaque, hwaddr addr, 297 uint64_t val, unsigned size) 298 { 299 TyphoonState *s = opaque; 300 uint64_t oldval, newval; 301 302 switch (addr) { 303 case 0x0000: 304 /* CSC: Cchip System Configuration Register. */ 305 /* All sorts of data here; nothing relevant RW. */ 306 break; 307 308 case 0x0040: 309 /* MTR: Memory Timing Register. */ 310 /* All sorts of stuff related to real DRAM. */ 311 break; 312 313 case 0x0080: 314 /* MISC: Miscellaneous Register. */ 315 newval = oldval = s->cchip.misc; 316 newval &= ~(val & 0x10000ff0); /* W1C fields */ 317 if (val & 0x100000) { 318 newval &= ~0xff0000ull; /* ACL clears ABT and ABW */ 319 } else { 320 newval |= val & 0x00f00000; /* ABT field is W1S */ 321 if ((newval & 0xf0000) == 0) { 322 newval |= val & 0xf0000; /* ABW field is W1S iff zero */ 323 } 324 } 325 newval |= (val & 0xf000) >> 4; /* IPREQ field sets IPINTR. */ 326 327 newval &= ~0xf0000000000ull; /* WO and RW fields */ 328 newval |= val & 0xf0000000000ull; 329 s->cchip.misc = newval; 330 331 /* Pass on changes to IPI and ITI state. */ 332 if ((newval ^ oldval) & 0xff0) { 333 int i; 334 for (i = 0; i < 4; ++i) { 335 AlphaCPU *cpu = s->cchip.cpu[i]; 336 if (cpu != NULL) { 337 CPUState *cs = CPU(cpu); 338 /* IPI can be either cleared or set by the write. */ 339 if (newval & (1 << (i + 8))) { 340 cpu_interrupt(cs, CPU_INTERRUPT_SMP); 341 } else { 342 cpu_reset_interrupt(cs, CPU_INTERRUPT_SMP); 343 } 344 345 /* ITI can only be cleared by the write. */ 346 if ((newval & (1 << (i + 4))) == 0) { 347 cpu_reset_interrupt(cs, CPU_INTERRUPT_TIMER); 348 } 349 } 350 } 351 } 352 break; 353 354 case 0x00c0: 355 /* MPD: Memory Presence Detect Register. */ 356 break; 357 358 case 0x0100: /* AAR0 */ 359 case 0x0140: /* AAR1 */ 360 case 0x0180: /* AAR2 */ 361 case 0x01c0: /* AAR3 */ 362 /* AAR: Array Address Register. */ 363 /* All sorts of information about DRAM. */ 364 break; 365 366 case 0x0200: /* DIM0 */ 367 /* DIM: Device Interrupt Mask Register, CPU0. */ 368 s->cchip.dim[0] = val; 369 cpu_irq_change(s->cchip.cpu[0], val & s->cchip.drir); 370 break; 371 case 0x0240: /* DIM1 */ 372 /* DIM: Device Interrupt Mask Register, CPU1. */ 373 s->cchip.dim[0] = val; 374 cpu_irq_change(s->cchip.cpu[1], val & s->cchip.drir); 375 break; 376 377 case 0x0280: /* DIR0 (RO) */ 378 case 0x02c0: /* DIR1 (RO) */ 379 case 0x0300: /* DRIR (RO) */ 380 break; 381 382 case 0x0340: 383 /* PRBEN: Probe Enable Register. */ 384 break; 385 386 case 0x0380: /* IIC0 */ 387 s->cchip.iic[0] = val & 0xffffff; 388 break; 389 case 0x03c0: /* IIC1 */ 390 s->cchip.iic[1] = val & 0xffffff; 391 break; 392 393 case 0x0400: /* MPR0 */ 394 case 0x0440: /* MPR1 */ 395 case 0x0480: /* MPR2 */ 396 case 0x04c0: /* MPR3 */ 397 /* MPR: Memory Programming Register. */ 398 break; 399 400 case 0x0580: 401 /* TTR: TIGbus Timing Register. */ 402 /* All sorts of stuff related to interrupt delivery timings. */ 403 break; 404 case 0x05c0: 405 /* TDR: TIGbug Device Timing Register. */ 406 break; 407 408 case 0x0600: 409 /* DIM2: Device Interrupt Mask Register, CPU2. */ 410 s->cchip.dim[2] = val; 411 cpu_irq_change(s->cchip.cpu[2], val & s->cchip.drir); 412 break; 413 case 0x0640: 414 /* DIM3: Device Interrupt Mask Register, CPU3. */ 415 s->cchip.dim[3] = val; 416 cpu_irq_change(s->cchip.cpu[3], val & s->cchip.drir); 417 break; 418 419 case 0x0680: /* DIR2 (RO) */ 420 case 0x06c0: /* DIR3 (RO) */ 421 break; 422 423 case 0x0700: /* IIC2 */ 424 s->cchip.iic[2] = val & 0xffffff; 425 break; 426 case 0x0740: /* IIC3 */ 427 s->cchip.iic[3] = val & 0xffffff; 428 break; 429 430 case 0x0780: 431 /* PWR: Power Management Control. */ 432 break; 433 434 case 0x0c00: /* CMONCTLA */ 435 case 0x0c40: /* CMONCTLB */ 436 case 0x0c80: /* CMONCNT01 */ 437 case 0x0cc0: /* CMONCNT23 */ 438 break; 439 440 default: 441 cpu_unassigned_access(current_cpu, addr, true, false, 0, size); 442 return; 443 } 444 } 445 446 static void dchip_write(void *opaque, hwaddr addr, 447 uint64_t val, unsigned size) 448 { 449 /* Skip this. It's all related to DRAM timing and setup. */ 450 } 451 452 static void pchip_write(void *opaque, hwaddr addr, 453 uint64_t val, unsigned size) 454 { 455 TyphoonState *s = opaque; 456 uint64_t oldval; 457 458 switch (addr) { 459 case 0x0000: 460 /* WSBA0: Window Space Base Address Register. */ 461 s->pchip.win[0].base_addr = val; 462 break; 463 case 0x0040: 464 /* WSBA1 */ 465 s->pchip.win[1].base_addr = val; 466 break; 467 case 0x0080: 468 /* WSBA2 */ 469 s->pchip.win[2].base_addr = val; 470 break; 471 case 0x00c0: 472 /* WSBA3 */ 473 s->pchip.win[3].base_addr = val; 474 break; 475 476 case 0x0100: 477 /* WSM0: Window Space Mask Register. */ 478 s->pchip.win[0].mask = val; 479 break; 480 case 0x0140: 481 /* WSM1 */ 482 s->pchip.win[1].mask = val; 483 break; 484 case 0x0180: 485 /* WSM2 */ 486 s->pchip.win[2].mask = val; 487 break; 488 case 0x01c0: 489 /* WSM3 */ 490 s->pchip.win[3].mask = val; 491 break; 492 493 case 0x0200: 494 /* TBA0: Translated Base Address Register. */ 495 s->pchip.win[0].translated_base_pfn = val >> 10; 496 break; 497 case 0x0240: 498 /* TBA1 */ 499 s->pchip.win[1].translated_base_pfn = val >> 10; 500 break; 501 case 0x0280: 502 /* TBA2 */ 503 s->pchip.win[2].translated_base_pfn = val >> 10; 504 break; 505 case 0x02c0: 506 /* TBA3 */ 507 s->pchip.win[3].translated_base_pfn = val >> 10; 508 break; 509 510 case 0x0300: 511 /* PCTL: Pchip Control Register. */ 512 oldval = s->pchip.ctl; 513 oldval &= ~0x00001cff0fc7ffull; /* RW fields */ 514 oldval |= val & 0x00001cff0fc7ffull; 515 516 s->pchip.ctl = oldval; 517 break; 518 519 case 0x0340: 520 /* PLAT: Pchip Master Latency Register. */ 521 break; 522 case 0x03c0: 523 /* PERROR: Pchip Error Register. */ 524 break; 525 case 0x0400: 526 /* PERRMASK: Pchip Error Mask Register. */ 527 break; 528 case 0x0440: 529 /* PERRSET: Pchip Error Set Register. */ 530 break; 531 532 case 0x0480: 533 /* TLBIV: Translation Buffer Invalidate Virtual Register. */ 534 break; 535 536 case 0x04c0: 537 /* TLBIA: Translation Buffer Invalidate All Register (WO). */ 538 break; 539 540 case 0x0500: 541 /* PMONCTL */ 542 case 0x0540: 543 /* PMONCNT */ 544 case 0x0800: 545 /* SPRST */ 546 break; 547 548 default: 549 cpu_unassigned_access(current_cpu, addr, true, false, 0, size); 550 return; 551 } 552 } 553 554 static const MemoryRegionOps cchip_ops = { 555 .read = cchip_read, 556 .write = cchip_write, 557 .endianness = DEVICE_LITTLE_ENDIAN, 558 .valid = { 559 .min_access_size = 8, 560 .max_access_size = 8, 561 }, 562 .impl = { 563 .min_access_size = 8, 564 .max_access_size = 8, 565 }, 566 }; 567 568 static const MemoryRegionOps dchip_ops = { 569 .read = dchip_read, 570 .write = dchip_write, 571 .endianness = DEVICE_LITTLE_ENDIAN, 572 .valid = { 573 .min_access_size = 8, 574 .max_access_size = 8, 575 }, 576 .impl = { 577 .min_access_size = 8, 578 .max_access_size = 8, 579 }, 580 }; 581 582 static const MemoryRegionOps pchip_ops = { 583 .read = pchip_read, 584 .write = pchip_write, 585 .endianness = DEVICE_LITTLE_ENDIAN, 586 .valid = { 587 .min_access_size = 8, 588 .max_access_size = 8, 589 }, 590 .impl = { 591 .min_access_size = 8, 592 .max_access_size = 8, 593 }, 594 }; 595 596 static void typhoon_set_irq(void *opaque, int irq, int level) 597 { 598 TyphoonState *s = opaque; 599 uint64_t drir; 600 int i; 601 602 /* Set/Reset the bit in CCHIP.DRIR based on IRQ+LEVEL. */ 603 drir = s->cchip.drir; 604 if (level) { 605 drir |= 1ull << irq; 606 } else { 607 drir &= ~(1ull << irq); 608 } 609 s->cchip.drir = drir; 610 611 for (i = 0; i < 4; ++i) { 612 cpu_irq_change(s->cchip.cpu[i], s->cchip.dim[i] & drir); 613 } 614 } 615 616 static void typhoon_set_isa_irq(void *opaque, int irq, int level) 617 { 618 typhoon_set_irq(opaque, 55, level); 619 } 620 621 static void typhoon_set_timer_irq(void *opaque, int irq, int level) 622 { 623 TyphoonState *s = opaque; 624 int i; 625 626 /* Thankfully, the mc146818rtc code doesn't track the IRQ state, 627 and so we don't have to worry about missing interrupts just 628 because we never actually ACK the interrupt. Just ignore any 629 case of the interrupt level going low. */ 630 if (level == 0) { 631 return; 632 } 633 634 /* Deliver the interrupt to each CPU, considering each CPU's IIC. */ 635 for (i = 0; i < 4; ++i) { 636 AlphaCPU *cpu = s->cchip.cpu[i]; 637 if (cpu != NULL) { 638 uint32_t iic = s->cchip.iic[i]; 639 640 /* ??? The verbage in Section 10.2.2.10 isn't 100% clear. 641 Bit 24 is the OverFlow bit, RO, and set when the count 642 decrements past 0. When is OF cleared? My guess is that 643 OF is actually cleared when the IIC is written, and that 644 the ICNT field always decrements. At least, that's an 645 interpretation that makes sense, and "allows the CPU to 646 determine exactly how mant interval timer ticks were 647 skipped". At least within the next 4M ticks... */ 648 649 iic = ((iic - 1) & 0x1ffffff) | (iic & 0x1000000); 650 s->cchip.iic[i] = iic; 651 652 if (iic & 0x1000000) { 653 /* Set the ITI bit for this cpu. */ 654 s->cchip.misc |= 1 << (i + 4); 655 /* And signal the interrupt. */ 656 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_TIMER); 657 } 658 } 659 } 660 } 661 662 static void typhoon_alarm_timer(void *opaque) 663 { 664 TyphoonState *s = (TyphoonState *)((uintptr_t)opaque & ~3); 665 int cpu = (uintptr_t)opaque & 3; 666 667 /* Set the ITI bit for this cpu. */ 668 s->cchip.misc |= 1 << (cpu + 4); 669 cpu_interrupt(CPU(s->cchip.cpu[cpu]), CPU_INTERRUPT_TIMER); 670 } 671 672 PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, 673 qemu_irq *p_rtc_irq, 674 AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq) 675 { 676 const uint64_t MB = 1024 * 1024; 677 const uint64_t GB = 1024 * MB; 678 MemoryRegion *addr_space = get_system_memory(); 679 DeviceState *dev; 680 TyphoonState *s; 681 PCIHostState *phb; 682 PCIBus *b; 683 int i; 684 685 dev = qdev_create(NULL, TYPE_TYPHOON_PCI_HOST_BRIDGE); 686 qdev_init_nofail(dev); 687 688 s = TYPHOON_PCI_HOST_BRIDGE(dev); 689 phb = PCI_HOST_BRIDGE(dev); 690 691 /* Remember the CPUs so that we can deliver interrupts to them. */ 692 for (i = 0; i < 4; i++) { 693 AlphaCPU *cpu = cpus[i]; 694 s->cchip.cpu[i] = cpu; 695 if (cpu != NULL) { 696 cpu->alarm_timer = qemu_new_timer_ns(vm_clock, 697 typhoon_alarm_timer, 698 (void *)((uintptr_t)s + i)); 699 } 700 } 701 702 *p_rtc_irq = *qemu_allocate_irqs(typhoon_set_timer_irq, s, 1); 703 704 /* Main memory region, 0x00.0000.0000. Real hardware supports 32GB, 705 but the address space hole reserved at this point is 8TB. */ 706 memory_region_init_ram(&s->ram_region, OBJECT(s), "ram", ram_size); 707 vmstate_register_ram_global(&s->ram_region); 708 memory_region_add_subregion(addr_space, 0, &s->ram_region); 709 710 /* TIGbus, 0x801.0000.0000, 1GB. */ 711 /* ??? The TIGbus is used for delivering interrupts, and access to 712 the flash ROM. I'm not sure that we need to implement it at all. */ 713 714 /* Pchip0 CSRs, 0x801.8000.0000, 256MB. */ 715 memory_region_init_io(&s->pchip.region, OBJECT(s), &pchip_ops, s, "pchip0", 716 256*MB); 717 memory_region_add_subregion(addr_space, 0x80180000000ULL, 718 &s->pchip.region); 719 720 /* Cchip CSRs, 0x801.A000.0000, 256MB. */ 721 memory_region_init_io(&s->cchip.region, OBJECT(s), &cchip_ops, s, "cchip0", 722 256*MB); 723 memory_region_add_subregion(addr_space, 0x801a0000000ULL, 724 &s->cchip.region); 725 726 /* Dchip CSRs, 0x801.B000.0000, 256MB. */ 727 memory_region_init_io(&s->dchip_region, OBJECT(s), &dchip_ops, s, "dchip0", 728 256*MB); 729 memory_region_add_subregion(addr_space, 0x801b0000000ULL, 730 &s->dchip_region); 731 732 /* Pchip0 PCI memory, 0x800.0000.0000, 4GB. */ 733 memory_region_init(&s->pchip.reg_mem, OBJECT(s), "pci0-mem", 4*GB); 734 memory_region_add_subregion(addr_space, 0x80000000000ULL, 735 &s->pchip.reg_mem); 736 737 /* Pchip0 PCI I/O, 0x801.FC00.0000, 32MB. */ 738 memory_region_init_io(&s->pchip.reg_io, OBJECT(s), &alpha_pci_ignore_ops, 739 NULL, "pci0-io", 32*MB); 740 memory_region_add_subregion(addr_space, 0x801fc000000ULL, 741 &s->pchip.reg_io); 742 743 b = pci_register_bus(dev, "pci", 744 typhoon_set_irq, sys_map_irq, s, 745 &s->pchip.reg_mem, &s->pchip.reg_io, 746 0, 64, TYPE_PCI_BUS); 747 phb->bus = b; 748 749 /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */ 750 memory_region_init_io(&s->pchip.reg_iack, OBJECT(s), &alpha_pci_iack_ops, 751 b, "pci0-iack", 64*MB); 752 memory_region_add_subregion(addr_space, 0x801f8000000ULL, 753 &s->pchip.reg_iack); 754 755 /* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */ 756 memory_region_init_io(&s->pchip.reg_conf, OBJECT(s), &alpha_pci_conf1_ops, 757 b, "pci0-conf", 16*MB); 758 memory_region_add_subregion(addr_space, 0x801fe000000ULL, 759 &s->pchip.reg_conf); 760 761 /* For the record, these are the mappings for the second PCI bus. 762 We can get away with not implementing them because we indicate 763 via the Cchip.CSC<PIP> bit that Pchip1 is not present. */ 764 /* Pchip1 PCI memory, 0x802.0000.0000, 4GB. */ 765 /* Pchip1 CSRs, 0x802.8000.0000, 256MB. */ 766 /* Pchip1 PCI special/interrupt acknowledge, 0x802.F800.0000, 64MB. */ 767 /* Pchip1 PCI I/O, 0x802.FC00.0000, 32MB. */ 768 /* Pchip1 PCI configuration, 0x802.FE00.0000, 16MB. */ 769 770 /* Init the ISA bus. */ 771 /* ??? Technically there should be a cy82c693ub pci-isa bridge. */ 772 { 773 qemu_irq isa_pci_irq, *isa_irqs; 774 775 *isa_bus = isa_bus_new(NULL, &s->pchip.reg_io); 776 isa_pci_irq = *qemu_allocate_irqs(typhoon_set_isa_irq, s, 1); 777 isa_irqs = i8259_init(*isa_bus, isa_pci_irq); 778 isa_bus_irqs(*isa_bus, isa_irqs); 779 } 780 781 return b; 782 } 783 784 static int typhoon_pcihost_init(SysBusDevice *dev) 785 { 786 return 0; 787 } 788 789 static void typhoon_pcihost_class_init(ObjectClass *klass, void *data) 790 { 791 DeviceClass *dc = DEVICE_CLASS(klass); 792 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 793 794 k->init = typhoon_pcihost_init; 795 dc->no_user = 1; 796 } 797 798 static const TypeInfo typhoon_pcihost_info = { 799 .name = TYPE_TYPHOON_PCI_HOST_BRIDGE, 800 .parent = TYPE_PCI_HOST_BRIDGE, 801 .instance_size = sizeof(TyphoonState), 802 .class_init = typhoon_pcihost_class_init, 803 }; 804 805 static void typhoon_register_types(void) 806 { 807 type_register_static(&typhoon_pcihost_info); 808 } 809 810 type_init(typhoon_register_types) 811