1 /* 2 * DEC 21272 (TSUNAMI/TYPHOON) chipset emulation. 3 * 4 * Written by Richard Henderson. 5 * 6 * This work is licensed under the GNU GPL license version 2 or later. 7 */ 8 9 #include "cpu.h" 10 #include "hw/hw.h" 11 #include "hw/devices.h" 12 #include "sysemu/sysemu.h" 13 #include "alpha_sys.h" 14 #include "exec/address-spaces.h" 15 16 17 #define TYPE_TYPHOON_PCI_HOST_BRIDGE "typhoon-pcihost" 18 19 typedef struct TyphoonCchip { 20 MemoryRegion region; 21 uint64_t misc; 22 uint64_t drir; 23 uint64_t dim[4]; 24 uint32_t iic[4]; 25 AlphaCPU *cpu[4]; 26 } TyphoonCchip; 27 28 typedef struct TyphoonWindow { 29 uint32_t base_addr; 30 uint32_t mask; 31 uint32_t translated_base_pfn; 32 } TyphoonWindow; 33 34 typedef struct TyphoonPchip { 35 MemoryRegion region; 36 MemoryRegion reg_iack; 37 MemoryRegion reg_mem; 38 MemoryRegion reg_io; 39 MemoryRegion reg_conf; 40 uint64_t ctl; 41 TyphoonWindow win[4]; 42 } TyphoonPchip; 43 44 #define TYPHOON_PCI_HOST_BRIDGE(obj) \ 45 OBJECT_CHECK(TyphoonState, (obj), TYPE_TYPHOON_PCI_HOST_BRIDGE) 46 47 typedef struct TyphoonState { 48 PCIHostState parent_obj; 49 50 TyphoonCchip cchip; 51 TyphoonPchip pchip; 52 MemoryRegion dchip_region; 53 MemoryRegion ram_region; 54 55 /* QEMU emulation state. */ 56 uint32_t latch_tmp; 57 } TyphoonState; 58 59 /* Called when one of DRIR or DIM changes. */ 60 static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) 61 { 62 /* If there are any non-masked interrupts, tell the cpu. */ 63 if (cpu != NULL) { 64 CPUState *cs = CPU(cpu); 65 if (req) { 66 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 67 } else { 68 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 69 } 70 } 71 } 72 73 static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) 74 { 75 CPUAlphaState *env = cpu_single_env; 76 TyphoonState *s = opaque; 77 CPUState *cpu; 78 uint64_t ret = 0; 79 80 if (addr & 4) { 81 return s->latch_tmp; 82 } 83 84 switch (addr) { 85 case 0x0000: 86 /* CSC: Cchip System Configuration Register. */ 87 /* All sorts of data here; probably the only thing relevant is 88 PIP<14> Pchip 1 Present = 0. */ 89 break; 90 91 case 0x0040: 92 /* MTR: Memory Timing Register. */ 93 /* All sorts of stuff related to real DRAM. */ 94 break; 95 96 case 0x0080: 97 /* MISC: Miscellaneous Register. */ 98 cpu = ENV_GET_CPU(env); 99 ret = s->cchip.misc | (cpu->cpu_index & 3); 100 break; 101 102 case 0x00c0: 103 /* MPD: Memory Presence Detect Register. */ 104 break; 105 106 case 0x0100: /* AAR0 */ 107 case 0x0140: /* AAR1 */ 108 case 0x0180: /* AAR2 */ 109 case 0x01c0: /* AAR3 */ 110 /* AAR: Array Address Register. */ 111 /* All sorts of information about DRAM. */ 112 break; 113 114 case 0x0200: 115 /* DIM0: Device Interrupt Mask Register, CPU0. */ 116 ret = s->cchip.dim[0]; 117 break; 118 case 0x0240: 119 /* DIM1: Device Interrupt Mask Register, CPU1. */ 120 ret = s->cchip.dim[1]; 121 break; 122 case 0x0280: 123 /* DIR0: Device Interrupt Request Register, CPU0. */ 124 ret = s->cchip.dim[0] & s->cchip.drir; 125 break; 126 case 0x02c0: 127 /* DIR1: Device Interrupt Request Register, CPU1. */ 128 ret = s->cchip.dim[1] & s->cchip.drir; 129 break; 130 case 0x0300: 131 /* DRIR: Device Raw Interrupt Request Register. */ 132 ret = s->cchip.drir; 133 break; 134 135 case 0x0340: 136 /* PRBEN: Probe Enable Register. */ 137 break; 138 139 case 0x0380: 140 /* IIC0: Interval Ignore Count Register, CPU0. */ 141 ret = s->cchip.iic[0]; 142 break; 143 case 0x03c0: 144 /* IIC1: Interval Ignore Count Register, CPU1. */ 145 ret = s->cchip.iic[1]; 146 break; 147 148 case 0x0400: /* MPR0 */ 149 case 0x0440: /* MPR1 */ 150 case 0x0480: /* MPR2 */ 151 case 0x04c0: /* MPR3 */ 152 /* MPR: Memory Programming Register. */ 153 break; 154 155 case 0x0580: 156 /* TTR: TIGbus Timing Register. */ 157 /* All sorts of stuff related to interrupt delivery timings. */ 158 break; 159 case 0x05c0: 160 /* TDR: TIGbug Device Timing Register. */ 161 break; 162 163 case 0x0600: 164 /* DIM2: Device Interrupt Mask Register, CPU2. */ 165 ret = s->cchip.dim[2]; 166 break; 167 case 0x0640: 168 /* DIM3: Device Interrupt Mask Register, CPU3. */ 169 ret = s->cchip.dim[3]; 170 break; 171 case 0x0680: 172 /* DIR2: Device Interrupt Request Register, CPU2. */ 173 ret = s->cchip.dim[2] & s->cchip.drir; 174 break; 175 case 0x06c0: 176 /* DIR3: Device Interrupt Request Register, CPU3. */ 177 ret = s->cchip.dim[3] & s->cchip.drir; 178 break; 179 180 case 0x0700: 181 /* IIC2: Interval Ignore Count Register, CPU2. */ 182 ret = s->cchip.iic[2]; 183 break; 184 case 0x0740: 185 /* IIC3: Interval Ignore Count Register, CPU3. */ 186 ret = s->cchip.iic[3]; 187 break; 188 189 case 0x0780: 190 /* PWR: Power Management Control. */ 191 break; 192 193 case 0x0c00: /* CMONCTLA */ 194 case 0x0c40: /* CMONCTLB */ 195 case 0x0c80: /* CMONCNT01 */ 196 case 0x0cc0: /* CMONCNT23 */ 197 break; 198 199 default: 200 cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size); 201 return -1; 202 } 203 204 s->latch_tmp = ret >> 32; 205 return ret; 206 } 207 208 static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size) 209 { 210 /* Skip this. It's all related to DRAM timing and setup. */ 211 return 0; 212 } 213 214 static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) 215 { 216 TyphoonState *s = opaque; 217 uint64_t ret = 0; 218 219 if (addr & 4) { 220 return s->latch_tmp; 221 } 222 223 switch (addr) { 224 case 0x0000: 225 /* WSBA0: Window Space Base Address Register. */ 226 ret = s->pchip.win[0].base_addr; 227 break; 228 case 0x0040: 229 /* WSBA1 */ 230 ret = s->pchip.win[1].base_addr; 231 break; 232 case 0x0080: 233 /* WSBA2 */ 234 ret = s->pchip.win[2].base_addr; 235 break; 236 case 0x00c0: 237 /* WSBA3 */ 238 ret = s->pchip.win[3].base_addr; 239 break; 240 241 case 0x0100: 242 /* WSM0: Window Space Mask Register. */ 243 ret = s->pchip.win[0].mask; 244 break; 245 case 0x0140: 246 /* WSM1 */ 247 ret = s->pchip.win[1].mask; 248 break; 249 case 0x0180: 250 /* WSM2 */ 251 ret = s->pchip.win[2].mask; 252 break; 253 case 0x01c0: 254 /* WSM3 */ 255 ret = s->pchip.win[3].mask; 256 break; 257 258 case 0x0200: 259 /* TBA0: Translated Base Address Register. */ 260 ret = (uint64_t)s->pchip.win[0].translated_base_pfn << 10; 261 break; 262 case 0x0240: 263 /* TBA1 */ 264 ret = (uint64_t)s->pchip.win[1].translated_base_pfn << 10; 265 break; 266 case 0x0280: 267 /* TBA2 */ 268 ret = (uint64_t)s->pchip.win[2].translated_base_pfn << 10; 269 break; 270 case 0x02c0: 271 /* TBA3 */ 272 ret = (uint64_t)s->pchip.win[3].translated_base_pfn << 10; 273 break; 274 275 case 0x0300: 276 /* PCTL: Pchip Control Register. */ 277 ret = s->pchip.ctl; 278 break; 279 case 0x0340: 280 /* PLAT: Pchip Master Latency Register. */ 281 break; 282 case 0x03c0: 283 /* PERROR: Pchip Error Register. */ 284 break; 285 case 0x0400: 286 /* PERRMASK: Pchip Error Mask Register. */ 287 break; 288 case 0x0440: 289 /* PERRSET: Pchip Error Set Register. */ 290 break; 291 case 0x0480: 292 /* TLBIV: Translation Buffer Invalidate Virtual Register (WO). */ 293 break; 294 case 0x04c0: 295 /* TLBIA: Translation Buffer Invalidate All Register (WO). */ 296 break; 297 case 0x0500: /* PMONCTL */ 298 case 0x0540: /* PMONCNT */ 299 case 0x0800: /* SPRST */ 300 break; 301 302 default: 303 cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size); 304 return -1; 305 } 306 307 s->latch_tmp = ret >> 32; 308 return ret; 309 } 310 311 static void cchip_write(void *opaque, hwaddr addr, 312 uint64_t v32, unsigned size) 313 { 314 TyphoonState *s = opaque; 315 uint64_t val, oldval, newval; 316 317 if (addr & 4) { 318 val = v32 << 32 | s->latch_tmp; 319 addr ^= 4; 320 } else { 321 s->latch_tmp = v32; 322 return; 323 } 324 325 switch (addr) { 326 case 0x0000: 327 /* CSC: Cchip System Configuration Register. */ 328 /* All sorts of data here; nothing relevant RW. */ 329 break; 330 331 case 0x0040: 332 /* MTR: Memory Timing Register. */ 333 /* All sorts of stuff related to real DRAM. */ 334 break; 335 336 case 0x0080: 337 /* MISC: Miscellaneous Register. */ 338 newval = oldval = s->cchip.misc; 339 newval &= ~(val & 0x10000ff0); /* W1C fields */ 340 if (val & 0x100000) { 341 newval &= ~0xff0000ull; /* ACL clears ABT and ABW */ 342 } else { 343 newval |= val & 0x00f00000; /* ABT field is W1S */ 344 if ((newval & 0xf0000) == 0) { 345 newval |= val & 0xf0000; /* ABW field is W1S iff zero */ 346 } 347 } 348 newval |= (val & 0xf000) >> 4; /* IPREQ field sets IPINTR. */ 349 350 newval &= ~0xf0000000000ull; /* WO and RW fields */ 351 newval |= val & 0xf0000000000ull; 352 s->cchip.misc = newval; 353 354 /* Pass on changes to IPI and ITI state. */ 355 if ((newval ^ oldval) & 0xff0) { 356 int i; 357 for (i = 0; i < 4; ++i) { 358 AlphaCPU *cpu = s->cchip.cpu[i]; 359 if (cpu != NULL) { 360 CPUState *cs = CPU(cpu); 361 /* IPI can be either cleared or set by the write. */ 362 if (newval & (1 << (i + 8))) { 363 cpu_interrupt(cs, CPU_INTERRUPT_SMP); 364 } else { 365 cpu_reset_interrupt(cs, CPU_INTERRUPT_SMP); 366 } 367 368 /* ITI can only be cleared by the write. */ 369 if ((newval & (1 << (i + 4))) == 0) { 370 cpu_reset_interrupt(cs, CPU_INTERRUPT_TIMER); 371 } 372 } 373 } 374 } 375 break; 376 377 case 0x00c0: 378 /* MPD: Memory Presence Detect Register. */ 379 break; 380 381 case 0x0100: /* AAR0 */ 382 case 0x0140: /* AAR1 */ 383 case 0x0180: /* AAR2 */ 384 case 0x01c0: /* AAR3 */ 385 /* AAR: Array Address Register. */ 386 /* All sorts of information about DRAM. */ 387 break; 388 389 case 0x0200: /* DIM0 */ 390 /* DIM: Device Interrupt Mask Register, CPU0. */ 391 s->cchip.dim[0] = val; 392 cpu_irq_change(s->cchip.cpu[0], val & s->cchip.drir); 393 break; 394 case 0x0240: /* DIM1 */ 395 /* DIM: Device Interrupt Mask Register, CPU1. */ 396 s->cchip.dim[0] = val; 397 cpu_irq_change(s->cchip.cpu[1], val & s->cchip.drir); 398 break; 399 400 case 0x0280: /* DIR0 (RO) */ 401 case 0x02c0: /* DIR1 (RO) */ 402 case 0x0300: /* DRIR (RO) */ 403 break; 404 405 case 0x0340: 406 /* PRBEN: Probe Enable Register. */ 407 break; 408 409 case 0x0380: /* IIC0 */ 410 s->cchip.iic[0] = val & 0xffffff; 411 break; 412 case 0x03c0: /* IIC1 */ 413 s->cchip.iic[1] = val & 0xffffff; 414 break; 415 416 case 0x0400: /* MPR0 */ 417 case 0x0440: /* MPR1 */ 418 case 0x0480: /* MPR2 */ 419 case 0x04c0: /* MPR3 */ 420 /* MPR: Memory Programming Register. */ 421 break; 422 423 case 0x0580: 424 /* TTR: TIGbus Timing Register. */ 425 /* All sorts of stuff related to interrupt delivery timings. */ 426 break; 427 case 0x05c0: 428 /* TDR: TIGbug Device Timing Register. */ 429 break; 430 431 case 0x0600: 432 /* DIM2: Device Interrupt Mask Register, CPU2. */ 433 s->cchip.dim[2] = val; 434 cpu_irq_change(s->cchip.cpu[2], val & s->cchip.drir); 435 break; 436 case 0x0640: 437 /* DIM3: Device Interrupt Mask Register, CPU3. */ 438 s->cchip.dim[3] = val; 439 cpu_irq_change(s->cchip.cpu[3], val & s->cchip.drir); 440 break; 441 442 case 0x0680: /* DIR2 (RO) */ 443 case 0x06c0: /* DIR3 (RO) */ 444 break; 445 446 case 0x0700: /* IIC2 */ 447 s->cchip.iic[2] = val & 0xffffff; 448 break; 449 case 0x0740: /* IIC3 */ 450 s->cchip.iic[3] = val & 0xffffff; 451 break; 452 453 case 0x0780: 454 /* PWR: Power Management Control. */ 455 break; 456 457 case 0x0c00: /* CMONCTLA */ 458 case 0x0c40: /* CMONCTLB */ 459 case 0x0c80: /* CMONCNT01 */ 460 case 0x0cc0: /* CMONCNT23 */ 461 break; 462 463 default: 464 cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size); 465 return; 466 } 467 } 468 469 static void dchip_write(void *opaque, hwaddr addr, 470 uint64_t val, unsigned size) 471 { 472 /* Skip this. It's all related to DRAM timing and setup. */ 473 } 474 475 static void pchip_write(void *opaque, hwaddr addr, 476 uint64_t v32, unsigned size) 477 { 478 TyphoonState *s = opaque; 479 uint64_t val, oldval; 480 481 if (addr & 4) { 482 val = v32 << 32 | s->latch_tmp; 483 addr ^= 4; 484 } else { 485 s->latch_tmp = v32; 486 return; 487 } 488 489 switch (addr) { 490 case 0x0000: 491 /* WSBA0: Window Space Base Address Register. */ 492 s->pchip.win[0].base_addr = val; 493 break; 494 case 0x0040: 495 /* WSBA1 */ 496 s->pchip.win[1].base_addr = val; 497 break; 498 case 0x0080: 499 /* WSBA2 */ 500 s->pchip.win[2].base_addr = val; 501 break; 502 case 0x00c0: 503 /* WSBA3 */ 504 s->pchip.win[3].base_addr = val; 505 break; 506 507 case 0x0100: 508 /* WSM0: Window Space Mask Register. */ 509 s->pchip.win[0].mask = val; 510 break; 511 case 0x0140: 512 /* WSM1 */ 513 s->pchip.win[1].mask = val; 514 break; 515 case 0x0180: 516 /* WSM2 */ 517 s->pchip.win[2].mask = val; 518 break; 519 case 0x01c0: 520 /* WSM3 */ 521 s->pchip.win[3].mask = val; 522 break; 523 524 case 0x0200: 525 /* TBA0: Translated Base Address Register. */ 526 s->pchip.win[0].translated_base_pfn = val >> 10; 527 break; 528 case 0x0240: 529 /* TBA1 */ 530 s->pchip.win[1].translated_base_pfn = val >> 10; 531 break; 532 case 0x0280: 533 /* TBA2 */ 534 s->pchip.win[2].translated_base_pfn = val >> 10; 535 break; 536 case 0x02c0: 537 /* TBA3 */ 538 s->pchip.win[3].translated_base_pfn = val >> 10; 539 break; 540 541 case 0x0300: 542 /* PCTL: Pchip Control Register. */ 543 oldval = s->pchip.ctl; 544 oldval &= ~0x00001cff0fc7ffull; /* RW fields */ 545 oldval |= val & 0x00001cff0fc7ffull; 546 547 s->pchip.ctl = oldval; 548 break; 549 550 case 0x0340: 551 /* PLAT: Pchip Master Latency Register. */ 552 break; 553 case 0x03c0: 554 /* PERROR: Pchip Error Register. */ 555 break; 556 case 0x0400: 557 /* PERRMASK: Pchip Error Mask Register. */ 558 break; 559 case 0x0440: 560 /* PERRSET: Pchip Error Set Register. */ 561 break; 562 563 case 0x0480: 564 /* TLBIV: Translation Buffer Invalidate Virtual Register. */ 565 break; 566 567 case 0x04c0: 568 /* TLBIA: Translation Buffer Invalidate All Register (WO). */ 569 break; 570 571 case 0x0500: 572 /* PMONCTL */ 573 case 0x0540: 574 /* PMONCNT */ 575 case 0x0800: 576 /* SPRST */ 577 break; 578 579 default: 580 cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size); 581 return; 582 } 583 } 584 585 static const MemoryRegionOps cchip_ops = { 586 .read = cchip_read, 587 .write = cchip_write, 588 .endianness = DEVICE_LITTLE_ENDIAN, 589 .valid = { 590 .min_access_size = 4, /* ??? Should be 8. */ 591 .max_access_size = 8, 592 }, 593 .impl = { 594 .min_access_size = 4, 595 .max_access_size = 4, 596 }, 597 }; 598 599 static const MemoryRegionOps dchip_ops = { 600 .read = dchip_read, 601 .write = dchip_write, 602 .endianness = DEVICE_LITTLE_ENDIAN, 603 .valid = { 604 .min_access_size = 4, /* ??? Should be 8. */ 605 .max_access_size = 8, 606 }, 607 .impl = { 608 .min_access_size = 4, 609 .max_access_size = 8, 610 }, 611 }; 612 613 static const MemoryRegionOps pchip_ops = { 614 .read = pchip_read, 615 .write = pchip_write, 616 .endianness = DEVICE_LITTLE_ENDIAN, 617 .valid = { 618 .min_access_size = 4, /* ??? Should be 8. */ 619 .max_access_size = 8, 620 }, 621 .impl = { 622 .min_access_size = 4, 623 .max_access_size = 4, 624 }, 625 }; 626 627 static void typhoon_set_irq(void *opaque, int irq, int level) 628 { 629 TyphoonState *s = opaque; 630 uint64_t drir; 631 int i; 632 633 /* Set/Reset the bit in CCHIP.DRIR based on IRQ+LEVEL. */ 634 drir = s->cchip.drir; 635 if (level) { 636 drir |= 1ull << irq; 637 } else { 638 drir &= ~(1ull << irq); 639 } 640 s->cchip.drir = drir; 641 642 for (i = 0; i < 4; ++i) { 643 cpu_irq_change(s->cchip.cpu[i], s->cchip.dim[i] & drir); 644 } 645 } 646 647 static void typhoon_set_isa_irq(void *opaque, int irq, int level) 648 { 649 typhoon_set_irq(opaque, 55, level); 650 } 651 652 static void typhoon_set_timer_irq(void *opaque, int irq, int level) 653 { 654 TyphoonState *s = opaque; 655 int i; 656 657 /* Thankfully, the mc146818rtc code doesn't track the IRQ state, 658 and so we don't have to worry about missing interrupts just 659 because we never actually ACK the interrupt. Just ignore any 660 case of the interrupt level going low. */ 661 if (level == 0) { 662 return; 663 } 664 665 /* Deliver the interrupt to each CPU, considering each CPU's IIC. */ 666 for (i = 0; i < 4; ++i) { 667 AlphaCPU *cpu = s->cchip.cpu[i]; 668 if (cpu != NULL) { 669 uint32_t iic = s->cchip.iic[i]; 670 671 /* ??? The verbage in Section 10.2.2.10 isn't 100% clear. 672 Bit 24 is the OverFlow bit, RO, and set when the count 673 decrements past 0. When is OF cleared? My guess is that 674 OF is actually cleared when the IIC is written, and that 675 the ICNT field always decrements. At least, that's an 676 interpretation that makes sense, and "allows the CPU to 677 determine exactly how mant interval timer ticks were 678 skipped". At least within the next 4M ticks... */ 679 680 iic = ((iic - 1) & 0x1ffffff) | (iic & 0x1000000); 681 s->cchip.iic[i] = iic; 682 683 if (iic & 0x1000000) { 684 /* Set the ITI bit for this cpu. */ 685 s->cchip.misc |= 1 << (i + 4); 686 /* And signal the interrupt. */ 687 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_TIMER); 688 } 689 } 690 } 691 } 692 693 static void typhoon_alarm_timer(void *opaque) 694 { 695 TyphoonState *s = (TyphoonState *)((uintptr_t)opaque & ~3); 696 int cpu = (uintptr_t)opaque & 3; 697 698 /* Set the ITI bit for this cpu. */ 699 s->cchip.misc |= 1 << (cpu + 4); 700 cpu_interrupt(CPU(s->cchip.cpu[cpu]), CPU_INTERRUPT_TIMER); 701 } 702 703 PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, 704 qemu_irq *p_rtc_irq, 705 AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq) 706 { 707 const uint64_t MB = 1024 * 1024; 708 const uint64_t GB = 1024 * MB; 709 MemoryRegion *addr_space = get_system_memory(); 710 MemoryRegion *addr_space_io = get_system_io(); 711 DeviceState *dev; 712 TyphoonState *s; 713 PCIHostState *phb; 714 PCIBus *b; 715 int i; 716 717 dev = qdev_create(NULL, TYPE_TYPHOON_PCI_HOST_BRIDGE); 718 qdev_init_nofail(dev); 719 720 s = TYPHOON_PCI_HOST_BRIDGE(dev); 721 phb = PCI_HOST_BRIDGE(dev); 722 723 /* Remember the CPUs so that we can deliver interrupts to them. */ 724 for (i = 0; i < 4; i++) { 725 AlphaCPU *cpu = cpus[i]; 726 s->cchip.cpu[i] = cpu; 727 if (cpu != NULL) { 728 cpu->alarm_timer = qemu_new_timer_ns(rtc_clock, 729 typhoon_alarm_timer, 730 (void *)((uintptr_t)s + i)); 731 } 732 } 733 734 *p_rtc_irq = *qemu_allocate_irqs(typhoon_set_timer_irq, s, 1); 735 736 /* Main memory region, 0x00.0000.0000. Real hardware supports 32GB, 737 but the address space hole reserved at this point is 8TB. */ 738 memory_region_init_ram(&s->ram_region, "ram", ram_size); 739 vmstate_register_ram_global(&s->ram_region); 740 memory_region_add_subregion(addr_space, 0, &s->ram_region); 741 742 /* TIGbus, 0x801.0000.0000, 1GB. */ 743 /* ??? The TIGbus is used for delivering interrupts, and access to 744 the flash ROM. I'm not sure that we need to implement it at all. */ 745 746 /* Pchip0 CSRs, 0x801.8000.0000, 256MB. */ 747 memory_region_init_io(&s->pchip.region, &pchip_ops, s, "pchip0", 256*MB); 748 memory_region_add_subregion(addr_space, 0x80180000000ULL, 749 &s->pchip.region); 750 751 /* Cchip CSRs, 0x801.A000.0000, 256MB. */ 752 memory_region_init_io(&s->cchip.region, &cchip_ops, s, "cchip0", 256*MB); 753 memory_region_add_subregion(addr_space, 0x801a0000000ULL, 754 &s->cchip.region); 755 756 /* Dchip CSRs, 0x801.B000.0000, 256MB. */ 757 memory_region_init_io(&s->dchip_region, &dchip_ops, s, "dchip0", 256*MB); 758 memory_region_add_subregion(addr_space, 0x801b0000000ULL, 759 &s->dchip_region); 760 761 /* Pchip0 PCI memory, 0x800.0000.0000, 4GB. */ 762 memory_region_init(&s->pchip.reg_mem, "pci0-mem", 4*GB); 763 memory_region_add_subregion(addr_space, 0x80000000000ULL, 764 &s->pchip.reg_mem); 765 766 /* Pchip0 PCI I/O, 0x801.FC00.0000, 32MB. */ 767 /* ??? Ideally we drop the "system" i/o space on the floor and give the 768 PCI subsystem the full address space reserved by the chipset. 769 We can't do that until the MEM and IO paths in memory.c are unified. */ 770 memory_region_init_io(&s->pchip.reg_io, &alpha_pci_bw_io_ops, NULL, 771 "pci0-io", 32*MB); 772 memory_region_add_subregion(addr_space, 0x801fc000000ULL, 773 &s->pchip.reg_io); 774 775 b = pci_register_bus(dev, "pci", 776 typhoon_set_irq, sys_map_irq, s, 777 &s->pchip.reg_mem, addr_space_io, 0, 64, TYPE_PCI_BUS); 778 phb->bus = b; 779 780 /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */ 781 memory_region_init_io(&s->pchip.reg_iack, &alpha_pci_iack_ops, b, 782 "pci0-iack", 64*MB); 783 memory_region_add_subregion(addr_space, 0x801f8000000ULL, 784 &s->pchip.reg_iack); 785 786 /* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */ 787 memory_region_init_io(&s->pchip.reg_conf, &alpha_pci_conf1_ops, b, 788 "pci0-conf", 16*MB); 789 memory_region_add_subregion(addr_space, 0x801fe000000ULL, 790 &s->pchip.reg_conf); 791 792 /* For the record, these are the mappings for the second PCI bus. 793 We can get away with not implementing them because we indicate 794 via the Cchip.CSC<PIP> bit that Pchip1 is not present. */ 795 /* Pchip1 PCI memory, 0x802.0000.0000, 4GB. */ 796 /* Pchip1 CSRs, 0x802.8000.0000, 256MB. */ 797 /* Pchip1 PCI special/interrupt acknowledge, 0x802.F800.0000, 64MB. */ 798 /* Pchip1 PCI I/O, 0x802.FC00.0000, 32MB. */ 799 /* Pchip1 PCI configuration, 0x802.FE00.0000, 16MB. */ 800 801 /* Init the ISA bus. */ 802 /* ??? Technically there should be a cy82c693ub pci-isa bridge. */ 803 { 804 qemu_irq isa_pci_irq, *isa_irqs; 805 806 *isa_bus = isa_bus_new(NULL, addr_space_io); 807 isa_pci_irq = *qemu_allocate_irqs(typhoon_set_isa_irq, s, 1); 808 isa_irqs = i8259_init(*isa_bus, isa_pci_irq); 809 isa_bus_irqs(*isa_bus, isa_irqs); 810 } 811 812 return b; 813 } 814 815 static int typhoon_pcihost_init(SysBusDevice *dev) 816 { 817 return 0; 818 } 819 820 static void typhoon_pcihost_class_init(ObjectClass *klass, void *data) 821 { 822 DeviceClass *dc = DEVICE_CLASS(klass); 823 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 824 825 k->init = typhoon_pcihost_init; 826 dc->no_user = 1; 827 } 828 829 static const TypeInfo typhoon_pcihost_info = { 830 .name = TYPE_TYPHOON_PCI_HOST_BRIDGE, 831 .parent = TYPE_PCI_HOST_BRIDGE, 832 .instance_size = sizeof(TyphoonState), 833 .class_init = typhoon_pcihost_class_init, 834 }; 835 836 static void typhoon_register_types(void) 837 { 838 type_register_static(&typhoon_pcihost_info); 839 } 840 841 type_init(typhoon_register_types) 842