1 /* 2 * QEMU Alpha PCI support functions. 3 * 4 * Some of this isn't very Alpha specific at all. 5 * 6 * ??? Sparse memory access not implemented. 7 */ 8 9 #include "config.h" 10 #include "alpha_sys.h" 11 #include "qemu/log.h" 12 #include "sysemu/sysemu.h" 13 14 15 /* PCI IO reads/writes, to byte-word addressable memory. */ 16 /* ??? Doesn't handle multiple PCI busses. */ 17 18 static uint64_t bw_io_read(void *opaque, hwaddr addr, unsigned size) 19 { 20 switch (size) { 21 case 1: 22 return cpu_inb(addr); 23 case 2: 24 return cpu_inw(addr); 25 case 4: 26 return cpu_inl(addr); 27 } 28 abort(); 29 } 30 31 static void bw_io_write(void *opaque, hwaddr addr, 32 uint64_t val, unsigned size) 33 { 34 switch (size) { 35 case 1: 36 cpu_outb(addr, val); 37 break; 38 case 2: 39 cpu_outw(addr, val); 40 break; 41 case 4: 42 cpu_outl(addr, val); 43 break; 44 default: 45 abort(); 46 } 47 } 48 49 const MemoryRegionOps alpha_pci_bw_io_ops = { 50 .read = bw_io_read, 51 .write = bw_io_write, 52 .endianness = DEVICE_LITTLE_ENDIAN, 53 .impl = { 54 .min_access_size = 1, 55 .max_access_size = 4, 56 }, 57 }; 58 59 /* PCI config space reads/writes, to byte-word addressable memory. */ 60 static uint64_t bw_conf1_read(void *opaque, hwaddr addr, 61 unsigned size) 62 { 63 PCIBus *b = opaque; 64 return pci_data_read(b, addr, size); 65 } 66 67 static void bw_conf1_write(void *opaque, hwaddr addr, 68 uint64_t val, unsigned size) 69 { 70 PCIBus *b = opaque; 71 pci_data_write(b, addr, val, size); 72 } 73 74 const MemoryRegionOps alpha_pci_conf1_ops = { 75 .read = bw_conf1_read, 76 .write = bw_conf1_write, 77 .endianness = DEVICE_LITTLE_ENDIAN, 78 .impl = { 79 .min_access_size = 1, 80 .max_access_size = 4, 81 }, 82 }; 83 84 /* PCI/EISA Interrupt Acknowledge Cycle. */ 85 86 static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size) 87 { 88 return pic_read_irq(isa_pic); 89 } 90 91 static void special_write(void *opaque, hwaddr addr, 92 uint64_t val, unsigned size) 93 { 94 qemu_log("pci: special write cycle"); 95 } 96 97 const MemoryRegionOps alpha_pci_iack_ops = { 98 .read = iack_read, 99 .write = special_write, 100 .endianness = DEVICE_LITTLE_ENDIAN, 101 .valid = { 102 .min_access_size = 4, 103 .max_access_size = 4, 104 }, 105 .impl = { 106 .min_access_size = 4, 107 .max_access_size = 4, 108 }, 109 }; 110