1 /* 2 * STM32F2XX ADC 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "hw/hw.h" 28 #include "qemu/log.h" 29 #include "hw/adc/stm32f2xx_adc.h" 30 31 #ifndef STM_ADC_ERR_DEBUG 32 #define STM_ADC_ERR_DEBUG 0 33 #endif 34 35 #define DB_PRINT_L(lvl, fmt, args...) do { \ 36 if (STM_ADC_ERR_DEBUG >= lvl) { \ 37 qemu_log("%s: " fmt, __func__, ## args); \ 38 } \ 39 } while (0) 40 41 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 42 43 static void stm32f2xx_adc_reset(DeviceState *dev) 44 { 45 STM32F2XXADCState *s = STM32F2XX_ADC(dev); 46 47 s->adc_sr = 0x00000000; 48 s->adc_cr1 = 0x00000000; 49 s->adc_cr2 = 0x00000000; 50 s->adc_smpr1 = 0x00000000; 51 s->adc_smpr2 = 0x00000000; 52 s->adc_jofr[0] = 0x00000000; 53 s->adc_jofr[1] = 0x00000000; 54 s->adc_jofr[2] = 0x00000000; 55 s->adc_jofr[3] = 0x00000000; 56 s->adc_htr = 0x00000FFF; 57 s->adc_ltr = 0x00000000; 58 s->adc_sqr1 = 0x00000000; 59 s->adc_sqr2 = 0x00000000; 60 s->adc_sqr3 = 0x00000000; 61 s->adc_jsqr = 0x00000000; 62 s->adc_jdr[0] = 0x00000000; 63 s->adc_jdr[1] = 0x00000000; 64 s->adc_jdr[2] = 0x00000000; 65 s->adc_jdr[3] = 0x00000000; 66 s->adc_dr = 0x00000000; 67 } 68 69 static uint32_t stm32f2xx_adc_generate_value(STM32F2XXADCState *s) 70 { 71 /* Attempts to fake some ADC values */ 72 s->adc_dr = s->adc_dr + 7; 73 74 switch ((s->adc_cr1 & ADC_CR1_RES) >> 24) { 75 case 0: 76 /* 12-bit */ 77 s->adc_dr &= 0xFFF; 78 break; 79 case 1: 80 /* 10-bit */ 81 s->adc_dr &= 0x3FF; 82 break; 83 case 2: 84 /* 8-bit */ 85 s->adc_dr &= 0xFF; 86 break; 87 default: 88 /* 6-bit */ 89 s->adc_dr &= 0x3F; 90 } 91 92 if (s->adc_cr2 & ADC_CR2_ALIGN) { 93 return (s->adc_dr << 1) & 0xFFF0; 94 } else { 95 return s->adc_dr; 96 } 97 } 98 99 static uint64_t stm32f2xx_adc_read(void *opaque, hwaddr addr, 100 unsigned int size) 101 { 102 STM32F2XXADCState *s = opaque; 103 104 DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr); 105 106 if (addr >= ADC_COMMON_ADDRESS) { 107 qemu_log_mask(LOG_UNIMP, 108 "%s: ADC Common Register Unsupported\n", __func__); 109 } 110 111 switch (addr) { 112 case ADC_SR: 113 return s->adc_sr; 114 case ADC_CR1: 115 return s->adc_cr1; 116 case ADC_CR2: 117 return s->adc_cr2 & 0xFFFFFFF; 118 case ADC_SMPR1: 119 return s->adc_smpr1; 120 case ADC_SMPR2: 121 return s->adc_smpr2; 122 case ADC_JOFR1: 123 case ADC_JOFR2: 124 case ADC_JOFR3: 125 case ADC_JOFR4: 126 qemu_log_mask(LOG_UNIMP, "%s: " \ 127 "Injection ADC is not implemented, the registers are " \ 128 "included for compatibility\n", __func__); 129 return s->adc_jofr[(addr - ADC_JOFR1) / 4]; 130 case ADC_HTR: 131 return s->adc_htr; 132 case ADC_LTR: 133 return s->adc_ltr; 134 case ADC_SQR1: 135 return s->adc_sqr1; 136 case ADC_SQR2: 137 return s->adc_sqr2; 138 case ADC_SQR3: 139 return s->adc_sqr3; 140 case ADC_JSQR: 141 qemu_log_mask(LOG_UNIMP, "%s: " \ 142 "Injection ADC is not implemented, the registers are " \ 143 "included for compatibility\n", __func__); 144 return s->adc_jsqr; 145 case ADC_JDR1: 146 case ADC_JDR2: 147 case ADC_JDR3: 148 case ADC_JDR4: 149 qemu_log_mask(LOG_UNIMP, "%s: " \ 150 "Injection ADC is not implemented, the registers are " \ 151 "included for compatibility\n", __func__); 152 return s->adc_jdr[(addr - ADC_JDR1) / 4] - 153 s->adc_jofr[(addr - ADC_JDR1) / 4]; 154 case ADC_DR: 155 if ((s->adc_cr2 & ADC_CR2_ADON) && (s->adc_cr2 & ADC_CR2_SWSTART)) { 156 s->adc_cr2 ^= ADC_CR2_SWSTART; 157 return stm32f2xx_adc_generate_value(s); 158 } else { 159 return 0; 160 } 161 default: 162 qemu_log_mask(LOG_GUEST_ERROR, 163 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); 164 } 165 166 return 0; 167 } 168 169 static void stm32f2xx_adc_write(void *opaque, hwaddr addr, 170 uint64_t val64, unsigned int size) 171 { 172 STM32F2XXADCState *s = opaque; 173 uint32_t value = (uint32_t) val64; 174 175 DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", 176 addr, value); 177 178 if (addr >= 0x100) { 179 qemu_log_mask(LOG_UNIMP, 180 "%s: ADC Common Register Unsupported\n", __func__); 181 } 182 183 switch (addr) { 184 case ADC_SR: 185 s->adc_sr &= (value & 0x3F); 186 break; 187 case ADC_CR1: 188 s->adc_cr1 = value; 189 break; 190 case ADC_CR2: 191 s->adc_cr2 = value; 192 break; 193 case ADC_SMPR1: 194 s->adc_smpr1 = value; 195 break; 196 case ADC_SMPR2: 197 s->adc_smpr2 = value; 198 break; 199 case ADC_JOFR1: 200 case ADC_JOFR2: 201 case ADC_JOFR3: 202 case ADC_JOFR4: 203 s->adc_jofr[(addr - ADC_JOFR1) / 4] = (value & 0xFFF); 204 qemu_log_mask(LOG_UNIMP, "%s: " \ 205 "Injection ADC is not implemented, the registers are " \ 206 "included for compatibility\n", __func__); 207 break; 208 case ADC_HTR: 209 s->adc_htr = value; 210 break; 211 case ADC_LTR: 212 s->adc_ltr = value; 213 break; 214 case ADC_SQR1: 215 s->adc_sqr1 = value; 216 break; 217 case ADC_SQR2: 218 s->adc_sqr2 = value; 219 break; 220 case ADC_SQR3: 221 s->adc_sqr3 = value; 222 break; 223 case ADC_JSQR: 224 s->adc_jsqr = value; 225 qemu_log_mask(LOG_UNIMP, "%s: " \ 226 "Injection ADC is not implemented, the registers are " \ 227 "included for compatibility\n", __func__); 228 break; 229 case ADC_JDR1: 230 case ADC_JDR2: 231 case ADC_JDR3: 232 case ADC_JDR4: 233 s->adc_jdr[(addr - ADC_JDR1) / 4] = value; 234 qemu_log_mask(LOG_UNIMP, "%s: " \ 235 "Injection ADC is not implemented, the registers are " \ 236 "included for compatibility\n", __func__); 237 break; 238 default: 239 qemu_log_mask(LOG_GUEST_ERROR, 240 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); 241 } 242 } 243 244 static const MemoryRegionOps stm32f2xx_adc_ops = { 245 .read = stm32f2xx_adc_read, 246 .write = stm32f2xx_adc_write, 247 .endianness = DEVICE_NATIVE_ENDIAN, 248 }; 249 250 static const VMStateDescription vmstate_stm32f2xx_adc = { 251 .name = TYPE_STM32F2XX_ADC, 252 .version_id = 1, 253 .minimum_version_id = 1, 254 .fields = (VMStateField[]) { 255 VMSTATE_UINT32(adc_sr, STM32F2XXADCState), 256 VMSTATE_UINT32(adc_cr1, STM32F2XXADCState), 257 VMSTATE_UINT32(adc_cr2, STM32F2XXADCState), 258 VMSTATE_UINT32(adc_smpr1, STM32F2XXADCState), 259 VMSTATE_UINT32(adc_smpr2, STM32F2XXADCState), 260 VMSTATE_UINT32_ARRAY(adc_jofr, STM32F2XXADCState, 4), 261 VMSTATE_UINT32(adc_htr, STM32F2XXADCState), 262 VMSTATE_UINT32(adc_ltr, STM32F2XXADCState), 263 VMSTATE_UINT32(adc_sqr1, STM32F2XXADCState), 264 VMSTATE_UINT32(adc_sqr2, STM32F2XXADCState), 265 VMSTATE_UINT32(adc_sqr3, STM32F2XXADCState), 266 VMSTATE_UINT32(adc_jsqr, STM32F2XXADCState), 267 VMSTATE_UINT32_ARRAY(adc_jdr, STM32F2XXADCState, 4), 268 VMSTATE_UINT32(adc_dr, STM32F2XXADCState), 269 VMSTATE_END_OF_LIST() 270 } 271 }; 272 273 static void stm32f2xx_adc_init(Object *obj) 274 { 275 STM32F2XXADCState *s = STM32F2XX_ADC(obj); 276 277 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 278 279 memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s, 280 TYPE_STM32F2XX_ADC, 0xFF); 281 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 282 } 283 284 static void stm32f2xx_adc_class_init(ObjectClass *klass, void *data) 285 { 286 DeviceClass *dc = DEVICE_CLASS(klass); 287 288 dc->reset = stm32f2xx_adc_reset; 289 dc->vmsd = &vmstate_stm32f2xx_adc; 290 } 291 292 static const TypeInfo stm32f2xx_adc_info = { 293 .name = TYPE_STM32F2XX_ADC, 294 .parent = TYPE_SYS_BUS_DEVICE, 295 .instance_size = sizeof(STM32F2XXADCState), 296 .instance_init = stm32f2xx_adc_init, 297 .class_init = stm32f2xx_adc_class_init, 298 }; 299 300 static void stm32f2xx_adc_register_types(void) 301 { 302 type_register_static(&stm32f2xx_adc_info); 303 } 304 305 type_init(stm32f2xx_adc_register_types) 306