xref: /openbmc/qemu/hw/acpi/piix4.c (revision fe8adae3)
1 /*
2  * ACPI implementation
3  *
4  * Copyright (c) 2006 Fabrice Bellard
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License version 2.1 as published by the Free Software Foundation.
9  *
10  * This library is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13  * Lesser General Public License for more details.
14  *
15  * You should have received a copy of the GNU Lesser General Public
16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
17  *
18  * Contributions after 2012-01-13 are licensed under the terms of the
19  * GNU GPL, version 2 or (at your option) any later version.
20  */
21 
22 #include "qemu/osdep.h"
23 #include "hw/i386/pc.h"
24 #include "hw/southbridge/piix.h"
25 #include "hw/irq.h"
26 #include "hw/isa/apm.h"
27 #include "hw/i2c/pm_smbus.h"
28 #include "hw/pci/pci.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/acpi/acpi.h"
31 #include "sysemu/runstate.h"
32 #include "sysemu/sysemu.h"
33 #include "sysemu/xen.h"
34 #include "qapi/error.h"
35 #include "qemu/range.h"
36 #include "hw/acpi/pcihp.h"
37 #include "hw/acpi/cpu_hotplug.h"
38 #include "hw/acpi/cpu.h"
39 #include "hw/hotplug.h"
40 #include "hw/mem/pc-dimm.h"
41 #include "hw/mem/nvdimm.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "hw/acpi/acpi_dev_interface.h"
44 #include "migration/vmstate.h"
45 #include "hw/core/cpu.h"
46 #include "trace.h"
47 #include "qom/object.h"
48 
49 #define GPE_BASE 0xafe0
50 #define GPE_LEN 4
51 
52 #define ACPI_PCIHP_ADDR_PIIX4 0xae00
53 
54 struct pci_status {
55     uint32_t up; /* deprecated, maintained for migration compatibility */
56     uint32_t down;
57 };
58 
59 struct PIIX4PMState {
60     /*< private >*/
61     PCIDevice parent_obj;
62     /*< public >*/
63 
64     MemoryRegion io;
65     uint32_t io_base;
66 
67     MemoryRegion io_gpe;
68     ACPIREGS ar;
69 
70     APMState apm;
71 
72     PMSMBus smb;
73     uint32_t smb_io_base;
74 
75     qemu_irq irq;
76     qemu_irq smi_irq;
77     int smm_enabled;
78     bool smm_compat;
79     Notifier machine_ready;
80     Notifier powerdown_notifier;
81 
82     AcpiPciHpState acpi_pci_hotplug;
83     bool use_acpi_hotplug_bridge;
84     bool use_acpi_root_pci_hotplug;
85 
86     uint8_t disable_s3;
87     uint8_t disable_s4;
88     uint8_t s4_val;
89 
90     bool cpu_hotplug_legacy;
91     AcpiCpuHotplug gpe_cpu;
92     CPUHotplugState cpuhp_state;
93 
94     MemHotplugState acpi_memory_hotplug;
95 };
96 
97 OBJECT_DECLARE_SIMPLE_TYPE(PIIX4PMState, PIIX4_PM)
98 
99 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
100                                            PCIBus *bus, PIIX4PMState *s);
101 
102 #define ACPI_ENABLE 0xf1
103 #define ACPI_DISABLE 0xf0
104 
105 static void pm_tmr_timer(ACPIREGS *ar)
106 {
107     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
108     acpi_update_sci(&s->ar, s->irq);
109 }
110 
111 static void apm_ctrl_changed(uint32_t val, void *arg)
112 {
113     PIIX4PMState *s = arg;
114     PCIDevice *d = PCI_DEVICE(s);
115 
116     /* ACPI specs 3.0, 4.7.2.5 */
117     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
118     if (val == ACPI_ENABLE || val == ACPI_DISABLE) {
119         return;
120     }
121 
122     if (d->config[0x5b] & (1 << 1)) {
123         if (s->smi_irq) {
124             qemu_irq_raise(s->smi_irq);
125         }
126     }
127 }
128 
129 static void pm_io_space_update(PIIX4PMState *s)
130 {
131     PCIDevice *d = PCI_DEVICE(s);
132 
133     s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
134     s->io_base &= 0xffc0;
135 
136     memory_region_transaction_begin();
137     memory_region_set_enabled(&s->io, d->config[0x80] & 1);
138     memory_region_set_address(&s->io, s->io_base);
139     memory_region_transaction_commit();
140 }
141 
142 static void smbus_io_space_update(PIIX4PMState *s)
143 {
144     PCIDevice *d = PCI_DEVICE(s);
145 
146     s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
147     s->smb_io_base &= 0xffc0;
148 
149     memory_region_transaction_begin();
150     memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
151     memory_region_set_address(&s->smb.io, s->smb_io_base);
152     memory_region_transaction_commit();
153 }
154 
155 static void pm_write_config(PCIDevice *d,
156                             uint32_t address, uint32_t val, int len)
157 {
158     pci_default_write_config(d, address, val, len);
159     if (range_covers_byte(address, len, 0x80) ||
160         ranges_overlap(address, len, 0x40, 4)) {
161         pm_io_space_update((PIIX4PMState *)d);
162     }
163     if (range_covers_byte(address, len, 0xd2) ||
164         ranges_overlap(address, len, 0x90, 4)) {
165         smbus_io_space_update((PIIX4PMState *)d);
166     }
167 }
168 
169 static int vmstate_acpi_post_load(void *opaque, int version_id)
170 {
171     PIIX4PMState *s = opaque;
172 
173     pm_io_space_update(s);
174     smbus_io_space_update(s);
175     return 0;
176 }
177 
178 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
179  {                                                                   \
180      .name       = (stringify(_field)),                              \
181      .version_id = 0,                                                \
182      .info       = &vmstate_info_uint16,                             \
183      .size       = sizeof(uint16_t),                                 \
184      .flags      = VMS_SINGLE | VMS_POINTER,                         \
185      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
186  }
187 
188 static const VMStateDescription vmstate_gpe = {
189     .name = "gpe",
190     .version_id = 1,
191     .minimum_version_id = 1,
192     .fields = (VMStateField[]) {
193         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
194         VMSTATE_GPE_ARRAY(en, ACPIGPE),
195         VMSTATE_END_OF_LIST()
196     }
197 };
198 
199 static const VMStateDescription vmstate_pci_status = {
200     .name = "pci_status",
201     .version_id = 1,
202     .minimum_version_id = 1,
203     .fields = (VMStateField[]) {
204         VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
205         VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
206         VMSTATE_END_OF_LIST()
207     }
208 };
209 
210 static bool vmstate_test_use_acpi_hotplug_bridge(void *opaque, int version_id)
211 {
212     PIIX4PMState *s = opaque;
213     return s->use_acpi_hotplug_bridge;
214 }
215 
216 static bool vmstate_test_no_use_acpi_hotplug_bridge(void *opaque,
217                                                     int version_id)
218 {
219     PIIX4PMState *s = opaque;
220     return !s->use_acpi_hotplug_bridge;
221 }
222 
223 static bool vmstate_test_use_memhp(void *opaque)
224 {
225     PIIX4PMState *s = opaque;
226     return s->acpi_memory_hotplug.is_enabled;
227 }
228 
229 static const VMStateDescription vmstate_memhp_state = {
230     .name = "piix4_pm/memhp",
231     .version_id = 1,
232     .minimum_version_id = 1,
233     .minimum_version_id_old = 1,
234     .needed = vmstate_test_use_memhp,
235     .fields      = (VMStateField[]) {
236         VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState),
237         VMSTATE_END_OF_LIST()
238     }
239 };
240 
241 static bool vmstate_test_use_cpuhp(void *opaque)
242 {
243     PIIX4PMState *s = opaque;
244     return !s->cpu_hotplug_legacy;
245 }
246 
247 static int vmstate_cpuhp_pre_load(void *opaque)
248 {
249     Object *obj = OBJECT(opaque);
250     object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort);
251     return 0;
252 }
253 
254 static const VMStateDescription vmstate_cpuhp_state = {
255     .name = "piix4_pm/cpuhp",
256     .version_id = 1,
257     .minimum_version_id = 1,
258     .minimum_version_id_old = 1,
259     .needed = vmstate_test_use_cpuhp,
260     .pre_load = vmstate_cpuhp_pre_load,
261     .fields      = (VMStateField[]) {
262         VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState),
263         VMSTATE_END_OF_LIST()
264     }
265 };
266 
267 static bool piix4_vmstate_need_smbus(void *opaque, int version_id)
268 {
269     return pm_smbus_vmstate_needed();
270 }
271 
272 /* qemu-kvm 1.2 uses version 3 but advertised as 2
273  * To support incoming qemu-kvm 1.2 migration, change version_id
274  * and minimum_version_id to 2 below (which breaks migration from
275  * qemu 1.2).
276  *
277  */
278 static const VMStateDescription vmstate_acpi = {
279     .name = "piix4_pm",
280     .version_id = 3,
281     .minimum_version_id = 3,
282     .post_load = vmstate_acpi_post_load,
283     .fields = (VMStateField[]) {
284         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
285         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
286         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
287         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
288         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
289         VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3,
290                             pmsmb_vmstate, PMSMBus),
291         VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
292         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
293         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
294         VMSTATE_STRUCT_TEST(
295             acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
296             PIIX4PMState,
297             vmstate_test_no_use_acpi_hotplug_bridge,
298             2, vmstate_pci_status,
299             struct AcpiPciHpPciStatus),
300         VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
301                             vmstate_test_use_acpi_hotplug_bridge,
302                             vmstate_acpi_pcihp_use_acpi_index),
303         VMSTATE_END_OF_LIST()
304     },
305     .subsections = (const VMStateDescription*[]) {
306          &vmstate_memhp_state,
307          &vmstate_cpuhp_state,
308          NULL
309     }
310 };
311 
312 static void piix4_pm_reset(DeviceState *dev)
313 {
314     PIIX4PMState *s = PIIX4_PM(dev);
315     PCIDevice *d = PCI_DEVICE(s);
316     uint8_t *pci_conf = d->config;
317 
318     pci_conf[0x58] = 0;
319     pci_conf[0x59] = 0;
320     pci_conf[0x5a] = 0;
321     pci_conf[0x5b] = 0;
322 
323     pci_conf[0x40] = 0x01; /* PM io base read only bit */
324     pci_conf[0x80] = 0;
325 
326     if (!s->smm_enabled) {
327         /* Mark SMM as already inited (until KVM supports SMM). */
328         pci_conf[0x5B] = 0x02;
329     }
330 
331     acpi_pm1_evt_reset(&s->ar);
332     acpi_pm1_cnt_reset(&s->ar);
333     acpi_pm_tmr_reset(&s->ar);
334     acpi_gpe_reset(&s->ar);
335     acpi_update_sci(&s->ar, s->irq);
336 
337     pm_io_space_update(s);
338     acpi_pcihp_reset(&s->acpi_pci_hotplug, !s->use_acpi_root_pci_hotplug);
339 }
340 
341 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
342 {
343     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
344 
345     assert(s != NULL);
346     acpi_pm1_evt_power_down(&s->ar);
347 }
348 
349 static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev,
350                                     DeviceState *dev, Error **errp)
351 {
352     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
353 
354     if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
355         acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp);
356     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
357         if (!s->acpi_memory_hotplug.is_enabled) {
358             error_setg(errp,
359                 "memory hotplug is not enabled: %s.memory-hotplug-support "
360                 "is not set", object_get_typename(OBJECT(s)));
361         }
362     } else if (
363                !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
364         error_setg(errp, "acpi: device pre plug request for not supported"
365                    " device type: %s", object_get_typename(OBJECT(dev)));
366     }
367 }
368 
369 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev,
370                                  DeviceState *dev, Error **errp)
371 {
372     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
373 
374     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
375         if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
376             nvdimm_acpi_plug_cb(hotplug_dev, dev);
377         } else {
378             acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug,
379                                 dev, errp);
380         }
381     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
382         acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp);
383     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
384         if (s->cpu_hotplug_legacy) {
385             legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp);
386         } else {
387             acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
388         }
389     } else {
390         g_assert_not_reached();
391     }
392 }
393 
394 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev,
395                                            DeviceState *dev, Error **errp)
396 {
397     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
398 
399     if (s->acpi_memory_hotplug.is_enabled &&
400         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
401         acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug,
402                                       dev, errp);
403     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
404         acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug,
405                                             dev, errp);
406     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
407                !s->cpu_hotplug_legacy) {
408         acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
409     } else {
410         error_setg(errp, "acpi: device unplug request for not supported device"
411                    " type: %s", object_get_typename(OBJECT(dev)));
412     }
413 }
414 
415 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev,
416                                    DeviceState *dev, Error **errp)
417 {
418     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
419 
420     if (s->acpi_memory_hotplug.is_enabled &&
421         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
422         acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp);
423     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
424         acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev,
425                                     errp);
426     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
427                !s->cpu_hotplug_legacy) {
428         acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
429     } else {
430         error_setg(errp, "acpi: device unplug for not supported device"
431                    " type: %s", object_get_typename(OBJECT(dev)));
432     }
433 }
434 
435 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
436 {
437     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
438     PCIDevice *d = PCI_DEVICE(s);
439     MemoryRegion *io_as = pci_address_space_io(d);
440     uint8_t *pci_conf;
441 
442     pci_conf = d->config;
443     pci_conf[0x5f] = 0x10 |
444         (memory_region_present(io_as, 0x378) ? 0x80 : 0);
445     pci_conf[0x63] = 0x60;
446     pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
447         (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
448 }
449 
450 static void piix4_pm_add_properties(PIIX4PMState *s)
451 {
452     static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
453     static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
454     static const uint32_t gpe0_blk = GPE_BASE;
455     static const uint32_t gpe0_blk_len = GPE_LEN;
456     static const uint16_t sci_int = 9;
457 
458     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
459                                   &acpi_enable_cmd, OBJ_PROP_FLAG_READ);
460     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
461                                   &acpi_disable_cmd, OBJ_PROP_FLAG_READ);
462     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
463                                   &gpe0_blk, OBJ_PROP_FLAG_READ);
464     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
465                                   &gpe0_blk_len, OBJ_PROP_FLAG_READ);
466     object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
467                                   &sci_int, OBJ_PROP_FLAG_READ);
468     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
469                                   &s->io_base, OBJ_PROP_FLAG_READ);
470 }
471 
472 static void piix4_pm_realize(PCIDevice *dev, Error **errp)
473 {
474     PIIX4PMState *s = PIIX4_PM(dev);
475     uint8_t *pci_conf;
476 
477     pci_conf = dev->config;
478     pci_conf[0x06] = 0x80;
479     pci_conf[0x07] = 0x02;
480     pci_conf[0x09] = 0x00;
481     pci_conf[0x3d] = 0x01; // interrupt pin 1
482 
483     /* APM */
484     apm_init(dev, &s->apm, apm_ctrl_changed, s);
485 
486     if (!s->smm_enabled) {
487         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
488          * support SMM mode. */
489         pci_conf[0x5B] = 0x02;
490     }
491 
492     /* XXX: which specification is used ? The i82731AB has different
493        mappings */
494     pci_conf[0x90] = s->smb_io_base | 1;
495     pci_conf[0x91] = s->smb_io_base >> 8;
496     pci_conf[0xd2] = 0x09;
497     pm_smbus_init(DEVICE(dev), &s->smb, true);
498     memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
499     memory_region_add_subregion(pci_address_space_io(dev),
500                                 s->smb_io_base, &s->smb.io);
501 
502     memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
503     memory_region_set_enabled(&s->io, false);
504     memory_region_add_subregion(pci_address_space_io(dev),
505                                 0, &s->io);
506 
507     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
508     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
509     acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val,
510                       !s->smm_compat && !s->smm_enabled);
511     acpi_gpe_init(&s->ar, GPE_LEN);
512 
513     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
514     qemu_register_powerdown_notifier(&s->powerdown_notifier);
515 
516     s->machine_ready.notify = piix4_pm_machine_ready;
517     qemu_add_machine_init_done_notifier(&s->machine_ready);
518 
519     piix4_acpi_system_hot_add_init(pci_address_space_io(dev),
520                                    pci_get_bus(dev), s);
521     qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s));
522 
523     piix4_pm_add_properties(s);
524 }
525 
526 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
527                       qemu_irq sci_irq, qemu_irq smi_irq,
528                       int smm_enabled, DeviceState **piix4_pm)
529 {
530     PCIDevice *pci_dev;
531     DeviceState *dev;
532     PIIX4PMState *s;
533 
534     pci_dev = pci_new(devfn, TYPE_PIIX4_PM);
535     dev = DEVICE(pci_dev);
536     qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
537     if (piix4_pm) {
538         *piix4_pm = dev;
539     }
540 
541     s = PIIX4_PM(dev);
542     s->irq = sci_irq;
543     s->smi_irq = smi_irq;
544     s->smm_enabled = smm_enabled;
545     if (xen_enabled()) {
546         s->use_acpi_hotplug_bridge = false;
547     }
548 
549     pci_realize_and_unref(pci_dev, bus, &error_fatal);
550 
551     return s->smb.smbus;
552 }
553 
554 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
555 {
556     PIIX4PMState *s = opaque;
557     uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
558 
559     trace_piix4_gpe_readb(addr, width, val);
560     return val;
561 }
562 
563 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
564                        unsigned width)
565 {
566     PIIX4PMState *s = opaque;
567 
568     trace_piix4_gpe_writeb(addr, width, val);
569     acpi_gpe_ioport_writeb(&s->ar, addr, val);
570     acpi_update_sci(&s->ar, s->irq);
571 }
572 
573 static const MemoryRegionOps piix4_gpe_ops = {
574     .read = gpe_readb,
575     .write = gpe_writeb,
576     .valid.min_access_size = 1,
577     .valid.max_access_size = 4,
578     .impl.min_access_size = 1,
579     .impl.max_access_size = 1,
580     .endianness = DEVICE_LITTLE_ENDIAN,
581 };
582 
583 
584 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp)
585 {
586     PIIX4PMState *s = PIIX4_PM(obj);
587 
588     return s->cpu_hotplug_legacy;
589 }
590 
591 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp)
592 {
593     PIIX4PMState *s = PIIX4_PM(obj);
594 
595     assert(!value);
596     if (s->cpu_hotplug_legacy && value == false) {
597         acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state,
598                                    PIIX4_CPU_HOTPLUG_IO_BASE);
599     }
600     s->cpu_hotplug_legacy = value;
601 }
602 
603 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
604                                            PCIBus *bus, PIIX4PMState *s)
605 {
606     memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
607                           "acpi-gpe0", GPE_LEN);
608     memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
609 
610     if (s->use_acpi_hotplug_bridge || s->use_acpi_root_pci_hotplug) {
611         acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
612                         s->use_acpi_hotplug_bridge, ACPI_PCIHP_ADDR_PIIX4);
613     }
614 
615     s->cpu_hotplug_legacy = true;
616     object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy",
617                              piix4_get_cpu_hotplug_legacy,
618                              piix4_set_cpu_hotplug_legacy);
619     legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu,
620                                  PIIX4_CPU_HOTPLUG_IO_BASE);
621 
622     if (s->acpi_memory_hotplug.is_enabled) {
623         acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug,
624                                  ACPI_MEMORY_HOTPLUG_BASE);
625     }
626 }
627 
628 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
629 {
630     PIIX4PMState *s = PIIX4_PM(adev);
631 
632     acpi_memory_ospm_status(&s->acpi_memory_hotplug, list);
633     if (!s->cpu_hotplug_legacy) {
634         acpi_cpu_ospm_status(&s->cpuhp_state, list);
635     }
636 }
637 
638 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
639 {
640     PIIX4PMState *s = PIIX4_PM(adev);
641 
642     acpi_send_gpe_event(&s->ar, s->irq, ev);
643 }
644 
645 static Property piix4_pm_properties[] = {
646     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
647     DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
648     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
649     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
650     DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, PIIX4PMState,
651                      use_acpi_hotplug_bridge, true),
652     DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCI_ROOTHP, PIIX4PMState,
653                      use_acpi_root_pci_hotplug, true),
654     DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
655                      acpi_memory_hotplug.is_enabled, true),
656     DEFINE_PROP_BOOL("smm-compat", PIIX4PMState, smm_compat, false),
657     DEFINE_PROP_END_OF_LIST(),
658 };
659 
660 static void piix4_pm_class_init(ObjectClass *klass, void *data)
661 {
662     DeviceClass *dc = DEVICE_CLASS(klass);
663     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
664     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
665     AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
666 
667     k->realize = piix4_pm_realize;
668     k->config_write = pm_write_config;
669     k->vendor_id = PCI_VENDOR_ID_INTEL;
670     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
671     k->revision = 0x03;
672     k->class_id = PCI_CLASS_BRIDGE_OTHER;
673     dc->reset = piix4_pm_reset;
674     dc->desc = "PM";
675     dc->vmsd = &vmstate_acpi;
676     device_class_set_props(dc, piix4_pm_properties);
677     /*
678      * Reason: part of PIIX4 southbridge, needs to be wired up,
679      * e.g. by mips_malta_init()
680      */
681     dc->user_creatable = false;
682     dc->hotpluggable = false;
683     hc->pre_plug = piix4_device_pre_plug_cb;
684     hc->plug = piix4_device_plug_cb;
685     hc->unplug_request = piix4_device_unplug_request_cb;
686     hc->unplug = piix4_device_unplug_cb;
687     adevc->ospm_status = piix4_ospm_status;
688     adevc->send_event = piix4_send_gpe;
689     adevc->madt_cpu = pc_madt_cpu_entry;
690 }
691 
692 static const TypeInfo piix4_pm_info = {
693     .name          = TYPE_PIIX4_PM,
694     .parent        = TYPE_PCI_DEVICE,
695     .instance_size = sizeof(PIIX4PMState),
696     .class_init    = piix4_pm_class_init,
697     .interfaces = (InterfaceInfo[]) {
698         { TYPE_HOTPLUG_HANDLER },
699         { TYPE_ACPI_DEVICE_IF },
700         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
701         { }
702     }
703 };
704 
705 static void piix4_pm_register_types(void)
706 {
707     type_register_static(&piix4_pm_info);
708 }
709 
710 type_init(piix4_pm_register_types)
711