1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2.1 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/i386/pc.h" 24 #include "hw/irq.h" 25 #include "hw/isa/apm.h" 26 #include "hw/i2c/pm_smbus.h" 27 #include "hw/pci/pci.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/acpi/acpi.h" 30 #include "hw/acpi/pcihp.h" 31 #include "hw/acpi/piix4.h" 32 #include "sysemu/runstate.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/xen.h" 35 #include "qapi/error.h" 36 #include "qemu/range.h" 37 #include "hw/acpi/cpu_hotplug.h" 38 #include "hw/acpi/cpu.h" 39 #include "hw/hotplug.h" 40 #include "hw/mem/pc-dimm.h" 41 #include "hw/mem/nvdimm.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "hw/acpi/acpi_dev_interface.h" 44 #include "migration/vmstate.h" 45 #include "hw/core/cpu.h" 46 #include "trace.h" 47 #include "qom/object.h" 48 49 #define GPE_BASE 0xafe0 50 #define GPE_LEN 4 51 52 #define ACPI_PCIHP_ADDR_PIIX4 0xae00 53 54 struct pci_status { 55 uint32_t up; /* deprecated, maintained for migration compatibility */ 56 uint32_t down; 57 }; 58 59 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 60 PCIBus *bus, PIIX4PMState *s); 61 62 #define ACPI_ENABLE 0xf1 63 #define ACPI_DISABLE 0xf0 64 65 static void pm_tmr_timer(ACPIREGS *ar) 66 { 67 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 68 acpi_update_sci(&s->ar, s->irq); 69 } 70 71 static void apm_ctrl_changed(uint32_t val, void *arg) 72 { 73 PIIX4PMState *s = arg; 74 PCIDevice *d = PCI_DEVICE(s); 75 76 /* ACPI specs 3.0, 4.7.2.5 */ 77 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 78 if (val == ACPI_ENABLE || val == ACPI_DISABLE) { 79 return; 80 } 81 82 if (d->config[0x5b] & (1 << 1)) { 83 if (s->smi_irq) { 84 qemu_irq_raise(s->smi_irq); 85 } 86 } 87 } 88 89 static void pm_io_space_update(PIIX4PMState *s) 90 { 91 PCIDevice *d = PCI_DEVICE(s); 92 93 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 94 s->io_base &= 0xffc0; 95 96 memory_region_transaction_begin(); 97 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 98 memory_region_set_address(&s->io, s->io_base); 99 memory_region_transaction_commit(); 100 } 101 102 static void smbus_io_space_update(PIIX4PMState *s) 103 { 104 PCIDevice *d = PCI_DEVICE(s); 105 106 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 107 s->smb_io_base &= 0xffc0; 108 109 memory_region_transaction_begin(); 110 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 111 memory_region_set_address(&s->smb.io, s->smb_io_base); 112 memory_region_transaction_commit(); 113 } 114 115 static void pm_write_config(PCIDevice *d, 116 uint32_t address, uint32_t val, int len) 117 { 118 pci_default_write_config(d, address, val, len); 119 if (range_covers_byte(address, len, 0x80) || 120 ranges_overlap(address, len, 0x40, 4)) { 121 pm_io_space_update((PIIX4PMState *)d); 122 } 123 if (range_covers_byte(address, len, 0xd2) || 124 ranges_overlap(address, len, 0x90, 4)) { 125 smbus_io_space_update((PIIX4PMState *)d); 126 } 127 } 128 129 static int vmstate_acpi_post_load(void *opaque, int version_id) 130 { 131 PIIX4PMState *s = opaque; 132 133 pm_io_space_update(s); 134 smbus_io_space_update(s); 135 return 0; 136 } 137 138 #define VMSTATE_GPE_ARRAY(_field, _state) \ 139 { \ 140 .name = (stringify(_field)), \ 141 .version_id = 0, \ 142 .info = &vmstate_info_uint16, \ 143 .size = sizeof(uint16_t), \ 144 .flags = VMS_SINGLE | VMS_POINTER, \ 145 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 146 } 147 148 static const VMStateDescription vmstate_gpe = { 149 .name = "gpe", 150 .version_id = 1, 151 .minimum_version_id = 1, 152 .fields = (VMStateField[]) { 153 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 154 VMSTATE_GPE_ARRAY(en, ACPIGPE), 155 VMSTATE_END_OF_LIST() 156 } 157 }; 158 159 static const VMStateDescription vmstate_pci_status = { 160 .name = "pci_status", 161 .version_id = 1, 162 .minimum_version_id = 1, 163 .fields = (VMStateField[]) { 164 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), 165 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), 166 VMSTATE_END_OF_LIST() 167 } 168 }; 169 170 static bool vmstate_test_use_acpi_hotplug_bridge(void *opaque, int version_id) 171 { 172 PIIX4PMState *s = opaque; 173 return s->acpi_pci_hotplug.use_acpi_hotplug_bridge; 174 } 175 176 static bool vmstate_test_no_use_acpi_hotplug_bridge(void *opaque, 177 int version_id) 178 { 179 PIIX4PMState *s = opaque; 180 return !s->acpi_pci_hotplug.use_acpi_hotplug_bridge; 181 } 182 183 static bool vmstate_test_use_memhp(void *opaque) 184 { 185 PIIX4PMState *s = opaque; 186 return s->acpi_memory_hotplug.is_enabled; 187 } 188 189 static const VMStateDescription vmstate_memhp_state = { 190 .name = "piix4_pm/memhp", 191 .version_id = 1, 192 .minimum_version_id = 1, 193 .needed = vmstate_test_use_memhp, 194 .fields = (VMStateField[]) { 195 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), 196 VMSTATE_END_OF_LIST() 197 } 198 }; 199 200 static bool vmstate_test_use_cpuhp(void *opaque) 201 { 202 PIIX4PMState *s = opaque; 203 return !s->cpu_hotplug_legacy; 204 } 205 206 static int vmstate_cpuhp_pre_load(void *opaque) 207 { 208 Object *obj = OBJECT(opaque); 209 object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort); 210 return 0; 211 } 212 213 static const VMStateDescription vmstate_cpuhp_state = { 214 .name = "piix4_pm/cpuhp", 215 .version_id = 1, 216 .minimum_version_id = 1, 217 .needed = vmstate_test_use_cpuhp, 218 .pre_load = vmstate_cpuhp_pre_load, 219 .fields = (VMStateField[]) { 220 VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), 221 VMSTATE_END_OF_LIST() 222 } 223 }; 224 225 static bool piix4_vmstate_need_smbus(void *opaque, int version_id) 226 { 227 return pm_smbus_vmstate_needed(); 228 } 229 230 /* 231 * This is a fudge to turn off the acpi_index field, 232 * whose test was always broken on piix4 with 6.2 and older machine types. 233 */ 234 static bool vmstate_test_migrate_acpi_index(void *opaque, int version_id) 235 { 236 PIIX4PMState *s = PIIX4_PM(opaque); 237 return s->acpi_pci_hotplug.use_acpi_hotplug_bridge && 238 !s->not_migrate_acpi_index; 239 } 240 241 /* qemu-kvm 1.2 uses version 3 but advertised as 2 242 * To support incoming qemu-kvm 1.2 migration, change version_id 243 * and minimum_version_id to 2 below (which breaks migration from 244 * qemu 1.2). 245 * 246 */ 247 static const VMStateDescription vmstate_acpi = { 248 .name = "piix4_pm", 249 .version_id = 3, 250 .minimum_version_id = 3, 251 .post_load = vmstate_acpi_post_load, 252 .fields = (VMStateField[]) { 253 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 254 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 255 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 256 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 257 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 258 VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3, 259 pmsmb_vmstate, PMSMBus), 260 VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), 261 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 262 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 263 VMSTATE_STRUCT_TEST( 264 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 265 PIIX4PMState, 266 vmstate_test_no_use_acpi_hotplug_bridge, 267 2, vmstate_pci_status, 268 struct AcpiPciHpPciStatus), 269 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 270 vmstate_test_use_acpi_hotplug_bridge, 271 vmstate_test_migrate_acpi_index), 272 VMSTATE_END_OF_LIST() 273 }, 274 .subsections = (const VMStateDescription*[]) { 275 &vmstate_memhp_state, 276 &vmstate_cpuhp_state, 277 NULL 278 } 279 }; 280 281 static void piix4_pm_reset(DeviceState *dev) 282 { 283 PIIX4PMState *s = PIIX4_PM(dev); 284 PCIDevice *d = PCI_DEVICE(s); 285 uint8_t *pci_conf = d->config; 286 287 pci_conf[0x58] = 0; 288 pci_conf[0x59] = 0; 289 pci_conf[0x5a] = 0; 290 pci_conf[0x5b] = 0; 291 292 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 293 pci_conf[0x80] = 0; 294 295 if (!s->smm_enabled) { 296 /* Mark SMM as already inited (until KVM supports SMM). */ 297 pci_conf[0x5B] = 0x02; 298 } 299 300 acpi_pm1_evt_reset(&s->ar); 301 acpi_pm1_cnt_reset(&s->ar); 302 acpi_pm_tmr_reset(&s->ar); 303 acpi_gpe_reset(&s->ar); 304 acpi_update_sci(&s->ar, s->irq); 305 306 pm_io_space_update(s); 307 if (s->acpi_pci_hotplug.use_acpi_hotplug_bridge || 308 s->acpi_pci_hotplug.use_acpi_root_pci_hotplug) { 309 acpi_pcihp_reset(&s->acpi_pci_hotplug); 310 } 311 } 312 313 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 314 { 315 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 316 317 assert(s != NULL); 318 acpi_pm1_evt_power_down(&s->ar); 319 } 320 321 static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev, 322 DeviceState *dev, Error **errp) 323 { 324 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 325 326 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 327 acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp); 328 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 329 if (!s->acpi_memory_hotplug.is_enabled) { 330 error_setg(errp, 331 "memory hotplug is not enabled: %s.memory-hotplug-support " 332 "is not set", object_get_typename(OBJECT(s))); 333 } 334 } else if ( 335 !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 336 error_setg(errp, "acpi: device pre plug request for not supported" 337 " device type: %s", object_get_typename(OBJECT(dev))); 338 } 339 } 340 341 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, 342 DeviceState *dev, Error **errp) 343 { 344 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 345 346 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 347 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 348 nvdimm_acpi_plug_cb(hotplug_dev, dev); 349 } else { 350 acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug, 351 dev, errp); 352 } 353 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 354 acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); 355 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 356 if (s->cpu_hotplug_legacy) { 357 legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp); 358 } else { 359 acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 360 } 361 } else { 362 g_assert_not_reached(); 363 } 364 } 365 366 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, 367 DeviceState *dev, Error **errp) 368 { 369 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 370 371 if (s->acpi_memory_hotplug.is_enabled && 372 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 373 acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug, 374 dev, errp); 375 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 376 acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug, 377 dev, errp); 378 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 379 !s->cpu_hotplug_legacy) { 380 acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 381 } else { 382 error_setg(errp, "acpi: device unplug request for not supported device" 383 " type: %s", object_get_typename(OBJECT(dev))); 384 } 385 } 386 387 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, 388 DeviceState *dev, Error **errp) 389 { 390 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 391 392 if (s->acpi_memory_hotplug.is_enabled && 393 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 394 acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); 395 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 396 acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, 397 errp); 398 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 399 !s->cpu_hotplug_legacy) { 400 acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); 401 } else { 402 error_setg(errp, "acpi: device unplug for not supported device" 403 " type: %s", object_get_typename(OBJECT(dev))); 404 } 405 } 406 407 static bool piix4_is_hotpluggable_bus(HotplugHandler *hotplug_dev, 408 BusState *bus) 409 { 410 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 411 return acpi_pcihp_is_hotpluggbale_bus(&s->acpi_pci_hotplug, bus); 412 } 413 414 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 415 { 416 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 417 PCIDevice *d = PCI_DEVICE(s); 418 MemoryRegion *io_as = pci_address_space_io(d); 419 uint8_t *pci_conf; 420 421 pci_conf = d->config; 422 pci_conf[0x5f] = 0x10 | 423 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 424 pci_conf[0x63] = 0x60; 425 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 426 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 427 } 428 429 static void piix4_pm_add_properties(PIIX4PMState *s) 430 { 431 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 432 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 433 static const uint32_t gpe0_blk = GPE_BASE; 434 static const uint32_t gpe0_blk_len = GPE_LEN; 435 static const uint16_t sci_int = 9; 436 437 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 438 &acpi_enable_cmd, OBJ_PROP_FLAG_READ); 439 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 440 &acpi_disable_cmd, OBJ_PROP_FLAG_READ); 441 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 442 &gpe0_blk, OBJ_PROP_FLAG_READ); 443 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 444 &gpe0_blk_len, OBJ_PROP_FLAG_READ); 445 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 446 &sci_int, OBJ_PROP_FLAG_READ); 447 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 448 &s->io_base, OBJ_PROP_FLAG_READ); 449 } 450 451 static void piix4_pm_realize(PCIDevice *dev, Error **errp) 452 { 453 PIIX4PMState *s = PIIX4_PM(dev); 454 uint8_t *pci_conf; 455 456 pci_conf = dev->config; 457 pci_conf[0x06] = 0x80; 458 pci_conf[0x07] = 0x02; 459 pci_conf[0x09] = 0x00; 460 pci_conf[0x3d] = 0x01; // interrupt pin 1 461 462 /* APM */ 463 apm_init(dev, &s->apm, apm_ctrl_changed, s); 464 465 if (!s->smm_enabled) { 466 /* Mark SMM as already inited to prevent SMM from running. KVM does not 467 * support SMM mode. */ 468 pci_conf[0x5B] = 0x02; 469 } 470 471 /* XXX: which specification is used ? The i82731AB has different 472 mappings */ 473 pci_conf[0x90] = s->smb_io_base | 1; 474 pci_conf[0x91] = s->smb_io_base >> 8; 475 pci_conf[0xd2] = 0x09; 476 pm_smbus_init(DEVICE(dev), &s->smb, true); 477 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 478 memory_region_add_subregion(pci_address_space_io(dev), 479 s->smb_io_base, &s->smb.io); 480 481 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 482 memory_region_set_enabled(&s->io, false); 483 memory_region_add_subregion(pci_address_space_io(dev), 484 0, &s->io); 485 486 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 487 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 488 acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val, 489 !s->smm_compat && !s->smm_enabled); 490 acpi_gpe_init(&s->ar, GPE_LEN); 491 492 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 493 qemu_register_powerdown_notifier(&s->powerdown_notifier); 494 495 s->machine_ready.notify = piix4_pm_machine_ready; 496 qemu_add_machine_init_done_notifier(&s->machine_ready); 497 498 if (xen_enabled()) { 499 s->acpi_pci_hotplug.use_acpi_hotplug_bridge = false; 500 } 501 502 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), 503 pci_get_bus(dev), s); 504 505 piix4_pm_add_properties(s); 506 } 507 508 static void piix4_pm_init(Object *obj) 509 { 510 PIIX4PMState *s = PIIX4_PM(obj); 511 512 qdev_init_gpio_out(DEVICE(obj), &s->irq, 1); 513 qdev_init_gpio_out_named(DEVICE(obj), &s->smi_irq, "smi-irq", 1); 514 } 515 516 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 517 { 518 PIIX4PMState *s = opaque; 519 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 520 521 trace_piix4_gpe_readb(addr, width, val); 522 return val; 523 } 524 525 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 526 unsigned width) 527 { 528 PIIX4PMState *s = opaque; 529 530 trace_piix4_gpe_writeb(addr, width, val); 531 acpi_gpe_ioport_writeb(&s->ar, addr, val); 532 acpi_update_sci(&s->ar, s->irq); 533 } 534 535 static const MemoryRegionOps piix4_gpe_ops = { 536 .read = gpe_readb, 537 .write = gpe_writeb, 538 .valid.min_access_size = 1, 539 .valid.max_access_size = 4, 540 .impl.min_access_size = 1, 541 .impl.max_access_size = 1, 542 .endianness = DEVICE_LITTLE_ENDIAN, 543 }; 544 545 546 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp) 547 { 548 PIIX4PMState *s = PIIX4_PM(obj); 549 550 return s->cpu_hotplug_legacy; 551 } 552 553 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp) 554 { 555 PIIX4PMState *s = PIIX4_PM(obj); 556 557 assert(!value); 558 if (s->cpu_hotplug_legacy && value == false) { 559 acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state, 560 PIIX4_CPU_HOTPLUG_IO_BASE); 561 } 562 s->cpu_hotplug_legacy = value; 563 } 564 565 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 566 PCIBus *bus, PIIX4PMState *s) 567 { 568 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 569 "acpi-gpe0", GPE_LEN); 570 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 571 572 if (s->acpi_pci_hotplug.use_acpi_hotplug_bridge || 573 s->acpi_pci_hotplug.use_acpi_root_pci_hotplug) { 574 acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, 575 ACPI_PCIHP_ADDR_PIIX4); 576 qbus_set_hotplug_handler(BUS(pci_get_bus(PCI_DEVICE(s))), OBJECT(s)); 577 } 578 579 s->cpu_hotplug_legacy = true; 580 object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", 581 piix4_get_cpu_hotplug_legacy, 582 piix4_set_cpu_hotplug_legacy); 583 legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, 584 PIIX4_CPU_HOTPLUG_IO_BASE); 585 586 if (s->acpi_memory_hotplug.is_enabled) { 587 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug, 588 ACPI_MEMORY_HOTPLUG_BASE); 589 } 590 } 591 592 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) 593 { 594 PIIX4PMState *s = PIIX4_PM(adev); 595 596 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); 597 if (!s->cpu_hotplug_legacy) { 598 acpi_cpu_ospm_status(&s->cpuhp_state, list); 599 } 600 } 601 602 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 603 { 604 PIIX4PMState *s = PIIX4_PM(adev); 605 606 acpi_send_gpe_event(&s->ar, s->irq, ev); 607 } 608 609 static Property piix4_pm_properties[] = { 610 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 611 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 612 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 613 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 614 DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, PIIX4PMState, 615 acpi_pci_hotplug.use_acpi_hotplug_bridge, true), 616 DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCI_ROOTHP, PIIX4PMState, 617 acpi_pci_hotplug.use_acpi_root_pci_hotplug, true), 618 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, 619 acpi_memory_hotplug.is_enabled, true), 620 DEFINE_PROP_BOOL("smm-compat", PIIX4PMState, smm_compat, false), 621 DEFINE_PROP_BOOL("smm-enabled", PIIX4PMState, smm_enabled, false), 622 DEFINE_PROP_BOOL("x-not-migrate-acpi-index", PIIX4PMState, 623 not_migrate_acpi_index, false), 624 DEFINE_PROP_END_OF_LIST(), 625 }; 626 627 static void piix4_pm_class_init(ObjectClass *klass, void *data) 628 { 629 DeviceClass *dc = DEVICE_CLASS(klass); 630 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 631 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 632 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 633 634 k->realize = piix4_pm_realize; 635 k->config_write = pm_write_config; 636 k->vendor_id = PCI_VENDOR_ID_INTEL; 637 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 638 k->revision = 0x03; 639 k->class_id = PCI_CLASS_BRIDGE_OTHER; 640 dc->reset = piix4_pm_reset; 641 dc->desc = "PM"; 642 dc->vmsd = &vmstate_acpi; 643 device_class_set_props(dc, piix4_pm_properties); 644 /* 645 * Reason: part of PIIX4 southbridge, needs to be wired up, 646 * e.g. by mips_malta_init() 647 */ 648 dc->user_creatable = false; 649 dc->hotpluggable = false; 650 hc->pre_plug = piix4_device_pre_plug_cb; 651 hc->plug = piix4_device_plug_cb; 652 hc->unplug_request = piix4_device_unplug_request_cb; 653 hc->unplug = piix4_device_unplug_cb; 654 hc->is_hotpluggable_bus = piix4_is_hotpluggable_bus; 655 adevc->ospm_status = piix4_ospm_status; 656 adevc->send_event = piix4_send_gpe; 657 adevc->madt_cpu = pc_madt_cpu_entry; 658 } 659 660 static const TypeInfo piix4_pm_info = { 661 .name = TYPE_PIIX4_PM, 662 .parent = TYPE_PCI_DEVICE, 663 .instance_init = piix4_pm_init, 664 .instance_size = sizeof(PIIX4PMState), 665 .class_init = piix4_pm_class_init, 666 .interfaces = (InterfaceInfo[]) { 667 { TYPE_HOTPLUG_HANDLER }, 668 { TYPE_ACPI_DEVICE_IF }, 669 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 670 { } 671 } 672 }; 673 674 static void piix4_pm_register_types(void) 675 { 676 type_register_static(&piix4_pm_info); 677 } 678 679 type_init(piix4_pm_register_types) 680