1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 #include "hw/hw.h" 22 #include "hw/i386/pc.h" 23 #include "hw/isa/apm.h" 24 #include "hw/i2c/pm_smbus.h" 25 #include "hw/pci/pci.h" 26 #include "hw/acpi/acpi.h" 27 #include "sysemu/sysemu.h" 28 #include "qemu/range.h" 29 #include "exec/ioport.h" 30 #include "hw/nvram/fw_cfg.h" 31 #include "exec/address-spaces.h" 32 #include "hw/acpi/piix4.h" 33 #include "hw/acpi/pcihp.h" 34 #include "hw/acpi/cpu_hotplug.h" 35 36 //#define DEBUG 37 38 #ifdef DEBUG 39 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 40 #else 41 # define PIIX4_DPRINTF(format, ...) do { } while (0) 42 #endif 43 44 #define GPE_BASE 0xafe0 45 #define GPE_LEN 4 46 47 #define PCI_HOTPLUG_ADDR 0xae00 48 #define PCI_HOTPLUG_SIZE 0x000f 49 #define PCI_UP_BASE 0xae00 50 #define PCI_DOWN_BASE 0xae04 51 #define PCI_EJ_BASE 0xae08 52 #define PCI_RMV_BASE 0xae0c 53 54 #define PIIX4_PROC_BASE 0xaf00 55 56 #define PIIX4_PCI_HOTPLUG_STATUS 2 57 58 struct pci_status { 59 uint32_t up; /* deprecated, maintained for migration compatibility */ 60 uint32_t down; 61 }; 62 63 typedef struct PIIX4PMState { 64 /*< private >*/ 65 PCIDevice parent_obj; 66 /*< public >*/ 67 68 MemoryRegion io; 69 uint32_t io_base; 70 71 MemoryRegion io_gpe; 72 ACPIREGS ar; 73 74 APMState apm; 75 76 PMSMBus smb; 77 uint32_t smb_io_base; 78 79 qemu_irq irq; 80 qemu_irq smi_irq; 81 int kvm_enabled; 82 Notifier machine_ready; 83 Notifier powerdown_notifier; 84 85 /* for legacy pci hotplug (compatible with qemu 1.6 and older) */ 86 MemoryRegion io_pci; 87 struct pci_status pci0_status; 88 uint32_t pci0_hotplug_enable; 89 uint32_t pci0_slot_device_present; 90 91 /* for new pci hotplug (with PCI2PCI bridge support) */ 92 AcpiPciHpState acpi_pci_hotplug; 93 bool use_acpi_pci_hotplug; 94 95 uint8_t disable_s3; 96 uint8_t disable_s4; 97 uint8_t s4_val; 98 99 AcpiCpuHotplug gpe_cpu; 100 Notifier cpu_added_notifier; 101 } PIIX4PMState; 102 103 #define TYPE_PIIX4_PM "PIIX4_PM" 104 105 #define PIIX4_PM(obj) \ 106 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) 107 108 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 109 PCIBus *bus, PIIX4PMState *s); 110 111 #define ACPI_ENABLE 0xf1 112 #define ACPI_DISABLE 0xf0 113 114 static void pm_tmr_timer(ACPIREGS *ar) 115 { 116 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 117 acpi_update_sci(&s->ar, s->irq); 118 } 119 120 static void apm_ctrl_changed(uint32_t val, void *arg) 121 { 122 PIIX4PMState *s = arg; 123 PCIDevice *d = PCI_DEVICE(s); 124 125 /* ACPI specs 3.0, 4.7.2.5 */ 126 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 127 128 if (d->config[0x5b] & (1 << 1)) { 129 if (s->smi_irq) { 130 qemu_irq_raise(s->smi_irq); 131 } 132 } 133 } 134 135 static void pm_io_space_update(PIIX4PMState *s) 136 { 137 PCIDevice *d = PCI_DEVICE(s); 138 139 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 140 s->io_base &= 0xffc0; 141 142 memory_region_transaction_begin(); 143 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 144 memory_region_set_address(&s->io, s->io_base); 145 memory_region_transaction_commit(); 146 } 147 148 static void smbus_io_space_update(PIIX4PMState *s) 149 { 150 PCIDevice *d = PCI_DEVICE(s); 151 152 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 153 s->smb_io_base &= 0xffc0; 154 155 memory_region_transaction_begin(); 156 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 157 memory_region_set_address(&s->smb.io, s->smb_io_base); 158 memory_region_transaction_commit(); 159 } 160 161 static void pm_write_config(PCIDevice *d, 162 uint32_t address, uint32_t val, int len) 163 { 164 pci_default_write_config(d, address, val, len); 165 if (range_covers_byte(address, len, 0x80) || 166 ranges_overlap(address, len, 0x40, 4)) { 167 pm_io_space_update((PIIX4PMState *)d); 168 } 169 if (range_covers_byte(address, len, 0xd2) || 170 ranges_overlap(address, len, 0x90, 4)) { 171 smbus_io_space_update((PIIX4PMState *)d); 172 } 173 } 174 175 static void vmstate_pci_status_pre_save(void *opaque) 176 { 177 struct pci_status *pci0_status = opaque; 178 PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status); 179 180 /* We no longer track up, so build a safe value for migrating 181 * to a version that still does... of course these might get lost 182 * by an old buggy implementation, but we try. */ 183 pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable; 184 } 185 186 static int vmstate_acpi_post_load(void *opaque, int version_id) 187 { 188 PIIX4PMState *s = opaque; 189 190 pm_io_space_update(s); 191 return 0; 192 } 193 194 #define VMSTATE_GPE_ARRAY(_field, _state) \ 195 { \ 196 .name = (stringify(_field)), \ 197 .version_id = 0, \ 198 .info = &vmstate_info_uint16, \ 199 .size = sizeof(uint16_t), \ 200 .flags = VMS_SINGLE | VMS_POINTER, \ 201 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 202 } 203 204 static const VMStateDescription vmstate_gpe = { 205 .name = "gpe", 206 .version_id = 1, 207 .minimum_version_id = 1, 208 .minimum_version_id_old = 1, 209 .fields = (VMStateField []) { 210 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 211 VMSTATE_GPE_ARRAY(en, ACPIGPE), 212 VMSTATE_END_OF_LIST() 213 } 214 }; 215 216 static const VMStateDescription vmstate_pci_status = { 217 .name = "pci_status", 218 .version_id = 1, 219 .minimum_version_id = 1, 220 .minimum_version_id_old = 1, 221 .pre_save = vmstate_pci_status_pre_save, 222 .fields = (VMStateField []) { 223 VMSTATE_UINT32(up, struct pci_status), 224 VMSTATE_UINT32(down, struct pci_status), 225 VMSTATE_END_OF_LIST() 226 } 227 }; 228 229 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) 230 { 231 PIIX4PMState *s = opaque; 232 int ret, i; 233 uint16_t temp; 234 235 ret = pci_device_load(PCI_DEVICE(s), f); 236 if (ret < 0) { 237 return ret; 238 } 239 qemu_get_be16s(f, &s->ar.pm1.evt.sts); 240 qemu_get_be16s(f, &s->ar.pm1.evt.en); 241 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); 242 243 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); 244 if (ret) { 245 return ret; 246 } 247 248 timer_get(f, s->ar.tmr.timer); 249 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); 250 251 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); 252 for (i = 0; i < 3; i++) { 253 qemu_get_be16s(f, &temp); 254 } 255 256 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); 257 for (i = 0; i < 3; i++) { 258 qemu_get_be16s(f, &temp); 259 } 260 261 ret = vmstate_load_state(f, &vmstate_pci_status, &s->pci0_status, 1); 262 return ret; 263 } 264 265 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) 266 { 267 PIIX4PMState *s = opaque; 268 return s->use_acpi_pci_hotplug; 269 } 270 271 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id) 272 { 273 PIIX4PMState *s = opaque; 274 return !s->use_acpi_pci_hotplug; 275 } 276 277 /* qemu-kvm 1.2 uses version 3 but advertised as 2 278 * To support incoming qemu-kvm 1.2 migration, change version_id 279 * and minimum_version_id to 2 below (which breaks migration from 280 * qemu 1.2). 281 * 282 */ 283 static const VMStateDescription vmstate_acpi = { 284 .name = "piix4_pm", 285 .version_id = 3, 286 .minimum_version_id = 3, 287 .minimum_version_id_old = 1, 288 .load_state_old = acpi_load_old, 289 .post_load = vmstate_acpi_post_load, 290 .fields = (VMStateField []) { 291 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 292 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 293 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 294 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 295 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 296 VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), 297 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 298 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 299 VMSTATE_STRUCT_TEST(pci0_status, PIIX4PMState, 300 vmstate_test_no_use_acpi_pci_hotplug, 301 2, vmstate_pci_status, 302 struct pci_status), 303 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 304 vmstate_test_use_acpi_pci_hotplug), 305 VMSTATE_END_OF_LIST() 306 } 307 }; 308 309 static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) 310 { 311 BusChild *kid, *next; 312 BusState *bus = qdev_get_parent_bus(DEVICE(s)); 313 int slot = ffs(slots) - 1; 314 bool slot_free = true; 315 316 /* Mark request as complete */ 317 s->pci0_status.down &= ~(1U << slot); 318 319 QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { 320 DeviceState *qdev = kid->child; 321 PCIDevice *dev = PCI_DEVICE(qdev); 322 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 323 if (PCI_SLOT(dev->devfn) == slot) { 324 if (pc->no_hotplug) { 325 slot_free = false; 326 } else { 327 object_unparent(OBJECT(qdev)); 328 } 329 } 330 } 331 if (slot_free) { 332 s->pci0_slot_device_present &= ~(1U << slot); 333 } 334 } 335 336 static void piix4_update_hotplug(PIIX4PMState *s) 337 { 338 BusState *bus = qdev_get_parent_bus(DEVICE(s)); 339 BusChild *kid, *next; 340 341 /* Execute any pending removes during reset */ 342 while (s->pci0_status.down) { 343 acpi_piix_eject_slot(s, s->pci0_status.down); 344 } 345 346 s->pci0_hotplug_enable = ~0; 347 s->pci0_slot_device_present = 0; 348 349 QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { 350 DeviceState *qdev = kid->child; 351 PCIDevice *pdev = PCI_DEVICE(qdev); 352 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); 353 int slot = PCI_SLOT(pdev->devfn); 354 355 if (pc->no_hotplug) { 356 s->pci0_hotplug_enable &= ~(1U << slot); 357 } 358 359 s->pci0_slot_device_present |= (1U << slot); 360 } 361 } 362 363 static void piix4_reset(void *opaque) 364 { 365 PIIX4PMState *s = opaque; 366 PCIDevice *d = PCI_DEVICE(s); 367 uint8_t *pci_conf = d->config; 368 369 pci_conf[0x58] = 0; 370 pci_conf[0x59] = 0; 371 pci_conf[0x5a] = 0; 372 pci_conf[0x5b] = 0; 373 374 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 375 pci_conf[0x80] = 0; 376 377 if (s->kvm_enabled) { 378 /* Mark SMM as already inited (until KVM supports SMM). */ 379 pci_conf[0x5B] = 0x02; 380 } 381 pm_io_space_update(s); 382 if (s->use_acpi_pci_hotplug) { 383 acpi_pcihp_reset(&s->acpi_pci_hotplug); 384 } else { 385 piix4_update_hotplug(s); 386 } 387 } 388 389 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 390 { 391 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 392 393 assert(s != NULL); 394 acpi_pm1_evt_power_down(&s->ar); 395 } 396 397 static int piix4_acpi_pci_hotplug(DeviceState *qdev, PCIDevice *dev, 398 PCIHotplugState state) 399 { 400 PIIX4PMState *s = PIIX4_PM(qdev); 401 int ret = acpi_pcihp_device_hotplug(&s->acpi_pci_hotplug, dev, state); 402 if (ret < 0) { 403 return ret; 404 } 405 s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; 406 407 acpi_update_sci(&s->ar, s->irq); 408 return 0; 409 } 410 411 static void piix4_update_bus_hotplug(PCIBus *bus, void *opaque) 412 { 413 PIIX4PMState *s = opaque; 414 pci_bus_hotplug(bus, piix4_acpi_pci_hotplug, DEVICE(s)); 415 } 416 417 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 418 { 419 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 420 PCIDevice *d = PCI_DEVICE(s); 421 MemoryRegion *io_as = pci_address_space_io(d); 422 uint8_t *pci_conf; 423 424 pci_conf = d->config; 425 pci_conf[0x5f] = 0x10 | 426 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 427 pci_conf[0x63] = 0x60; 428 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 429 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 430 431 if (s->use_acpi_pci_hotplug) { 432 pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s); 433 } 434 } 435 436 static void piix4_pm_add_propeties(PIIX4PMState *s) 437 { 438 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 439 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 440 static const uint32_t gpe0_blk = GPE_BASE; 441 static const uint32_t gpe0_blk_len = GPE_LEN; 442 static const uint16_t sci_int = 9; 443 444 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 445 &acpi_enable_cmd, NULL); 446 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 447 &acpi_disable_cmd, NULL); 448 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 449 &gpe0_blk, NULL); 450 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 451 &gpe0_blk_len, NULL); 452 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 453 &sci_int, NULL); 454 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 455 &s->io_base, NULL); 456 } 457 458 static int piix4_pm_initfn(PCIDevice *dev) 459 { 460 PIIX4PMState *s = PIIX4_PM(dev); 461 uint8_t *pci_conf; 462 463 pci_conf = dev->config; 464 pci_conf[0x06] = 0x80; 465 pci_conf[0x07] = 0x02; 466 pci_conf[0x09] = 0x00; 467 pci_conf[0x3d] = 0x01; // interrupt pin 1 468 469 /* APM */ 470 apm_init(dev, &s->apm, apm_ctrl_changed, s); 471 472 if (s->kvm_enabled) { 473 /* Mark SMM as already inited to prevent SMM from running. KVM does not 474 * support SMM mode. */ 475 pci_conf[0x5B] = 0x02; 476 } 477 478 /* XXX: which specification is used ? The i82731AB has different 479 mappings */ 480 pci_conf[0x90] = s->smb_io_base | 1; 481 pci_conf[0x91] = s->smb_io_base >> 8; 482 pci_conf[0xd2] = 0x09; 483 pm_smbus_init(DEVICE(dev), &s->smb); 484 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 485 memory_region_add_subregion(pci_address_space_io(dev), 486 s->smb_io_base, &s->smb.io); 487 488 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 489 memory_region_set_enabled(&s->io, false); 490 memory_region_add_subregion(pci_address_space_io(dev), 491 0, &s->io); 492 493 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 494 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 495 acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val); 496 acpi_gpe_init(&s->ar, GPE_LEN); 497 498 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 499 qemu_register_powerdown_notifier(&s->powerdown_notifier); 500 501 s->machine_ready.notify = piix4_pm_machine_ready; 502 qemu_add_machine_init_done_notifier(&s->machine_ready); 503 qemu_register_reset(piix4_reset, s); 504 505 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s); 506 507 piix4_pm_add_propeties(s); 508 return 0; 509 } 510 511 Object *piix4_pm_find(void) 512 { 513 bool ambig; 514 Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig); 515 516 if (ambig || !o) { 517 return NULL; 518 } 519 return o; 520 } 521 522 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 523 qemu_irq sci_irq, qemu_irq smi_irq, 524 int kvm_enabled, FWCfgState *fw_cfg) 525 { 526 DeviceState *dev; 527 PIIX4PMState *s; 528 529 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); 530 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 531 532 s = PIIX4_PM(dev); 533 s->irq = sci_irq; 534 s->smi_irq = smi_irq; 535 s->kvm_enabled = kvm_enabled; 536 537 qdev_init_nofail(dev); 538 539 if (fw_cfg) { 540 uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; 541 suspend[3] = 1 | ((!s->disable_s3) << 7); 542 suspend[4] = s->s4_val | ((!s->disable_s4) << 7); 543 544 fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); 545 } 546 547 return s->smb.smbus; 548 } 549 550 static Property piix4_pm_properties[] = { 551 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 552 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 553 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 554 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 555 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, 556 use_acpi_pci_hotplug, true), 557 DEFINE_PROP_END_OF_LIST(), 558 }; 559 560 static void piix4_pm_class_init(ObjectClass *klass, void *data) 561 { 562 DeviceClass *dc = DEVICE_CLASS(klass); 563 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 564 565 k->no_hotplug = 1; 566 k->init = piix4_pm_initfn; 567 k->config_write = pm_write_config; 568 k->vendor_id = PCI_VENDOR_ID_INTEL; 569 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 570 k->revision = 0x03; 571 k->class_id = PCI_CLASS_BRIDGE_OTHER; 572 dc->desc = "PM"; 573 dc->vmsd = &vmstate_acpi; 574 dc->props = piix4_pm_properties; 575 /* 576 * Reason: part of PIIX4 southbridge, needs to be wired up, 577 * e.g. by mips_malta_init() 578 */ 579 dc->cannot_instantiate_with_device_add_yet = true; 580 } 581 582 static const TypeInfo piix4_pm_info = { 583 .name = TYPE_PIIX4_PM, 584 .parent = TYPE_PCI_DEVICE, 585 .instance_size = sizeof(PIIX4PMState), 586 .class_init = piix4_pm_class_init, 587 }; 588 589 static void piix4_pm_register_types(void) 590 { 591 type_register_static(&piix4_pm_info); 592 } 593 594 type_init(piix4_pm_register_types) 595 596 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 597 { 598 PIIX4PMState *s = opaque; 599 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 600 601 PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); 602 return val; 603 } 604 605 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 606 unsigned width) 607 { 608 PIIX4PMState *s = opaque; 609 610 acpi_gpe_ioport_writeb(&s->ar, addr, val); 611 acpi_update_sci(&s->ar, s->irq); 612 613 PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); 614 } 615 616 static const MemoryRegionOps piix4_gpe_ops = { 617 .read = gpe_readb, 618 .write = gpe_writeb, 619 .valid.min_access_size = 1, 620 .valid.max_access_size = 4, 621 .impl.min_access_size = 1, 622 .impl.max_access_size = 1, 623 .endianness = DEVICE_LITTLE_ENDIAN, 624 }; 625 626 static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) 627 { 628 PIIX4PMState *s = opaque; 629 uint32_t val = 0; 630 631 switch (addr) { 632 case PCI_UP_BASE - PCI_HOTPLUG_ADDR: 633 /* Manufacture an "up" value to cause a device check on any hotplug 634 * slot with a device. Extra device checks are harmless. */ 635 val = s->pci0_slot_device_present & s->pci0_hotplug_enable; 636 PIIX4_DPRINTF("pci_up_read %" PRIu32 "\n", val); 637 break; 638 case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR: 639 val = s->pci0_status.down; 640 PIIX4_DPRINTF("pci_down_read %" PRIu32 "\n", val); 641 break; 642 case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: 643 /* No feature defined yet */ 644 PIIX4_DPRINTF("pci_features_read %" PRIu32 "\n", val); 645 break; 646 case PCI_RMV_BASE - PCI_HOTPLUG_ADDR: 647 val = s->pci0_hotplug_enable; 648 break; 649 default: 650 break; 651 } 652 653 return val; 654 } 655 656 static void pci_write(void *opaque, hwaddr addr, uint64_t data, 657 unsigned int size) 658 { 659 switch (addr) { 660 case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: 661 acpi_piix_eject_slot(opaque, (uint32_t)data); 662 PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n", 663 addr, data); 664 break; 665 default: 666 break; 667 } 668 } 669 670 static const MemoryRegionOps piix4_pci_ops = { 671 .read = pci_read, 672 .write = pci_write, 673 .endianness = DEVICE_LITTLE_ENDIAN, 674 .valid = { 675 .min_access_size = 4, 676 .max_access_size = 4, 677 }, 678 }; 679 680 static void piix4_cpu_added_req(Notifier *n, void *opaque) 681 { 682 PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier); 683 684 assert(s != NULL); 685 AcpiCpuHotplug_add(&s->ar.gpe, &s->gpe_cpu, CPU(opaque)); 686 acpi_update_sci(&s->ar, s->irq); 687 } 688 689 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, 690 PCIHotplugState state); 691 692 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 693 PCIBus *bus, PIIX4PMState *s) 694 { 695 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 696 "acpi-gpe0", GPE_LEN); 697 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 698 699 if (s->use_acpi_pci_hotplug) { 700 acpi_pcihp_init(&s->acpi_pci_hotplug, bus, parent); 701 } else { 702 memory_region_init_io(&s->io_pci, OBJECT(s), &piix4_pci_ops, s, 703 "acpi-pci-hotplug", PCI_HOTPLUG_SIZE); 704 memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR, 705 &s->io_pci); 706 pci_bus_hotplug(bus, piix4_device_hotplug, DEVICE(s)); 707 } 708 709 AcpiCpuHotplug_init(parent, OBJECT(s), &s->gpe_cpu, PIIX4_PROC_BASE); 710 s->cpu_added_notifier.notify = piix4_cpu_added_req; 711 qemu_register_cpu_added_notifier(&s->cpu_added_notifier); 712 } 713 714 static void enable_device(PIIX4PMState *s, int slot) 715 { 716 s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; 717 s->pci0_slot_device_present |= (1U << slot); 718 } 719 720 static void disable_device(PIIX4PMState *s, int slot) 721 { 722 s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; 723 s->pci0_status.down |= (1U << slot); 724 } 725 726 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, 727 PCIHotplugState state) 728 { 729 int slot = PCI_SLOT(dev->devfn); 730 PIIX4PMState *s = PIIX4_PM(qdev); 731 732 /* Don't send event when device is enabled during qemu machine creation: 733 * it is present on boot, no hotplug event is necessary. We do send an 734 * event when the device is disabled later. */ 735 if (state == PCI_COLDPLUG_ENABLED) { 736 s->pci0_slot_device_present |= (1U << slot); 737 return 0; 738 } 739 740 if (state == PCI_HOTPLUG_ENABLED) { 741 enable_device(s, slot); 742 } else { 743 disable_device(s, slot); 744 } 745 746 acpi_update_sci(&s->ar, s->irq); 747 748 return 0; 749 } 750