1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 #include "hw/hw.h" 22 #include "hw/i386/pc.h" 23 #include "hw/isa/apm.h" 24 #include "hw/i2c/pm_smbus.h" 25 #include "hw/pci/pci.h" 26 #include "hw/acpi/acpi.h" 27 #include "sysemu/sysemu.h" 28 #include "qemu/range.h" 29 #include "exec/ioport.h" 30 #include "hw/nvram/fw_cfg.h" 31 #include "exec/address-spaces.h" 32 33 //#define DEBUG 34 35 #ifdef DEBUG 36 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 37 #else 38 # define PIIX4_DPRINTF(format, ...) do { } while (0) 39 #endif 40 41 #define GPE_BASE 0xafe0 42 #define GPE_LEN 4 43 44 #define PCI_HOTPLUG_ADDR 0xae00 45 #define PCI_HOTPLUG_SIZE 0x000f 46 #define PCI_UP_BASE 0xae00 47 #define PCI_DOWN_BASE 0xae04 48 #define PCI_EJ_BASE 0xae08 49 #define PCI_RMV_BASE 0xae0c 50 51 #define PIIX4_PROC_BASE 0xaf00 52 #define PIIX4_PROC_LEN 32 53 54 #define PIIX4_PCI_HOTPLUG_STATUS 2 55 #define PIIX4_CPU_HOTPLUG_STATUS 4 56 57 struct pci_status { 58 uint32_t up; /* deprecated, maintained for migration compatibility */ 59 uint32_t down; 60 }; 61 62 typedef struct CPUStatus { 63 uint8_t sts[PIIX4_PROC_LEN]; 64 } CPUStatus; 65 66 typedef struct PIIX4PMState { 67 PCIDevice dev; 68 69 MemoryRegion io; 70 MemoryRegion io_gpe; 71 MemoryRegion io_pci; 72 MemoryRegion io_cpu; 73 ACPIREGS ar; 74 75 APMState apm; 76 77 PMSMBus smb; 78 uint32_t smb_io_base; 79 80 qemu_irq irq; 81 qemu_irq smi_irq; 82 int kvm_enabled; 83 Notifier machine_ready; 84 Notifier powerdown_notifier; 85 86 /* for pci hotplug */ 87 struct pci_status pci0_status; 88 uint32_t pci0_hotplug_enable; 89 uint32_t pci0_slot_device_present; 90 91 uint8_t disable_s3; 92 uint8_t disable_s4; 93 uint8_t s4_val; 94 95 CPUStatus gpe_cpu; 96 Notifier cpu_added_notifier; 97 } PIIX4PMState; 98 99 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 100 PCIBus *bus, PIIX4PMState *s); 101 102 #define ACPI_ENABLE 0xf1 103 #define ACPI_DISABLE 0xf0 104 105 static void pm_update_sci(PIIX4PMState *s) 106 { 107 int sci_level, pmsts; 108 109 pmsts = acpi_pm1_evt_get_sts(&s->ar); 110 sci_level = (((pmsts & s->ar.pm1.evt.en) & 111 (ACPI_BITMASK_RT_CLOCK_ENABLE | 112 ACPI_BITMASK_POWER_BUTTON_ENABLE | 113 ACPI_BITMASK_GLOBAL_LOCK_ENABLE | 114 ACPI_BITMASK_TIMER_ENABLE)) != 0) || 115 (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) & 116 (PIIX4_PCI_HOTPLUG_STATUS | PIIX4_CPU_HOTPLUG_STATUS)) != 0); 117 118 qemu_set_irq(s->irq, sci_level); 119 /* schedule a timer interruption if needed */ 120 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && 121 !(pmsts & ACPI_BITMASK_TIMER_STATUS)); 122 } 123 124 static void pm_tmr_timer(ACPIREGS *ar) 125 { 126 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 127 pm_update_sci(s); 128 } 129 130 static void apm_ctrl_changed(uint32_t val, void *arg) 131 { 132 PIIX4PMState *s = arg; 133 134 /* ACPI specs 3.0, 4.7.2.5 */ 135 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 136 137 if (s->dev.config[0x5b] & (1 << 1)) { 138 if (s->smi_irq) { 139 qemu_irq_raise(s->smi_irq); 140 } 141 } 142 } 143 144 static void pm_io_space_update(PIIX4PMState *s) 145 { 146 uint32_t pm_io_base; 147 148 pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40)); 149 pm_io_base &= 0xffc0; 150 151 memory_region_transaction_begin(); 152 memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); 153 memory_region_set_address(&s->io, pm_io_base); 154 memory_region_transaction_commit(); 155 } 156 157 static void smbus_io_space_update(PIIX4PMState *s) 158 { 159 s->smb_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x90)); 160 s->smb_io_base &= 0xffc0; 161 162 memory_region_transaction_begin(); 163 memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & 1); 164 memory_region_set_address(&s->smb.io, s->smb_io_base); 165 memory_region_transaction_commit(); 166 } 167 168 static void pm_write_config(PCIDevice *d, 169 uint32_t address, uint32_t val, int len) 170 { 171 pci_default_write_config(d, address, val, len); 172 if (range_covers_byte(address, len, 0x80) || 173 ranges_overlap(address, len, 0x40, 4)) { 174 pm_io_space_update((PIIX4PMState *)d); 175 } 176 if (range_covers_byte(address, len, 0xd2) || 177 ranges_overlap(address, len, 0x90, 4)) { 178 smbus_io_space_update((PIIX4PMState *)d); 179 } 180 } 181 182 static void vmstate_pci_status_pre_save(void *opaque) 183 { 184 struct pci_status *pci0_status = opaque; 185 PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status); 186 187 /* We no longer track up, so build a safe value for migrating 188 * to a version that still does... of course these might get lost 189 * by an old buggy implementation, but we try. */ 190 pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable; 191 } 192 193 static int vmstate_acpi_post_load(void *opaque, int version_id) 194 { 195 PIIX4PMState *s = opaque; 196 197 pm_io_space_update(s); 198 return 0; 199 } 200 201 #define VMSTATE_GPE_ARRAY(_field, _state) \ 202 { \ 203 .name = (stringify(_field)), \ 204 .version_id = 0, \ 205 .info = &vmstate_info_uint16, \ 206 .size = sizeof(uint16_t), \ 207 .flags = VMS_SINGLE | VMS_POINTER, \ 208 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 209 } 210 211 static const VMStateDescription vmstate_gpe = { 212 .name = "gpe", 213 .version_id = 1, 214 .minimum_version_id = 1, 215 .minimum_version_id_old = 1, 216 .fields = (VMStateField []) { 217 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 218 VMSTATE_GPE_ARRAY(en, ACPIGPE), 219 VMSTATE_END_OF_LIST() 220 } 221 }; 222 223 static const VMStateDescription vmstate_pci_status = { 224 .name = "pci_status", 225 .version_id = 1, 226 .minimum_version_id = 1, 227 .minimum_version_id_old = 1, 228 .pre_save = vmstate_pci_status_pre_save, 229 .fields = (VMStateField []) { 230 VMSTATE_UINT32(up, struct pci_status), 231 VMSTATE_UINT32(down, struct pci_status), 232 VMSTATE_END_OF_LIST() 233 } 234 }; 235 236 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) 237 { 238 PIIX4PMState *s = opaque; 239 int ret, i; 240 uint16_t temp; 241 242 ret = pci_device_load(&s->dev, f); 243 if (ret < 0) { 244 return ret; 245 } 246 qemu_get_be16s(f, &s->ar.pm1.evt.sts); 247 qemu_get_be16s(f, &s->ar.pm1.evt.en); 248 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); 249 250 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); 251 if (ret) { 252 return ret; 253 } 254 255 qemu_get_timer(f, s->ar.tmr.timer); 256 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); 257 258 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); 259 for (i = 0; i < 3; i++) { 260 qemu_get_be16s(f, &temp); 261 } 262 263 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); 264 for (i = 0; i < 3; i++) { 265 qemu_get_be16s(f, &temp); 266 } 267 268 ret = vmstate_load_state(f, &vmstate_pci_status, &s->pci0_status, 1); 269 return ret; 270 } 271 272 /* qemu-kvm 1.2 uses version 3 but advertised as 2 273 * To support incoming qemu-kvm 1.2 migration, change version_id 274 * and minimum_version_id to 2 below (which breaks migration from 275 * qemu 1.2). 276 * 277 */ 278 static const VMStateDescription vmstate_acpi = { 279 .name = "piix4_pm", 280 .version_id = 3, 281 .minimum_version_id = 3, 282 .minimum_version_id_old = 1, 283 .load_state_old = acpi_load_old, 284 .post_load = vmstate_acpi_post_load, 285 .fields = (VMStateField []) { 286 VMSTATE_PCI_DEVICE(dev, PIIX4PMState), 287 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 288 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 289 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 290 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 291 VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), 292 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 293 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 294 VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status, 295 struct pci_status), 296 VMSTATE_END_OF_LIST() 297 } 298 }; 299 300 static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) 301 { 302 BusChild *kid, *next; 303 BusState *bus = qdev_get_parent_bus(&s->dev.qdev); 304 int slot = ffs(slots) - 1; 305 bool slot_free = true; 306 307 /* Mark request as complete */ 308 s->pci0_status.down &= ~(1U << slot); 309 310 QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { 311 DeviceState *qdev = kid->child; 312 PCIDevice *dev = PCI_DEVICE(qdev); 313 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 314 if (PCI_SLOT(dev->devfn) == slot) { 315 if (pc->no_hotplug) { 316 slot_free = false; 317 } else { 318 qdev_free(qdev); 319 } 320 } 321 } 322 if (slot_free) { 323 s->pci0_slot_device_present &= ~(1U << slot); 324 } 325 } 326 327 static void piix4_update_hotplug(PIIX4PMState *s) 328 { 329 PCIDevice *dev = &s->dev; 330 BusState *bus = qdev_get_parent_bus(&dev->qdev); 331 BusChild *kid, *next; 332 333 /* Execute any pending removes during reset */ 334 while (s->pci0_status.down) { 335 acpi_piix_eject_slot(s, s->pci0_status.down); 336 } 337 338 s->pci0_hotplug_enable = ~0; 339 s->pci0_slot_device_present = 0; 340 341 QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { 342 DeviceState *qdev = kid->child; 343 PCIDevice *pdev = PCI_DEVICE(qdev); 344 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); 345 int slot = PCI_SLOT(pdev->devfn); 346 347 if (pc->no_hotplug) { 348 s->pci0_hotplug_enable &= ~(1U << slot); 349 } 350 351 s->pci0_slot_device_present |= (1U << slot); 352 } 353 } 354 355 static void piix4_reset(void *opaque) 356 { 357 PIIX4PMState *s = opaque; 358 uint8_t *pci_conf = s->dev.config; 359 360 pci_conf[0x58] = 0; 361 pci_conf[0x59] = 0; 362 pci_conf[0x5a] = 0; 363 pci_conf[0x5b] = 0; 364 365 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 366 pci_conf[0x80] = 0; 367 368 if (s->kvm_enabled) { 369 /* Mark SMM as already inited (until KVM supports SMM). */ 370 pci_conf[0x5B] = 0x02; 371 } 372 piix4_update_hotplug(s); 373 } 374 375 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 376 { 377 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 378 379 assert(s != NULL); 380 acpi_pm1_evt_power_down(&s->ar); 381 } 382 383 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 384 { 385 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 386 MemoryRegion *io_as = pci_address_space_io(&s->dev); 387 uint8_t *pci_conf; 388 389 pci_conf = s->dev.config; 390 pci_conf[0x5f] = 0x10 | 391 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 392 pci_conf[0x63] = 0x60; 393 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 394 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 395 } 396 397 static int piix4_pm_initfn(PCIDevice *dev) 398 { 399 PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); 400 uint8_t *pci_conf; 401 402 pci_conf = s->dev.config; 403 pci_conf[0x06] = 0x80; 404 pci_conf[0x07] = 0x02; 405 pci_conf[0x09] = 0x00; 406 pci_conf[0x3d] = 0x01; // interrupt pin 1 407 408 /* APM */ 409 apm_init(dev, &s->apm, apm_ctrl_changed, s); 410 411 if (s->kvm_enabled) { 412 /* Mark SMM as already inited to prevent SMM from running. KVM does not 413 * support SMM mode. */ 414 pci_conf[0x5B] = 0x02; 415 } 416 417 /* XXX: which specification is used ? The i82731AB has different 418 mappings */ 419 pci_conf[0x90] = s->smb_io_base | 1; 420 pci_conf[0x91] = s->smb_io_base >> 8; 421 pci_conf[0xd2] = 0x09; 422 pm_smbus_init(&s->dev.qdev, &s->smb); 423 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 424 memory_region_add_subregion(pci_address_space_io(dev), 425 s->smb_io_base, &s->smb.io); 426 427 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 428 memory_region_set_enabled(&s->io, false); 429 memory_region_add_subregion(pci_address_space_io(dev), 430 0, &s->io); 431 432 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 433 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 434 acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val); 435 acpi_gpe_init(&s->ar, GPE_LEN); 436 437 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 438 qemu_register_powerdown_notifier(&s->powerdown_notifier); 439 440 s->machine_ready.notify = piix4_pm_machine_ready; 441 qemu_add_machine_init_done_notifier(&s->machine_ready); 442 qemu_register_reset(piix4_reset, s); 443 444 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s); 445 446 return 0; 447 } 448 449 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 450 qemu_irq sci_irq, qemu_irq smi_irq, 451 int kvm_enabled, FWCfgState *fw_cfg) 452 { 453 PCIDevice *dev; 454 PIIX4PMState *s; 455 456 dev = pci_create(bus, devfn, "PIIX4_PM"); 457 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); 458 459 s = DO_UPCAST(PIIX4PMState, dev, dev); 460 s->irq = sci_irq; 461 s->smi_irq = smi_irq; 462 s->kvm_enabled = kvm_enabled; 463 464 qdev_init_nofail(&dev->qdev); 465 466 if (fw_cfg) { 467 uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; 468 suspend[3] = 1 | ((!s->disable_s3) << 7); 469 suspend[4] = s->s4_val | ((!s->disable_s4) << 7); 470 471 fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); 472 } 473 474 return s->smb.smbus; 475 } 476 477 static Property piix4_pm_properties[] = { 478 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 479 DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0), 480 DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0), 481 DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2), 482 DEFINE_PROP_END_OF_LIST(), 483 }; 484 485 static void piix4_pm_class_init(ObjectClass *klass, void *data) 486 { 487 DeviceClass *dc = DEVICE_CLASS(klass); 488 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 489 490 k->no_hotplug = 1; 491 k->init = piix4_pm_initfn; 492 k->config_write = pm_write_config; 493 k->vendor_id = PCI_VENDOR_ID_INTEL; 494 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 495 k->revision = 0x03; 496 k->class_id = PCI_CLASS_BRIDGE_OTHER; 497 dc->desc = "PM"; 498 dc->no_user = 1; 499 dc->vmsd = &vmstate_acpi; 500 dc->props = piix4_pm_properties; 501 } 502 503 static const TypeInfo piix4_pm_info = { 504 .name = "PIIX4_PM", 505 .parent = TYPE_PCI_DEVICE, 506 .instance_size = sizeof(PIIX4PMState), 507 .class_init = piix4_pm_class_init, 508 }; 509 510 static void piix4_pm_register_types(void) 511 { 512 type_register_static(&piix4_pm_info); 513 } 514 515 type_init(piix4_pm_register_types) 516 517 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 518 { 519 PIIX4PMState *s = opaque; 520 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 521 522 PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); 523 return val; 524 } 525 526 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 527 unsigned width) 528 { 529 PIIX4PMState *s = opaque; 530 531 acpi_gpe_ioport_writeb(&s->ar, addr, val); 532 pm_update_sci(s); 533 534 PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); 535 } 536 537 static const MemoryRegionOps piix4_gpe_ops = { 538 .read = gpe_readb, 539 .write = gpe_writeb, 540 .valid.min_access_size = 1, 541 .valid.max_access_size = 4, 542 .impl.min_access_size = 1, 543 .impl.max_access_size = 1, 544 .endianness = DEVICE_LITTLE_ENDIAN, 545 }; 546 547 static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) 548 { 549 PIIX4PMState *s = opaque; 550 uint32_t val = 0; 551 552 switch (addr) { 553 case PCI_UP_BASE - PCI_HOTPLUG_ADDR: 554 /* Manufacture an "up" value to cause a device check on any hotplug 555 * slot with a device. Extra device checks are harmless. */ 556 val = s->pci0_slot_device_present & s->pci0_hotplug_enable; 557 PIIX4_DPRINTF("pci_up_read %" PRIu32 "\n", val); 558 break; 559 case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR: 560 val = s->pci0_status.down; 561 PIIX4_DPRINTF("pci_down_read %" PRIu32 "\n", val); 562 break; 563 case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: 564 /* No feature defined yet */ 565 PIIX4_DPRINTF("pci_features_read %" PRIu32 "\n", val); 566 break; 567 case PCI_RMV_BASE - PCI_HOTPLUG_ADDR: 568 val = s->pci0_hotplug_enable; 569 break; 570 default: 571 break; 572 } 573 574 return val; 575 } 576 577 static void pci_write(void *opaque, hwaddr addr, uint64_t data, 578 unsigned int size) 579 { 580 switch (addr) { 581 case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: 582 acpi_piix_eject_slot(opaque, (uint32_t)data); 583 PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n", 584 addr, data); 585 break; 586 default: 587 break; 588 } 589 } 590 591 static const MemoryRegionOps piix4_pci_ops = { 592 .read = pci_read, 593 .write = pci_write, 594 .endianness = DEVICE_LITTLE_ENDIAN, 595 .valid = { 596 .min_access_size = 4, 597 .max_access_size = 4, 598 }, 599 }; 600 601 static uint64_t cpu_status_read(void *opaque, hwaddr addr, unsigned int size) 602 { 603 PIIX4PMState *s = opaque; 604 CPUStatus *cpus = &s->gpe_cpu; 605 uint64_t val = cpus->sts[addr]; 606 607 return val; 608 } 609 610 static void cpu_status_write(void *opaque, hwaddr addr, uint64_t data, 611 unsigned int size) 612 { 613 /* TODO: implement VCPU removal on guest signal that CPU can be removed */ 614 } 615 616 static const MemoryRegionOps cpu_hotplug_ops = { 617 .read = cpu_status_read, 618 .write = cpu_status_write, 619 .endianness = DEVICE_LITTLE_ENDIAN, 620 .valid = { 621 .min_access_size = 1, 622 .max_access_size = 1, 623 }, 624 }; 625 626 typedef enum { 627 PLUG, 628 UNPLUG, 629 } HotplugEventType; 630 631 static void piix4_cpu_hotplug_req(PIIX4PMState *s, CPUState *cpu, 632 HotplugEventType action) 633 { 634 CPUStatus *g = &s->gpe_cpu; 635 ACPIGPE *gpe = &s->ar.gpe; 636 CPUClass *k = CPU_GET_CLASS(cpu); 637 int64_t cpu_id; 638 639 assert(s != NULL); 640 641 *gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS; 642 cpu_id = k->get_arch_id(CPU(cpu)); 643 if (action == PLUG) { 644 g->sts[cpu_id / 8] |= (1 << (cpu_id % 8)); 645 } else { 646 g->sts[cpu_id / 8] &= ~(1 << (cpu_id % 8)); 647 } 648 pm_update_sci(s); 649 } 650 651 static void piix4_cpu_added_req(Notifier *n, void *opaque) 652 { 653 PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier); 654 655 piix4_cpu_hotplug_req(s, CPU(opaque), PLUG); 656 } 657 658 static void piix4_init_cpu_status(CPUState *cpu, void *data) 659 { 660 CPUStatus *g = (CPUStatus *)data; 661 CPUClass *k = CPU_GET_CLASS(cpu); 662 int64_t id = k->get_arch_id(cpu); 663 664 g_assert((id / 8) < PIIX4_PROC_LEN); 665 g->sts[id / 8] |= (1 << (id % 8)); 666 } 667 668 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, 669 PCIHotplugState state); 670 671 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 672 PCIBus *bus, PIIX4PMState *s) 673 { 674 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 675 "acpi-gpe0", GPE_LEN); 676 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 677 678 memory_region_init_io(&s->io_pci, OBJECT(s), &piix4_pci_ops, s, 679 "acpi-pci-hotplug", PCI_HOTPLUG_SIZE); 680 memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR, 681 &s->io_pci); 682 pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); 683 684 qemu_for_each_cpu(piix4_init_cpu_status, &s->gpe_cpu); 685 memory_region_init_io(&s->io_cpu, OBJECT(s), &cpu_hotplug_ops, s, 686 "acpi-cpu-hotplug", PIIX4_PROC_LEN); 687 memory_region_add_subregion(parent, PIIX4_PROC_BASE, &s->io_cpu); 688 s->cpu_added_notifier.notify = piix4_cpu_added_req; 689 qemu_register_cpu_added_notifier(&s->cpu_added_notifier); 690 } 691 692 static void enable_device(PIIX4PMState *s, int slot) 693 { 694 s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; 695 s->pci0_slot_device_present |= (1U << slot); 696 } 697 698 static void disable_device(PIIX4PMState *s, int slot) 699 { 700 s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; 701 s->pci0_status.down |= (1U << slot); 702 } 703 704 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, 705 PCIHotplugState state) 706 { 707 int slot = PCI_SLOT(dev->devfn); 708 PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, 709 PCI_DEVICE(qdev)); 710 711 /* Don't send event when device is enabled during qemu machine creation: 712 * it is present on boot, no hotplug event is necessary. We do send an 713 * event when the device is disabled later. */ 714 if (state == PCI_COLDPLUG_ENABLED) { 715 s->pci0_slot_device_present |= (1U << slot); 716 return 0; 717 } 718 719 if (state == PCI_HOTPLUG_ENABLED) { 720 enable_device(s, slot); 721 } else { 722 disable_device(s, slot); 723 } 724 725 pm_update_sci(s); 726 727 return 0; 728 } 729