1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 #include "hw/hw.h" 22 #include "hw/i386/pc.h" 23 #include "hw/isa/apm.h" 24 #include "hw/i2c/pm_smbus.h" 25 #include "hw/pci/pci.h" 26 #include "hw/acpi/acpi.h" 27 #include "sysemu/sysemu.h" 28 #include "qemu/range.h" 29 #include "exec/ioport.h" 30 #include "hw/nvram/fw_cfg.h" 31 #include "exec/address-spaces.h" 32 #include "hw/acpi/piix4.h" 33 #include "hw/acpi/pcihp.h" 34 #include "hw/acpi/cpu_hotplug.h" 35 #include "hw/hotplug.h" 36 #include "hw/mem/pc-dimm.h" 37 #include "hw/acpi/memory_hotplug.h" 38 #include "hw/acpi/acpi_dev_interface.h" 39 #include "hw/xen/xen.h" 40 41 //#define DEBUG 42 43 #ifdef DEBUG 44 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 45 #else 46 # define PIIX4_DPRINTF(format, ...) do { } while (0) 47 #endif 48 49 #define GPE_BASE 0xafe0 50 #define GPE_LEN 4 51 52 struct pci_status { 53 uint32_t up; /* deprecated, maintained for migration compatibility */ 54 uint32_t down; 55 }; 56 57 typedef struct PIIX4PMState { 58 /*< private >*/ 59 PCIDevice parent_obj; 60 /*< public >*/ 61 62 MemoryRegion io; 63 uint32_t io_base; 64 65 MemoryRegion io_gpe; 66 ACPIREGS ar; 67 68 APMState apm; 69 70 PMSMBus smb; 71 uint32_t smb_io_base; 72 73 qemu_irq irq; 74 qemu_irq smi_irq; 75 int smm_enabled; 76 Notifier machine_ready; 77 Notifier powerdown_notifier; 78 79 AcpiPciHpState acpi_pci_hotplug; 80 bool use_acpi_pci_hotplug; 81 82 uint8_t disable_s3; 83 uint8_t disable_s4; 84 uint8_t s4_val; 85 86 AcpiCpuHotplug gpe_cpu; 87 88 MemHotplugState acpi_memory_hotplug; 89 } PIIX4PMState; 90 91 #define TYPE_PIIX4_PM "PIIX4_PM" 92 93 #define PIIX4_PM(obj) \ 94 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) 95 96 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 97 PCIBus *bus, PIIX4PMState *s); 98 99 #define ACPI_ENABLE 0xf1 100 #define ACPI_DISABLE 0xf0 101 102 static void pm_tmr_timer(ACPIREGS *ar) 103 { 104 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 105 acpi_update_sci(&s->ar, s->irq); 106 } 107 108 static void apm_ctrl_changed(uint32_t val, void *arg) 109 { 110 PIIX4PMState *s = arg; 111 PCIDevice *d = PCI_DEVICE(s); 112 113 /* ACPI specs 3.0, 4.7.2.5 */ 114 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 115 if (val == ACPI_ENABLE || val == ACPI_DISABLE) { 116 return; 117 } 118 119 if (d->config[0x5b] & (1 << 1)) { 120 if (s->smi_irq) { 121 qemu_irq_raise(s->smi_irq); 122 } 123 } 124 } 125 126 static void pm_io_space_update(PIIX4PMState *s) 127 { 128 PCIDevice *d = PCI_DEVICE(s); 129 130 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 131 s->io_base &= 0xffc0; 132 133 memory_region_transaction_begin(); 134 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 135 memory_region_set_address(&s->io, s->io_base); 136 memory_region_transaction_commit(); 137 } 138 139 static void smbus_io_space_update(PIIX4PMState *s) 140 { 141 PCIDevice *d = PCI_DEVICE(s); 142 143 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 144 s->smb_io_base &= 0xffc0; 145 146 memory_region_transaction_begin(); 147 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 148 memory_region_set_address(&s->smb.io, s->smb_io_base); 149 memory_region_transaction_commit(); 150 } 151 152 static void pm_write_config(PCIDevice *d, 153 uint32_t address, uint32_t val, int len) 154 { 155 pci_default_write_config(d, address, val, len); 156 if (range_covers_byte(address, len, 0x80) || 157 ranges_overlap(address, len, 0x40, 4)) { 158 pm_io_space_update((PIIX4PMState *)d); 159 } 160 if (range_covers_byte(address, len, 0xd2) || 161 ranges_overlap(address, len, 0x90, 4)) { 162 smbus_io_space_update((PIIX4PMState *)d); 163 } 164 } 165 166 static int vmstate_acpi_post_load(void *opaque, int version_id) 167 { 168 PIIX4PMState *s = opaque; 169 170 pm_io_space_update(s); 171 return 0; 172 } 173 174 #define VMSTATE_GPE_ARRAY(_field, _state) \ 175 { \ 176 .name = (stringify(_field)), \ 177 .version_id = 0, \ 178 .info = &vmstate_info_uint16, \ 179 .size = sizeof(uint16_t), \ 180 .flags = VMS_SINGLE | VMS_POINTER, \ 181 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 182 } 183 184 static const VMStateDescription vmstate_gpe = { 185 .name = "gpe", 186 .version_id = 1, 187 .minimum_version_id = 1, 188 .fields = (VMStateField[]) { 189 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 190 VMSTATE_GPE_ARRAY(en, ACPIGPE), 191 VMSTATE_END_OF_LIST() 192 } 193 }; 194 195 static const VMStateDescription vmstate_pci_status = { 196 .name = "pci_status", 197 .version_id = 1, 198 .minimum_version_id = 1, 199 .fields = (VMStateField[]) { 200 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), 201 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), 202 VMSTATE_END_OF_LIST() 203 } 204 }; 205 206 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) 207 { 208 PIIX4PMState *s = opaque; 209 int ret, i; 210 uint16_t temp; 211 212 ret = pci_device_load(PCI_DEVICE(s), f); 213 if (ret < 0) { 214 return ret; 215 } 216 qemu_get_be16s(f, &s->ar.pm1.evt.sts); 217 qemu_get_be16s(f, &s->ar.pm1.evt.en); 218 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); 219 220 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); 221 if (ret) { 222 return ret; 223 } 224 225 timer_get(f, s->ar.tmr.timer); 226 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); 227 228 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); 229 for (i = 0; i < 3; i++) { 230 qemu_get_be16s(f, &temp); 231 } 232 233 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); 234 for (i = 0; i < 3; i++) { 235 qemu_get_be16s(f, &temp); 236 } 237 238 ret = vmstate_load_state(f, &vmstate_pci_status, 239 &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1); 240 return ret; 241 } 242 243 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) 244 { 245 PIIX4PMState *s = opaque; 246 return s->use_acpi_pci_hotplug; 247 } 248 249 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id) 250 { 251 PIIX4PMState *s = opaque; 252 return !s->use_acpi_pci_hotplug; 253 } 254 255 static bool vmstate_test_use_memhp(void *opaque) 256 { 257 PIIX4PMState *s = opaque; 258 return s->acpi_memory_hotplug.is_enabled; 259 } 260 261 static const VMStateDescription vmstate_memhp_state = { 262 .name = "piix4_pm/memhp", 263 .version_id = 1, 264 .minimum_version_id = 1, 265 .minimum_version_id_old = 1, 266 .needed = vmstate_test_use_memhp, 267 .fields = (VMStateField[]) { 268 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), 269 VMSTATE_END_OF_LIST() 270 } 271 }; 272 273 /* qemu-kvm 1.2 uses version 3 but advertised as 2 274 * To support incoming qemu-kvm 1.2 migration, change version_id 275 * and minimum_version_id to 2 below (which breaks migration from 276 * qemu 1.2). 277 * 278 */ 279 static const VMStateDescription vmstate_acpi = { 280 .name = "piix4_pm", 281 .version_id = 3, 282 .minimum_version_id = 3, 283 .minimum_version_id_old = 1, 284 .load_state_old = acpi_load_old, 285 .post_load = vmstate_acpi_post_load, 286 .fields = (VMStateField[]) { 287 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 288 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 289 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 290 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 291 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 292 VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), 293 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 294 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 295 VMSTATE_STRUCT_TEST( 296 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 297 PIIX4PMState, 298 vmstate_test_no_use_acpi_pci_hotplug, 299 2, vmstate_pci_status, 300 struct AcpiPciHpPciStatus), 301 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 302 vmstate_test_use_acpi_pci_hotplug), 303 VMSTATE_END_OF_LIST() 304 }, 305 .subsections = (const VMStateDescription*[]) { 306 &vmstate_memhp_state, 307 NULL 308 } 309 }; 310 311 static void piix4_reset(void *opaque) 312 { 313 PIIX4PMState *s = opaque; 314 PCIDevice *d = PCI_DEVICE(s); 315 uint8_t *pci_conf = d->config; 316 317 pci_conf[0x58] = 0; 318 pci_conf[0x59] = 0; 319 pci_conf[0x5a] = 0; 320 pci_conf[0x5b] = 0; 321 322 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 323 pci_conf[0x80] = 0; 324 325 if (!s->smm_enabled) { 326 /* Mark SMM as already inited (until KVM supports SMM). */ 327 pci_conf[0x5B] = 0x02; 328 } 329 pm_io_space_update(s); 330 acpi_pcihp_reset(&s->acpi_pci_hotplug); 331 } 332 333 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 334 { 335 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 336 337 assert(s != NULL); 338 acpi_pm1_evt_power_down(&s->ar); 339 } 340 341 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, 342 DeviceState *dev, Error **errp) 343 { 344 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 345 346 if (s->acpi_memory_hotplug.is_enabled && 347 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 348 acpi_memory_plug_cb(&s->ar, s->irq, &s->acpi_memory_hotplug, dev, errp); 349 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 350 acpi_pcihp_device_plug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev, 351 errp); 352 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 353 acpi_cpu_plug_cb(&s->ar, s->irq, &s->gpe_cpu, dev, errp); 354 } else { 355 error_setg(errp, "acpi: device plug request for not supported device" 356 " type: %s", object_get_typename(OBJECT(dev))); 357 } 358 } 359 360 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, 361 DeviceState *dev, Error **errp) 362 { 363 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 364 365 if (s->acpi_memory_hotplug.is_enabled && 366 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 367 acpi_memory_unplug_request_cb(&s->ar, s->irq, &s->acpi_memory_hotplug, 368 dev, errp); 369 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 370 acpi_pcihp_device_unplug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev, 371 errp); 372 } else { 373 error_setg(errp, "acpi: device unplug request for not supported device" 374 " type: %s", object_get_typename(OBJECT(dev))); 375 } 376 } 377 378 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, 379 DeviceState *dev, Error **errp) 380 { 381 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 382 383 if (s->acpi_memory_hotplug.is_enabled && 384 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 385 acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); 386 } else { 387 error_setg(errp, "acpi: device unplug for not supported device" 388 " type: %s", object_get_typename(OBJECT(dev))); 389 } 390 } 391 392 static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque) 393 { 394 PIIX4PMState *s = opaque; 395 396 qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort); 397 } 398 399 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 400 { 401 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 402 PCIDevice *d = PCI_DEVICE(s); 403 MemoryRegion *io_as = pci_address_space_io(d); 404 uint8_t *pci_conf; 405 406 pci_conf = d->config; 407 pci_conf[0x5f] = 0x10 | 408 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 409 pci_conf[0x63] = 0x60; 410 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 411 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 412 413 if (s->use_acpi_pci_hotplug) { 414 pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s); 415 } else { 416 piix4_update_bus_hotplug(d->bus, s); 417 } 418 } 419 420 static void piix4_pm_add_propeties(PIIX4PMState *s) 421 { 422 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 423 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 424 static const uint32_t gpe0_blk = GPE_BASE; 425 static const uint32_t gpe0_blk_len = GPE_LEN; 426 static const uint16_t sci_int = 9; 427 428 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 429 &acpi_enable_cmd, NULL); 430 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 431 &acpi_disable_cmd, NULL); 432 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 433 &gpe0_blk, NULL); 434 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 435 &gpe0_blk_len, NULL); 436 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 437 &sci_int, NULL); 438 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 439 &s->io_base, NULL); 440 } 441 442 static void piix4_pm_realize(PCIDevice *dev, Error **errp) 443 { 444 PIIX4PMState *s = PIIX4_PM(dev); 445 uint8_t *pci_conf; 446 447 pci_conf = dev->config; 448 pci_conf[0x06] = 0x80; 449 pci_conf[0x07] = 0x02; 450 pci_conf[0x09] = 0x00; 451 pci_conf[0x3d] = 0x01; // interrupt pin 1 452 453 /* APM */ 454 apm_init(dev, &s->apm, apm_ctrl_changed, s); 455 456 if (!s->smm_enabled) { 457 /* Mark SMM as already inited to prevent SMM from running. KVM does not 458 * support SMM mode. */ 459 pci_conf[0x5B] = 0x02; 460 } 461 462 /* XXX: which specification is used ? The i82731AB has different 463 mappings */ 464 pci_conf[0x90] = s->smb_io_base | 1; 465 pci_conf[0x91] = s->smb_io_base >> 8; 466 pci_conf[0xd2] = 0x09; 467 pm_smbus_init(DEVICE(dev), &s->smb); 468 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 469 memory_region_add_subregion(pci_address_space_io(dev), 470 s->smb_io_base, &s->smb.io); 471 472 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 473 memory_region_set_enabled(&s->io, false); 474 memory_region_add_subregion(pci_address_space_io(dev), 475 0, &s->io); 476 477 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 478 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 479 acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val); 480 acpi_gpe_init(&s->ar, GPE_LEN); 481 482 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 483 qemu_register_powerdown_notifier(&s->powerdown_notifier); 484 485 s->machine_ready.notify = piix4_pm_machine_ready; 486 qemu_add_machine_init_done_notifier(&s->machine_ready); 487 qemu_register_reset(piix4_reset, s); 488 489 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s); 490 491 piix4_pm_add_propeties(s); 492 } 493 494 Object *piix4_pm_find(void) 495 { 496 bool ambig; 497 Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig); 498 499 if (ambig || !o) { 500 return NULL; 501 } 502 return o; 503 } 504 505 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 506 qemu_irq sci_irq, qemu_irq smi_irq, 507 int smm_enabled, DeviceState **piix4_pm) 508 { 509 DeviceState *dev; 510 PIIX4PMState *s; 511 512 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); 513 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 514 if (piix4_pm) { 515 *piix4_pm = dev; 516 } 517 518 s = PIIX4_PM(dev); 519 s->irq = sci_irq; 520 s->smi_irq = smi_irq; 521 s->smm_enabled = smm_enabled; 522 if (xen_enabled()) { 523 s->use_acpi_pci_hotplug = false; 524 } 525 526 qdev_init_nofail(dev); 527 528 return s->smb.smbus; 529 } 530 531 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 532 { 533 PIIX4PMState *s = opaque; 534 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 535 536 PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); 537 return val; 538 } 539 540 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 541 unsigned width) 542 { 543 PIIX4PMState *s = opaque; 544 545 acpi_gpe_ioport_writeb(&s->ar, addr, val); 546 acpi_update_sci(&s->ar, s->irq); 547 548 PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); 549 } 550 551 static const MemoryRegionOps piix4_gpe_ops = { 552 .read = gpe_readb, 553 .write = gpe_writeb, 554 .valid.min_access_size = 1, 555 .valid.max_access_size = 4, 556 .impl.min_access_size = 1, 557 .impl.max_access_size = 1, 558 .endianness = DEVICE_LITTLE_ENDIAN, 559 }; 560 561 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 562 PCIBus *bus, PIIX4PMState *s) 563 { 564 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 565 "acpi-gpe0", GPE_LEN); 566 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 567 568 acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, 569 s->use_acpi_pci_hotplug); 570 571 acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, 572 PIIX4_CPU_HOTPLUG_IO_BASE); 573 574 if (s->acpi_memory_hotplug.is_enabled) { 575 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug); 576 } 577 } 578 579 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) 580 { 581 PIIX4PMState *s = PIIX4_PM(adev); 582 583 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); 584 } 585 586 static Property piix4_pm_properties[] = { 587 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 588 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 589 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 590 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 591 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, 592 use_acpi_pci_hotplug, true), 593 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, 594 acpi_memory_hotplug.is_enabled, true), 595 DEFINE_PROP_END_OF_LIST(), 596 }; 597 598 static void piix4_pm_class_init(ObjectClass *klass, void *data) 599 { 600 DeviceClass *dc = DEVICE_CLASS(klass); 601 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 602 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 603 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 604 605 k->realize = piix4_pm_realize; 606 k->config_write = pm_write_config; 607 k->vendor_id = PCI_VENDOR_ID_INTEL; 608 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 609 k->revision = 0x03; 610 k->class_id = PCI_CLASS_BRIDGE_OTHER; 611 dc->desc = "PM"; 612 dc->vmsd = &vmstate_acpi; 613 dc->props = piix4_pm_properties; 614 /* 615 * Reason: part of PIIX4 southbridge, needs to be wired up, 616 * e.g. by mips_malta_init() 617 */ 618 dc->cannot_instantiate_with_device_add_yet = true; 619 dc->hotpluggable = false; 620 hc->plug = piix4_device_plug_cb; 621 hc->unplug_request = piix4_device_unplug_request_cb; 622 hc->unplug = piix4_device_unplug_cb; 623 adevc->ospm_status = piix4_ospm_status; 624 } 625 626 static const TypeInfo piix4_pm_info = { 627 .name = TYPE_PIIX4_PM, 628 .parent = TYPE_PCI_DEVICE, 629 .instance_size = sizeof(PIIX4PMState), 630 .class_init = piix4_pm_class_init, 631 .interfaces = (InterfaceInfo[]) { 632 { TYPE_HOTPLUG_HANDLER }, 633 { TYPE_ACPI_DEVICE_IF }, 634 { } 635 } 636 }; 637 638 static void piix4_pm_register_types(void) 639 { 640 type_register_static(&piix4_pm_info); 641 } 642 643 type_init(piix4_pm_register_types) 644