1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 #include "hw/hw.h" 22 #include "hw/i386/pc.h" 23 #include "hw/isa/apm.h" 24 #include "hw/i2c/pm_smbus.h" 25 #include "hw/pci/pci.h" 26 #include "hw/acpi/acpi.h" 27 #include "sysemu/sysemu.h" 28 #include "qemu/range.h" 29 #include "exec/ioport.h" 30 #include "hw/nvram/fw_cfg.h" 31 #include "exec/address-spaces.h" 32 #include "hw/acpi/piix4.h" 33 #include "hw/acpi/pcihp.h" 34 #include "hw/acpi/cpu_hotplug.h" 35 36 //#define DEBUG 37 38 #ifdef DEBUG 39 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 40 #else 41 # define PIIX4_DPRINTF(format, ...) do { } while (0) 42 #endif 43 44 #define GPE_BASE 0xafe0 45 #define GPE_LEN 4 46 47 #define PCI_HOTPLUG_ADDR 0xae00 48 #define PCI_HOTPLUG_SIZE 0x000f 49 #define PCI_UP_BASE 0xae00 50 #define PCI_DOWN_BASE 0xae04 51 #define PCI_EJ_BASE 0xae08 52 #define PCI_RMV_BASE 0xae0c 53 54 #define PIIX4_PCI_HOTPLUG_STATUS 2 55 56 struct pci_status { 57 uint32_t up; /* deprecated, maintained for migration compatibility */ 58 uint32_t down; 59 }; 60 61 typedef struct PIIX4PMState { 62 /*< private >*/ 63 PCIDevice parent_obj; 64 /*< public >*/ 65 66 MemoryRegion io; 67 uint32_t io_base; 68 69 MemoryRegion io_gpe; 70 ACPIREGS ar; 71 72 APMState apm; 73 74 PMSMBus smb; 75 uint32_t smb_io_base; 76 77 qemu_irq irq; 78 qemu_irq smi_irq; 79 int kvm_enabled; 80 Notifier machine_ready; 81 Notifier powerdown_notifier; 82 83 /* for legacy pci hotplug (compatible with qemu 1.6 and older) */ 84 MemoryRegion io_pci; 85 struct pci_status pci0_status; 86 uint32_t pci0_hotplug_enable; 87 uint32_t pci0_slot_device_present; 88 89 /* for new pci hotplug (with PCI2PCI bridge support) */ 90 AcpiPciHpState acpi_pci_hotplug; 91 bool use_acpi_pci_hotplug; 92 93 uint8_t disable_s3; 94 uint8_t disable_s4; 95 uint8_t s4_val; 96 97 AcpiCpuHotplug gpe_cpu; 98 Notifier cpu_added_notifier; 99 } PIIX4PMState; 100 101 #define TYPE_PIIX4_PM "PIIX4_PM" 102 103 #define PIIX4_PM(obj) \ 104 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) 105 106 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 107 PCIBus *bus, PIIX4PMState *s); 108 109 #define ACPI_ENABLE 0xf1 110 #define ACPI_DISABLE 0xf0 111 112 static void pm_tmr_timer(ACPIREGS *ar) 113 { 114 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 115 acpi_update_sci(&s->ar, s->irq); 116 } 117 118 static void apm_ctrl_changed(uint32_t val, void *arg) 119 { 120 PIIX4PMState *s = arg; 121 PCIDevice *d = PCI_DEVICE(s); 122 123 /* ACPI specs 3.0, 4.7.2.5 */ 124 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 125 126 if (d->config[0x5b] & (1 << 1)) { 127 if (s->smi_irq) { 128 qemu_irq_raise(s->smi_irq); 129 } 130 } 131 } 132 133 static void pm_io_space_update(PIIX4PMState *s) 134 { 135 PCIDevice *d = PCI_DEVICE(s); 136 137 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 138 s->io_base &= 0xffc0; 139 140 memory_region_transaction_begin(); 141 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 142 memory_region_set_address(&s->io, s->io_base); 143 memory_region_transaction_commit(); 144 } 145 146 static void smbus_io_space_update(PIIX4PMState *s) 147 { 148 PCIDevice *d = PCI_DEVICE(s); 149 150 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 151 s->smb_io_base &= 0xffc0; 152 153 memory_region_transaction_begin(); 154 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 155 memory_region_set_address(&s->smb.io, s->smb_io_base); 156 memory_region_transaction_commit(); 157 } 158 159 static void pm_write_config(PCIDevice *d, 160 uint32_t address, uint32_t val, int len) 161 { 162 pci_default_write_config(d, address, val, len); 163 if (range_covers_byte(address, len, 0x80) || 164 ranges_overlap(address, len, 0x40, 4)) { 165 pm_io_space_update((PIIX4PMState *)d); 166 } 167 if (range_covers_byte(address, len, 0xd2) || 168 ranges_overlap(address, len, 0x90, 4)) { 169 smbus_io_space_update((PIIX4PMState *)d); 170 } 171 } 172 173 static void vmstate_pci_status_pre_save(void *opaque) 174 { 175 struct pci_status *pci0_status = opaque; 176 PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status); 177 178 /* We no longer track up, so build a safe value for migrating 179 * to a version that still does... of course these might get lost 180 * by an old buggy implementation, but we try. */ 181 pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable; 182 } 183 184 static int vmstate_acpi_post_load(void *opaque, int version_id) 185 { 186 PIIX4PMState *s = opaque; 187 188 pm_io_space_update(s); 189 return 0; 190 } 191 192 #define VMSTATE_GPE_ARRAY(_field, _state) \ 193 { \ 194 .name = (stringify(_field)), \ 195 .version_id = 0, \ 196 .info = &vmstate_info_uint16, \ 197 .size = sizeof(uint16_t), \ 198 .flags = VMS_SINGLE | VMS_POINTER, \ 199 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 200 } 201 202 static const VMStateDescription vmstate_gpe = { 203 .name = "gpe", 204 .version_id = 1, 205 .minimum_version_id = 1, 206 .minimum_version_id_old = 1, 207 .fields = (VMStateField []) { 208 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 209 VMSTATE_GPE_ARRAY(en, ACPIGPE), 210 VMSTATE_END_OF_LIST() 211 } 212 }; 213 214 static const VMStateDescription vmstate_pci_status = { 215 .name = "pci_status", 216 .version_id = 1, 217 .minimum_version_id = 1, 218 .minimum_version_id_old = 1, 219 .pre_save = vmstate_pci_status_pre_save, 220 .fields = (VMStateField []) { 221 VMSTATE_UINT32(up, struct pci_status), 222 VMSTATE_UINT32(down, struct pci_status), 223 VMSTATE_END_OF_LIST() 224 } 225 }; 226 227 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) 228 { 229 PIIX4PMState *s = opaque; 230 int ret, i; 231 uint16_t temp; 232 233 ret = pci_device_load(PCI_DEVICE(s), f); 234 if (ret < 0) { 235 return ret; 236 } 237 qemu_get_be16s(f, &s->ar.pm1.evt.sts); 238 qemu_get_be16s(f, &s->ar.pm1.evt.en); 239 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); 240 241 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); 242 if (ret) { 243 return ret; 244 } 245 246 timer_get(f, s->ar.tmr.timer); 247 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); 248 249 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); 250 for (i = 0; i < 3; i++) { 251 qemu_get_be16s(f, &temp); 252 } 253 254 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); 255 for (i = 0; i < 3; i++) { 256 qemu_get_be16s(f, &temp); 257 } 258 259 ret = vmstate_load_state(f, &vmstate_pci_status, &s->pci0_status, 1); 260 return ret; 261 } 262 263 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) 264 { 265 PIIX4PMState *s = opaque; 266 return s->use_acpi_pci_hotplug; 267 } 268 269 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id) 270 { 271 PIIX4PMState *s = opaque; 272 return !s->use_acpi_pci_hotplug; 273 } 274 275 /* qemu-kvm 1.2 uses version 3 but advertised as 2 276 * To support incoming qemu-kvm 1.2 migration, change version_id 277 * and minimum_version_id to 2 below (which breaks migration from 278 * qemu 1.2). 279 * 280 */ 281 static const VMStateDescription vmstate_acpi = { 282 .name = "piix4_pm", 283 .version_id = 3, 284 .minimum_version_id = 3, 285 .minimum_version_id_old = 1, 286 .load_state_old = acpi_load_old, 287 .post_load = vmstate_acpi_post_load, 288 .fields = (VMStateField []) { 289 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 290 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 291 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 292 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 293 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 294 VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), 295 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 296 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 297 VMSTATE_STRUCT_TEST(pci0_status, PIIX4PMState, 298 vmstate_test_no_use_acpi_pci_hotplug, 299 2, vmstate_pci_status, 300 struct pci_status), 301 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 302 vmstate_test_use_acpi_pci_hotplug), 303 VMSTATE_END_OF_LIST() 304 } 305 }; 306 307 static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) 308 { 309 BusChild *kid, *next; 310 BusState *bus = qdev_get_parent_bus(DEVICE(s)); 311 int slot = ffs(slots) - 1; 312 bool slot_free = true; 313 314 /* Mark request as complete */ 315 s->pci0_status.down &= ~(1U << slot); 316 317 QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { 318 DeviceState *qdev = kid->child; 319 PCIDevice *dev = PCI_DEVICE(qdev); 320 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 321 if (PCI_SLOT(dev->devfn) == slot) { 322 if (pc->no_hotplug) { 323 slot_free = false; 324 } else { 325 object_unparent(OBJECT(qdev)); 326 } 327 } 328 } 329 if (slot_free) { 330 s->pci0_slot_device_present &= ~(1U << slot); 331 } 332 } 333 334 static void piix4_update_hotplug(PIIX4PMState *s) 335 { 336 BusState *bus = qdev_get_parent_bus(DEVICE(s)); 337 BusChild *kid, *next; 338 339 /* Execute any pending removes during reset */ 340 while (s->pci0_status.down) { 341 acpi_piix_eject_slot(s, s->pci0_status.down); 342 } 343 344 s->pci0_hotplug_enable = ~0; 345 s->pci0_slot_device_present = 0; 346 347 QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { 348 DeviceState *qdev = kid->child; 349 PCIDevice *pdev = PCI_DEVICE(qdev); 350 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); 351 int slot = PCI_SLOT(pdev->devfn); 352 353 if (pc->no_hotplug) { 354 s->pci0_hotplug_enable &= ~(1U << slot); 355 } 356 357 s->pci0_slot_device_present |= (1U << slot); 358 } 359 } 360 361 static void piix4_reset(void *opaque) 362 { 363 PIIX4PMState *s = opaque; 364 PCIDevice *d = PCI_DEVICE(s); 365 uint8_t *pci_conf = d->config; 366 367 pci_conf[0x58] = 0; 368 pci_conf[0x59] = 0; 369 pci_conf[0x5a] = 0; 370 pci_conf[0x5b] = 0; 371 372 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 373 pci_conf[0x80] = 0; 374 375 if (s->kvm_enabled) { 376 /* Mark SMM as already inited (until KVM supports SMM). */ 377 pci_conf[0x5B] = 0x02; 378 } 379 pm_io_space_update(s); 380 if (s->use_acpi_pci_hotplug) { 381 acpi_pcihp_reset(&s->acpi_pci_hotplug); 382 } else { 383 piix4_update_hotplug(s); 384 } 385 } 386 387 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 388 { 389 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 390 391 assert(s != NULL); 392 acpi_pm1_evt_power_down(&s->ar); 393 } 394 395 static int piix4_acpi_pci_hotplug(DeviceState *qdev, PCIDevice *dev, 396 PCIHotplugState state) 397 { 398 PIIX4PMState *s = PIIX4_PM(qdev); 399 int ret = acpi_pcihp_device_hotplug(&s->acpi_pci_hotplug, dev, state); 400 if (ret < 0) { 401 return ret; 402 } 403 s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; 404 405 acpi_update_sci(&s->ar, s->irq); 406 return 0; 407 } 408 409 static void piix4_update_bus_hotplug(PCIBus *bus, void *opaque) 410 { 411 PIIX4PMState *s = opaque; 412 pci_bus_hotplug(bus, piix4_acpi_pci_hotplug, DEVICE(s)); 413 } 414 415 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 416 { 417 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 418 PCIDevice *d = PCI_DEVICE(s); 419 MemoryRegion *io_as = pci_address_space_io(d); 420 uint8_t *pci_conf; 421 422 pci_conf = d->config; 423 pci_conf[0x5f] = 0x10 | 424 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 425 pci_conf[0x63] = 0x60; 426 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 427 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 428 429 if (s->use_acpi_pci_hotplug) { 430 pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s); 431 } 432 } 433 434 static void piix4_pm_add_propeties(PIIX4PMState *s) 435 { 436 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 437 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 438 static const uint32_t gpe0_blk = GPE_BASE; 439 static const uint32_t gpe0_blk_len = GPE_LEN; 440 static const uint16_t sci_int = 9; 441 442 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 443 &acpi_enable_cmd, NULL); 444 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 445 &acpi_disable_cmd, NULL); 446 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 447 &gpe0_blk, NULL); 448 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 449 &gpe0_blk_len, NULL); 450 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 451 &sci_int, NULL); 452 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 453 &s->io_base, NULL); 454 } 455 456 static int piix4_pm_initfn(PCIDevice *dev) 457 { 458 PIIX4PMState *s = PIIX4_PM(dev); 459 uint8_t *pci_conf; 460 461 pci_conf = dev->config; 462 pci_conf[0x06] = 0x80; 463 pci_conf[0x07] = 0x02; 464 pci_conf[0x09] = 0x00; 465 pci_conf[0x3d] = 0x01; // interrupt pin 1 466 467 /* APM */ 468 apm_init(dev, &s->apm, apm_ctrl_changed, s); 469 470 if (s->kvm_enabled) { 471 /* Mark SMM as already inited to prevent SMM from running. KVM does not 472 * support SMM mode. */ 473 pci_conf[0x5B] = 0x02; 474 } 475 476 /* XXX: which specification is used ? The i82731AB has different 477 mappings */ 478 pci_conf[0x90] = s->smb_io_base | 1; 479 pci_conf[0x91] = s->smb_io_base >> 8; 480 pci_conf[0xd2] = 0x09; 481 pm_smbus_init(DEVICE(dev), &s->smb); 482 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 483 memory_region_add_subregion(pci_address_space_io(dev), 484 s->smb_io_base, &s->smb.io); 485 486 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 487 memory_region_set_enabled(&s->io, false); 488 memory_region_add_subregion(pci_address_space_io(dev), 489 0, &s->io); 490 491 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 492 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 493 acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val); 494 acpi_gpe_init(&s->ar, GPE_LEN); 495 496 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 497 qemu_register_powerdown_notifier(&s->powerdown_notifier); 498 499 s->machine_ready.notify = piix4_pm_machine_ready; 500 qemu_add_machine_init_done_notifier(&s->machine_ready); 501 qemu_register_reset(piix4_reset, s); 502 503 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s); 504 505 piix4_pm_add_propeties(s); 506 return 0; 507 } 508 509 Object *piix4_pm_find(void) 510 { 511 bool ambig; 512 Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig); 513 514 if (ambig || !o) { 515 return NULL; 516 } 517 return o; 518 } 519 520 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 521 qemu_irq sci_irq, qemu_irq smi_irq, 522 int kvm_enabled, FWCfgState *fw_cfg) 523 { 524 DeviceState *dev; 525 PIIX4PMState *s; 526 527 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); 528 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 529 530 s = PIIX4_PM(dev); 531 s->irq = sci_irq; 532 s->smi_irq = smi_irq; 533 s->kvm_enabled = kvm_enabled; 534 535 qdev_init_nofail(dev); 536 537 if (fw_cfg) { 538 uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; 539 suspend[3] = 1 | ((!s->disable_s3) << 7); 540 suspend[4] = s->s4_val | ((!s->disable_s4) << 7); 541 542 fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); 543 } 544 545 return s->smb.smbus; 546 } 547 548 static Property piix4_pm_properties[] = { 549 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 550 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 551 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 552 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 553 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, 554 use_acpi_pci_hotplug, true), 555 DEFINE_PROP_END_OF_LIST(), 556 }; 557 558 static void piix4_pm_class_init(ObjectClass *klass, void *data) 559 { 560 DeviceClass *dc = DEVICE_CLASS(klass); 561 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 562 563 k->no_hotplug = 1; 564 k->init = piix4_pm_initfn; 565 k->config_write = pm_write_config; 566 k->vendor_id = PCI_VENDOR_ID_INTEL; 567 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 568 k->revision = 0x03; 569 k->class_id = PCI_CLASS_BRIDGE_OTHER; 570 dc->desc = "PM"; 571 dc->vmsd = &vmstate_acpi; 572 dc->props = piix4_pm_properties; 573 /* 574 * Reason: part of PIIX4 southbridge, needs to be wired up, 575 * e.g. by mips_malta_init() 576 */ 577 dc->cannot_instantiate_with_device_add_yet = true; 578 } 579 580 static const TypeInfo piix4_pm_info = { 581 .name = TYPE_PIIX4_PM, 582 .parent = TYPE_PCI_DEVICE, 583 .instance_size = sizeof(PIIX4PMState), 584 .class_init = piix4_pm_class_init, 585 }; 586 587 static void piix4_pm_register_types(void) 588 { 589 type_register_static(&piix4_pm_info); 590 } 591 592 type_init(piix4_pm_register_types) 593 594 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 595 { 596 PIIX4PMState *s = opaque; 597 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 598 599 PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); 600 return val; 601 } 602 603 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 604 unsigned width) 605 { 606 PIIX4PMState *s = opaque; 607 608 acpi_gpe_ioport_writeb(&s->ar, addr, val); 609 acpi_update_sci(&s->ar, s->irq); 610 611 PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); 612 } 613 614 static const MemoryRegionOps piix4_gpe_ops = { 615 .read = gpe_readb, 616 .write = gpe_writeb, 617 .valid.min_access_size = 1, 618 .valid.max_access_size = 4, 619 .impl.min_access_size = 1, 620 .impl.max_access_size = 1, 621 .endianness = DEVICE_LITTLE_ENDIAN, 622 }; 623 624 static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) 625 { 626 PIIX4PMState *s = opaque; 627 uint32_t val = 0; 628 629 switch (addr) { 630 case PCI_UP_BASE - PCI_HOTPLUG_ADDR: 631 /* Manufacture an "up" value to cause a device check on any hotplug 632 * slot with a device. Extra device checks are harmless. */ 633 val = s->pci0_slot_device_present & s->pci0_hotplug_enable; 634 PIIX4_DPRINTF("pci_up_read %" PRIu32 "\n", val); 635 break; 636 case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR: 637 val = s->pci0_status.down; 638 PIIX4_DPRINTF("pci_down_read %" PRIu32 "\n", val); 639 break; 640 case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: 641 /* No feature defined yet */ 642 PIIX4_DPRINTF("pci_features_read %" PRIu32 "\n", val); 643 break; 644 case PCI_RMV_BASE - PCI_HOTPLUG_ADDR: 645 val = s->pci0_hotplug_enable; 646 break; 647 default: 648 break; 649 } 650 651 return val; 652 } 653 654 static void pci_write(void *opaque, hwaddr addr, uint64_t data, 655 unsigned int size) 656 { 657 switch (addr) { 658 case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: 659 acpi_piix_eject_slot(opaque, (uint32_t)data); 660 PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n", 661 addr, data); 662 break; 663 default: 664 break; 665 } 666 } 667 668 static const MemoryRegionOps piix4_pci_ops = { 669 .read = pci_read, 670 .write = pci_write, 671 .endianness = DEVICE_LITTLE_ENDIAN, 672 .valid = { 673 .min_access_size = 4, 674 .max_access_size = 4, 675 }, 676 }; 677 678 static void piix4_cpu_added_req(Notifier *n, void *opaque) 679 { 680 PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier); 681 682 assert(s != NULL); 683 AcpiCpuHotplug_add(&s->ar.gpe, &s->gpe_cpu, CPU(opaque)); 684 acpi_update_sci(&s->ar, s->irq); 685 } 686 687 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, 688 PCIHotplugState state); 689 690 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 691 PCIBus *bus, PIIX4PMState *s) 692 { 693 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 694 "acpi-gpe0", GPE_LEN); 695 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 696 697 if (s->use_acpi_pci_hotplug) { 698 acpi_pcihp_init(&s->acpi_pci_hotplug, bus, parent); 699 } else { 700 memory_region_init_io(&s->io_pci, OBJECT(s), &piix4_pci_ops, s, 701 "acpi-pci-hotplug", PCI_HOTPLUG_SIZE); 702 memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR, 703 &s->io_pci); 704 pci_bus_hotplug(bus, piix4_device_hotplug, DEVICE(s)); 705 } 706 707 AcpiCpuHotplug_init(parent, OBJECT(s), &s->gpe_cpu, 708 PIIX4_CPU_HOTPLUG_IO_BASE); 709 s->cpu_added_notifier.notify = piix4_cpu_added_req; 710 qemu_register_cpu_added_notifier(&s->cpu_added_notifier); 711 } 712 713 static void enable_device(PIIX4PMState *s, int slot) 714 { 715 s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; 716 s->pci0_slot_device_present |= (1U << slot); 717 } 718 719 static void disable_device(PIIX4PMState *s, int slot) 720 { 721 s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; 722 s->pci0_status.down |= (1U << slot); 723 } 724 725 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, 726 PCIHotplugState state) 727 { 728 int slot = PCI_SLOT(dev->devfn); 729 PIIX4PMState *s = PIIX4_PM(qdev); 730 731 /* Don't send event when device is enabled during qemu machine creation: 732 * it is present on boot, no hotplug event is necessary. We do send an 733 * event when the device is disabled later. */ 734 if (state == PCI_COLDPLUG_ENABLED) { 735 s->pci0_slot_device_present |= (1U << slot); 736 return 0; 737 } 738 739 if (state == PCI_HOTPLUG_ENABLED) { 740 enable_device(s, slot); 741 } else { 742 disable_device(s, slot); 743 } 744 745 acpi_update_sci(&s->ar, s->irq); 746 747 return 0; 748 } 749