1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 #include "hw/hw.h" 22 #include "hw/i386/pc.h" 23 #include "hw/isa/apm.h" 24 #include "hw/i2c/pm_smbus.h" 25 #include "hw/pci/pci.h" 26 #include "hw/acpi/acpi.h" 27 #include "sysemu/sysemu.h" 28 #include "qemu/range.h" 29 #include "exec/ioport.h" 30 #include "hw/nvram/fw_cfg.h" 31 #include "exec/address-spaces.h" 32 #include "hw/acpi/piix4.h" 33 #include "hw/acpi/pcihp.h" 34 #include "hw/acpi/cpu_hotplug.h" 35 #include "hw/hotplug.h" 36 #include "hw/mem/pc-dimm.h" 37 #include "hw/acpi/memory_hotplug.h" 38 #include "hw/acpi/acpi_dev_interface.h" 39 40 //#define DEBUG 41 42 #ifdef DEBUG 43 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 44 #else 45 # define PIIX4_DPRINTF(format, ...) do { } while (0) 46 #endif 47 48 #define GPE_BASE 0xafe0 49 #define GPE_LEN 4 50 51 struct pci_status { 52 uint32_t up; /* deprecated, maintained for migration compatibility */ 53 uint32_t down; 54 }; 55 56 typedef struct PIIX4PMState { 57 /*< private >*/ 58 PCIDevice parent_obj; 59 /*< public >*/ 60 61 MemoryRegion io; 62 uint32_t io_base; 63 64 MemoryRegion io_gpe; 65 ACPIREGS ar; 66 67 APMState apm; 68 69 PMSMBus smb; 70 uint32_t smb_io_base; 71 72 qemu_irq irq; 73 qemu_irq smi_irq; 74 int kvm_enabled; 75 Notifier machine_ready; 76 Notifier powerdown_notifier; 77 78 AcpiPciHpState acpi_pci_hotplug; 79 bool use_acpi_pci_hotplug; 80 81 uint8_t disable_s3; 82 uint8_t disable_s4; 83 uint8_t s4_val; 84 85 AcpiCpuHotplug gpe_cpu; 86 87 MemHotplugState acpi_memory_hotplug; 88 } PIIX4PMState; 89 90 #define TYPE_PIIX4_PM "PIIX4_PM" 91 92 #define PIIX4_PM(obj) \ 93 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) 94 95 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 96 PCIBus *bus, PIIX4PMState *s); 97 98 #define ACPI_ENABLE 0xf1 99 #define ACPI_DISABLE 0xf0 100 101 static void pm_tmr_timer(ACPIREGS *ar) 102 { 103 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 104 acpi_update_sci(&s->ar, s->irq); 105 } 106 107 static void apm_ctrl_changed(uint32_t val, void *arg) 108 { 109 PIIX4PMState *s = arg; 110 PCIDevice *d = PCI_DEVICE(s); 111 112 /* ACPI specs 3.0, 4.7.2.5 */ 113 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 114 115 if (d->config[0x5b] & (1 << 1)) { 116 if (s->smi_irq) { 117 qemu_irq_raise(s->smi_irq); 118 } 119 } 120 } 121 122 static void pm_io_space_update(PIIX4PMState *s) 123 { 124 PCIDevice *d = PCI_DEVICE(s); 125 126 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 127 s->io_base &= 0xffc0; 128 129 memory_region_transaction_begin(); 130 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 131 memory_region_set_address(&s->io, s->io_base); 132 memory_region_transaction_commit(); 133 } 134 135 static void smbus_io_space_update(PIIX4PMState *s) 136 { 137 PCIDevice *d = PCI_DEVICE(s); 138 139 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 140 s->smb_io_base &= 0xffc0; 141 142 memory_region_transaction_begin(); 143 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 144 memory_region_set_address(&s->smb.io, s->smb_io_base); 145 memory_region_transaction_commit(); 146 } 147 148 static void pm_write_config(PCIDevice *d, 149 uint32_t address, uint32_t val, int len) 150 { 151 pci_default_write_config(d, address, val, len); 152 if (range_covers_byte(address, len, 0x80) || 153 ranges_overlap(address, len, 0x40, 4)) { 154 pm_io_space_update((PIIX4PMState *)d); 155 } 156 if (range_covers_byte(address, len, 0xd2) || 157 ranges_overlap(address, len, 0x90, 4)) { 158 smbus_io_space_update((PIIX4PMState *)d); 159 } 160 } 161 162 static int vmstate_acpi_post_load(void *opaque, int version_id) 163 { 164 PIIX4PMState *s = opaque; 165 166 pm_io_space_update(s); 167 return 0; 168 } 169 170 #define VMSTATE_GPE_ARRAY(_field, _state) \ 171 { \ 172 .name = (stringify(_field)), \ 173 .version_id = 0, \ 174 .info = &vmstate_info_uint16, \ 175 .size = sizeof(uint16_t), \ 176 .flags = VMS_SINGLE | VMS_POINTER, \ 177 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 178 } 179 180 static const VMStateDescription vmstate_gpe = { 181 .name = "gpe", 182 .version_id = 1, 183 .minimum_version_id = 1, 184 .fields = (VMStateField[]) { 185 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 186 VMSTATE_GPE_ARRAY(en, ACPIGPE), 187 VMSTATE_END_OF_LIST() 188 } 189 }; 190 191 static const VMStateDescription vmstate_pci_status = { 192 .name = "pci_status", 193 .version_id = 1, 194 .minimum_version_id = 1, 195 .fields = (VMStateField[]) { 196 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), 197 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), 198 VMSTATE_END_OF_LIST() 199 } 200 }; 201 202 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) 203 { 204 PIIX4PMState *s = opaque; 205 int ret, i; 206 uint16_t temp; 207 208 ret = pci_device_load(PCI_DEVICE(s), f); 209 if (ret < 0) { 210 return ret; 211 } 212 qemu_get_be16s(f, &s->ar.pm1.evt.sts); 213 qemu_get_be16s(f, &s->ar.pm1.evt.en); 214 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); 215 216 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); 217 if (ret) { 218 return ret; 219 } 220 221 timer_get(f, s->ar.tmr.timer); 222 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); 223 224 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); 225 for (i = 0; i < 3; i++) { 226 qemu_get_be16s(f, &temp); 227 } 228 229 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); 230 for (i = 0; i < 3; i++) { 231 qemu_get_be16s(f, &temp); 232 } 233 234 ret = vmstate_load_state(f, &vmstate_pci_status, 235 &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1); 236 return ret; 237 } 238 239 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) 240 { 241 PIIX4PMState *s = opaque; 242 return s->use_acpi_pci_hotplug; 243 } 244 245 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id) 246 { 247 PIIX4PMState *s = opaque; 248 return !s->use_acpi_pci_hotplug; 249 } 250 251 static bool vmstate_test_use_memhp(void *opaque) 252 { 253 PIIX4PMState *s = opaque; 254 return s->acpi_memory_hotplug.is_enabled; 255 } 256 257 static const VMStateDescription vmstate_memhp_state = { 258 .name = "piix4_pm/memhp", 259 .version_id = 1, 260 .minimum_version_id = 1, 261 .minimum_version_id_old = 1, 262 .fields = (VMStateField[]) { 263 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), 264 VMSTATE_END_OF_LIST() 265 } 266 }; 267 268 /* qemu-kvm 1.2 uses version 3 but advertised as 2 269 * To support incoming qemu-kvm 1.2 migration, change version_id 270 * and minimum_version_id to 2 below (which breaks migration from 271 * qemu 1.2). 272 * 273 */ 274 static const VMStateDescription vmstate_acpi = { 275 .name = "piix4_pm", 276 .version_id = 3, 277 .minimum_version_id = 3, 278 .minimum_version_id_old = 1, 279 .load_state_old = acpi_load_old, 280 .post_load = vmstate_acpi_post_load, 281 .fields = (VMStateField[]) { 282 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 283 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 284 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 285 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 286 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 287 VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), 288 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 289 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 290 VMSTATE_STRUCT_TEST( 291 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 292 PIIX4PMState, 293 vmstate_test_no_use_acpi_pci_hotplug, 294 2, vmstate_pci_status, 295 struct AcpiPciHpPciStatus), 296 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 297 vmstate_test_use_acpi_pci_hotplug), 298 VMSTATE_END_OF_LIST() 299 }, 300 .subsections = (VMStateSubsection[]) { 301 { 302 .vmsd = &vmstate_memhp_state, 303 .needed = vmstate_test_use_memhp, 304 }, 305 VMSTATE_END_OF_LIST() 306 } 307 }; 308 309 static void piix4_reset(void *opaque) 310 { 311 PIIX4PMState *s = opaque; 312 PCIDevice *d = PCI_DEVICE(s); 313 uint8_t *pci_conf = d->config; 314 315 pci_conf[0x58] = 0; 316 pci_conf[0x59] = 0; 317 pci_conf[0x5a] = 0; 318 pci_conf[0x5b] = 0; 319 320 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 321 pci_conf[0x80] = 0; 322 323 if (s->kvm_enabled) { 324 /* Mark SMM as already inited (until KVM supports SMM). */ 325 pci_conf[0x5B] = 0x02; 326 } 327 pm_io_space_update(s); 328 acpi_pcihp_reset(&s->acpi_pci_hotplug); 329 } 330 331 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 332 { 333 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 334 335 assert(s != NULL); 336 acpi_pm1_evt_power_down(&s->ar); 337 } 338 339 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, 340 DeviceState *dev, Error **errp) 341 { 342 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 343 344 if (s->acpi_memory_hotplug.is_enabled && 345 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 346 acpi_memory_plug_cb(&s->ar, s->irq, &s->acpi_memory_hotplug, dev, errp); 347 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 348 acpi_pcihp_device_plug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev, 349 errp); 350 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 351 acpi_cpu_plug_cb(&s->ar, s->irq, &s->gpe_cpu, dev, errp); 352 } else { 353 error_setg(errp, "acpi: device plug request for not supported device" 354 " type: %s", object_get_typename(OBJECT(dev))); 355 } 356 } 357 358 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, 359 DeviceState *dev, Error **errp) 360 { 361 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 362 363 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 364 acpi_pcihp_device_unplug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev, 365 errp); 366 } else { 367 error_setg(errp, "acpi: device unplug request for not supported device" 368 " type: %s", object_get_typename(OBJECT(dev))); 369 } 370 } 371 372 static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque) 373 { 374 PIIX4PMState *s = opaque; 375 376 qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort); 377 } 378 379 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 380 { 381 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 382 PCIDevice *d = PCI_DEVICE(s); 383 MemoryRegion *io_as = pci_address_space_io(d); 384 uint8_t *pci_conf; 385 386 pci_conf = d->config; 387 pci_conf[0x5f] = 0x10 | 388 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 389 pci_conf[0x63] = 0x60; 390 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 391 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 392 393 if (s->use_acpi_pci_hotplug) { 394 pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s); 395 } else { 396 piix4_update_bus_hotplug(d->bus, s); 397 } 398 } 399 400 static void piix4_pm_add_propeties(PIIX4PMState *s) 401 { 402 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 403 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 404 static const uint32_t gpe0_blk = GPE_BASE; 405 static const uint32_t gpe0_blk_len = GPE_LEN; 406 static const uint16_t sci_int = 9; 407 408 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 409 &acpi_enable_cmd, NULL); 410 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 411 &acpi_disable_cmd, NULL); 412 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 413 &gpe0_blk, NULL); 414 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 415 &gpe0_blk_len, NULL); 416 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 417 &sci_int, NULL); 418 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 419 &s->io_base, NULL); 420 } 421 422 static int piix4_pm_initfn(PCIDevice *dev) 423 { 424 PIIX4PMState *s = PIIX4_PM(dev); 425 uint8_t *pci_conf; 426 427 pci_conf = dev->config; 428 pci_conf[0x06] = 0x80; 429 pci_conf[0x07] = 0x02; 430 pci_conf[0x09] = 0x00; 431 pci_conf[0x3d] = 0x01; // interrupt pin 1 432 433 /* APM */ 434 apm_init(dev, &s->apm, apm_ctrl_changed, s); 435 436 if (s->kvm_enabled) { 437 /* Mark SMM as already inited to prevent SMM from running. KVM does not 438 * support SMM mode. */ 439 pci_conf[0x5B] = 0x02; 440 } 441 442 /* XXX: which specification is used ? The i82731AB has different 443 mappings */ 444 pci_conf[0x90] = s->smb_io_base | 1; 445 pci_conf[0x91] = s->smb_io_base >> 8; 446 pci_conf[0xd2] = 0x09; 447 pm_smbus_init(DEVICE(dev), &s->smb); 448 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 449 memory_region_add_subregion(pci_address_space_io(dev), 450 s->smb_io_base, &s->smb.io); 451 452 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 453 memory_region_set_enabled(&s->io, false); 454 memory_region_add_subregion(pci_address_space_io(dev), 455 0, &s->io); 456 457 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 458 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 459 acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val); 460 acpi_gpe_init(&s->ar, GPE_LEN); 461 462 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 463 qemu_register_powerdown_notifier(&s->powerdown_notifier); 464 465 s->machine_ready.notify = piix4_pm_machine_ready; 466 qemu_add_machine_init_done_notifier(&s->machine_ready); 467 qemu_register_reset(piix4_reset, s); 468 469 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s); 470 471 piix4_pm_add_propeties(s); 472 return 0; 473 } 474 475 Object *piix4_pm_find(void) 476 { 477 bool ambig; 478 Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig); 479 480 if (ambig || !o) { 481 return NULL; 482 } 483 return o; 484 } 485 486 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 487 qemu_irq sci_irq, qemu_irq smi_irq, 488 int kvm_enabled, FWCfgState *fw_cfg, 489 DeviceState **piix4_pm) 490 { 491 DeviceState *dev; 492 PIIX4PMState *s; 493 494 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); 495 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 496 if (piix4_pm) { 497 *piix4_pm = dev; 498 } 499 500 s = PIIX4_PM(dev); 501 s->irq = sci_irq; 502 s->smi_irq = smi_irq; 503 s->kvm_enabled = kvm_enabled; 504 505 qdev_init_nofail(dev); 506 507 if (fw_cfg) { 508 uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; 509 suspend[3] = 1 | ((!s->disable_s3) << 7); 510 suspend[4] = s->s4_val | ((!s->disable_s4) << 7); 511 512 fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); 513 } 514 515 return s->smb.smbus; 516 } 517 518 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 519 { 520 PIIX4PMState *s = opaque; 521 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 522 523 PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); 524 return val; 525 } 526 527 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 528 unsigned width) 529 { 530 PIIX4PMState *s = opaque; 531 532 acpi_gpe_ioport_writeb(&s->ar, addr, val); 533 acpi_update_sci(&s->ar, s->irq); 534 535 PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); 536 } 537 538 static const MemoryRegionOps piix4_gpe_ops = { 539 .read = gpe_readb, 540 .write = gpe_writeb, 541 .valid.min_access_size = 1, 542 .valid.max_access_size = 4, 543 .impl.min_access_size = 1, 544 .impl.max_access_size = 1, 545 .endianness = DEVICE_LITTLE_ENDIAN, 546 }; 547 548 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 549 PCIBus *bus, PIIX4PMState *s) 550 { 551 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 552 "acpi-gpe0", GPE_LEN); 553 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 554 555 acpi_pcihp_init(&s->acpi_pci_hotplug, bus, parent, 556 s->use_acpi_pci_hotplug); 557 558 acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, 559 PIIX4_CPU_HOTPLUG_IO_BASE); 560 561 if (s->acpi_memory_hotplug.is_enabled) { 562 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug); 563 } 564 } 565 566 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) 567 { 568 PIIX4PMState *s = PIIX4_PM(adev); 569 570 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); 571 } 572 573 static Property piix4_pm_properties[] = { 574 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 575 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 576 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 577 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 578 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, 579 use_acpi_pci_hotplug, true), 580 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, 581 acpi_memory_hotplug.is_enabled, true), 582 DEFINE_PROP_END_OF_LIST(), 583 }; 584 585 static void piix4_pm_class_init(ObjectClass *klass, void *data) 586 { 587 DeviceClass *dc = DEVICE_CLASS(klass); 588 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 589 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 590 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 591 592 k->init = piix4_pm_initfn; 593 k->config_write = pm_write_config; 594 k->vendor_id = PCI_VENDOR_ID_INTEL; 595 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 596 k->revision = 0x03; 597 k->class_id = PCI_CLASS_BRIDGE_OTHER; 598 dc->desc = "PM"; 599 dc->vmsd = &vmstate_acpi; 600 dc->props = piix4_pm_properties; 601 /* 602 * Reason: part of PIIX4 southbridge, needs to be wired up, 603 * e.g. by mips_malta_init() 604 */ 605 dc->cannot_instantiate_with_device_add_yet = true; 606 dc->hotpluggable = false; 607 hc->plug = piix4_device_plug_cb; 608 hc->unplug_request = piix4_device_unplug_request_cb; 609 adevc->ospm_status = piix4_ospm_status; 610 } 611 612 static const TypeInfo piix4_pm_info = { 613 .name = TYPE_PIIX4_PM, 614 .parent = TYPE_PCI_DEVICE, 615 .instance_size = sizeof(PIIX4PMState), 616 .class_init = piix4_pm_class_init, 617 .interfaces = (InterfaceInfo[]) { 618 { TYPE_HOTPLUG_HANDLER }, 619 { TYPE_ACPI_DEVICE_IF }, 620 { } 621 } 622 }; 623 624 static void piix4_pm_register_types(void) 625 { 626 type_register_static(&piix4_pm_info); 627 } 628 629 type_init(piix4_pm_register_types) 630