1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 #include "hw/hw.h" 22 #include "hw/i386/pc.h" 23 #include "hw/isa/apm.h" 24 #include "hw/i2c/pm_smbus.h" 25 #include "hw/pci/pci.h" 26 #include "hw/acpi/acpi.h" 27 #include "sysemu/sysemu.h" 28 #include "qemu/range.h" 29 #include "exec/ioport.h" 30 #include "hw/nvram/fw_cfg.h" 31 #include "exec/address-spaces.h" 32 33 //#define DEBUG 34 35 #ifdef DEBUG 36 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 37 #else 38 # define PIIX4_DPRINTF(format, ...) do { } while (0) 39 #endif 40 41 #define GPE_BASE 0xafe0 42 #define GPE_LEN 4 43 44 #define PCI_HOTPLUG_ADDR 0xae00 45 #define PCI_HOTPLUG_SIZE 0x000f 46 #define PCI_UP_BASE 0xae00 47 #define PCI_DOWN_BASE 0xae04 48 #define PCI_EJ_BASE 0xae08 49 #define PCI_RMV_BASE 0xae0c 50 51 #define PIIX4_PROC_BASE 0xaf00 52 #define PIIX4_PROC_LEN 32 53 54 #define PIIX4_PCI_HOTPLUG_STATUS 2 55 #define PIIX4_CPU_HOTPLUG_STATUS 4 56 57 struct pci_status { 58 uint32_t up; /* deprecated, maintained for migration compatibility */ 59 uint32_t down; 60 }; 61 62 typedef struct CPUStatus { 63 uint8_t sts[PIIX4_PROC_LEN]; 64 } CPUStatus; 65 66 typedef struct PIIX4PMState { 67 /*< private >*/ 68 PCIDevice parent_obj; 69 /*< public >*/ 70 71 MemoryRegion io; 72 MemoryRegion io_gpe; 73 MemoryRegion io_pci; 74 MemoryRegion io_cpu; 75 ACPIREGS ar; 76 77 APMState apm; 78 79 PMSMBus smb; 80 uint32_t smb_io_base; 81 82 qemu_irq irq; 83 qemu_irq smi_irq; 84 int kvm_enabled; 85 Notifier machine_ready; 86 Notifier powerdown_notifier; 87 88 /* for pci hotplug */ 89 struct pci_status pci0_status; 90 uint32_t pci0_hotplug_enable; 91 uint32_t pci0_slot_device_present; 92 93 uint8_t disable_s3; 94 uint8_t disable_s4; 95 uint8_t s4_val; 96 97 CPUStatus gpe_cpu; 98 Notifier cpu_added_notifier; 99 } PIIX4PMState; 100 101 #define TYPE_PIIX4_PM "PIIX4_PM" 102 103 #define PIIX4_PM(obj) \ 104 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) 105 106 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 107 PCIBus *bus, PIIX4PMState *s); 108 109 #define ACPI_ENABLE 0xf1 110 #define ACPI_DISABLE 0xf0 111 112 static void pm_update_sci(PIIX4PMState *s) 113 { 114 int sci_level, pmsts; 115 116 pmsts = acpi_pm1_evt_get_sts(&s->ar); 117 sci_level = (((pmsts & s->ar.pm1.evt.en) & 118 (ACPI_BITMASK_RT_CLOCK_ENABLE | 119 ACPI_BITMASK_POWER_BUTTON_ENABLE | 120 ACPI_BITMASK_GLOBAL_LOCK_ENABLE | 121 ACPI_BITMASK_TIMER_ENABLE)) != 0) || 122 (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) & 123 (PIIX4_PCI_HOTPLUG_STATUS | PIIX4_CPU_HOTPLUG_STATUS)) != 0); 124 125 qemu_set_irq(s->irq, sci_level); 126 /* schedule a timer interruption if needed */ 127 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && 128 !(pmsts & ACPI_BITMASK_TIMER_STATUS)); 129 } 130 131 static void pm_tmr_timer(ACPIREGS *ar) 132 { 133 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 134 pm_update_sci(s); 135 } 136 137 static void apm_ctrl_changed(uint32_t val, void *arg) 138 { 139 PIIX4PMState *s = arg; 140 PCIDevice *d = PCI_DEVICE(s); 141 142 /* ACPI specs 3.0, 4.7.2.5 */ 143 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 144 145 if (d->config[0x5b] & (1 << 1)) { 146 if (s->smi_irq) { 147 qemu_irq_raise(s->smi_irq); 148 } 149 } 150 } 151 152 static void pm_io_space_update(PIIX4PMState *s) 153 { 154 PCIDevice *d = PCI_DEVICE(s); 155 uint32_t pm_io_base; 156 157 pm_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 158 pm_io_base &= 0xffc0; 159 160 memory_region_transaction_begin(); 161 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 162 memory_region_set_address(&s->io, pm_io_base); 163 memory_region_transaction_commit(); 164 } 165 166 static void smbus_io_space_update(PIIX4PMState *s) 167 { 168 PCIDevice *d = PCI_DEVICE(s); 169 170 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 171 s->smb_io_base &= 0xffc0; 172 173 memory_region_transaction_begin(); 174 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 175 memory_region_set_address(&s->smb.io, s->smb_io_base); 176 memory_region_transaction_commit(); 177 } 178 179 static void pm_write_config(PCIDevice *d, 180 uint32_t address, uint32_t val, int len) 181 { 182 pci_default_write_config(d, address, val, len); 183 if (range_covers_byte(address, len, 0x80) || 184 ranges_overlap(address, len, 0x40, 4)) { 185 pm_io_space_update((PIIX4PMState *)d); 186 } 187 if (range_covers_byte(address, len, 0xd2) || 188 ranges_overlap(address, len, 0x90, 4)) { 189 smbus_io_space_update((PIIX4PMState *)d); 190 } 191 } 192 193 static void vmstate_pci_status_pre_save(void *opaque) 194 { 195 struct pci_status *pci0_status = opaque; 196 PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status); 197 198 /* We no longer track up, so build a safe value for migrating 199 * to a version that still does... of course these might get lost 200 * by an old buggy implementation, but we try. */ 201 pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable; 202 } 203 204 static int vmstate_acpi_post_load(void *opaque, int version_id) 205 { 206 PIIX4PMState *s = opaque; 207 208 pm_io_space_update(s); 209 return 0; 210 } 211 212 #define VMSTATE_GPE_ARRAY(_field, _state) \ 213 { \ 214 .name = (stringify(_field)), \ 215 .version_id = 0, \ 216 .info = &vmstate_info_uint16, \ 217 .size = sizeof(uint16_t), \ 218 .flags = VMS_SINGLE | VMS_POINTER, \ 219 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 220 } 221 222 static const VMStateDescription vmstate_gpe = { 223 .name = "gpe", 224 .version_id = 1, 225 .minimum_version_id = 1, 226 .minimum_version_id_old = 1, 227 .fields = (VMStateField []) { 228 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 229 VMSTATE_GPE_ARRAY(en, ACPIGPE), 230 VMSTATE_END_OF_LIST() 231 } 232 }; 233 234 static const VMStateDescription vmstate_pci_status = { 235 .name = "pci_status", 236 .version_id = 1, 237 .minimum_version_id = 1, 238 .minimum_version_id_old = 1, 239 .pre_save = vmstate_pci_status_pre_save, 240 .fields = (VMStateField []) { 241 VMSTATE_UINT32(up, struct pci_status), 242 VMSTATE_UINT32(down, struct pci_status), 243 VMSTATE_END_OF_LIST() 244 } 245 }; 246 247 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) 248 { 249 PIIX4PMState *s = opaque; 250 int ret, i; 251 uint16_t temp; 252 253 ret = pci_device_load(PCI_DEVICE(s), f); 254 if (ret < 0) { 255 return ret; 256 } 257 qemu_get_be16s(f, &s->ar.pm1.evt.sts); 258 qemu_get_be16s(f, &s->ar.pm1.evt.en); 259 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); 260 261 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); 262 if (ret) { 263 return ret; 264 } 265 266 timer_get(f, s->ar.tmr.timer); 267 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); 268 269 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); 270 for (i = 0; i < 3; i++) { 271 qemu_get_be16s(f, &temp); 272 } 273 274 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); 275 for (i = 0; i < 3; i++) { 276 qemu_get_be16s(f, &temp); 277 } 278 279 ret = vmstate_load_state(f, &vmstate_pci_status, &s->pci0_status, 1); 280 return ret; 281 } 282 283 /* qemu-kvm 1.2 uses version 3 but advertised as 2 284 * To support incoming qemu-kvm 1.2 migration, change version_id 285 * and minimum_version_id to 2 below (which breaks migration from 286 * qemu 1.2). 287 * 288 */ 289 static const VMStateDescription vmstate_acpi = { 290 .name = "piix4_pm", 291 .version_id = 3, 292 .minimum_version_id = 3, 293 .minimum_version_id_old = 1, 294 .load_state_old = acpi_load_old, 295 .post_load = vmstate_acpi_post_load, 296 .fields = (VMStateField []) { 297 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 298 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 299 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 300 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 301 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 302 VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), 303 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 304 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 305 VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status, 306 struct pci_status), 307 VMSTATE_END_OF_LIST() 308 } 309 }; 310 311 static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) 312 { 313 BusChild *kid, *next; 314 BusState *bus = qdev_get_parent_bus(DEVICE(s)); 315 int slot = ffs(slots) - 1; 316 bool slot_free = true; 317 318 /* Mark request as complete */ 319 s->pci0_status.down &= ~(1U << slot); 320 321 QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { 322 DeviceState *qdev = kid->child; 323 PCIDevice *dev = PCI_DEVICE(qdev); 324 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 325 if (PCI_SLOT(dev->devfn) == slot) { 326 if (pc->no_hotplug) { 327 slot_free = false; 328 } else { 329 qdev_free(qdev); 330 } 331 } 332 } 333 if (slot_free) { 334 s->pci0_slot_device_present &= ~(1U << slot); 335 } 336 } 337 338 static void piix4_update_hotplug(PIIX4PMState *s) 339 { 340 BusState *bus = qdev_get_parent_bus(DEVICE(s)); 341 BusChild *kid, *next; 342 343 /* Execute any pending removes during reset */ 344 while (s->pci0_status.down) { 345 acpi_piix_eject_slot(s, s->pci0_status.down); 346 } 347 348 s->pci0_hotplug_enable = ~0; 349 s->pci0_slot_device_present = 0; 350 351 QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { 352 DeviceState *qdev = kid->child; 353 PCIDevice *pdev = PCI_DEVICE(qdev); 354 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); 355 int slot = PCI_SLOT(pdev->devfn); 356 357 if (pc->no_hotplug) { 358 s->pci0_hotplug_enable &= ~(1U << slot); 359 } 360 361 s->pci0_slot_device_present |= (1U << slot); 362 } 363 } 364 365 static void piix4_reset(void *opaque) 366 { 367 PIIX4PMState *s = opaque; 368 PCIDevice *d = PCI_DEVICE(s); 369 uint8_t *pci_conf = d->config; 370 371 pci_conf[0x58] = 0; 372 pci_conf[0x59] = 0; 373 pci_conf[0x5a] = 0; 374 pci_conf[0x5b] = 0; 375 376 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 377 pci_conf[0x80] = 0; 378 379 if (s->kvm_enabled) { 380 /* Mark SMM as already inited (until KVM supports SMM). */ 381 pci_conf[0x5B] = 0x02; 382 } 383 pm_io_space_update(s); 384 piix4_update_hotplug(s); 385 } 386 387 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 388 { 389 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 390 391 assert(s != NULL); 392 acpi_pm1_evt_power_down(&s->ar); 393 } 394 395 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 396 { 397 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 398 PCIDevice *d = PCI_DEVICE(s); 399 MemoryRegion *io_as = pci_address_space_io(d); 400 uint8_t *pci_conf; 401 402 pci_conf = d->config; 403 pci_conf[0x5f] = 0x10 | 404 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 405 pci_conf[0x63] = 0x60; 406 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 407 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 408 } 409 410 static int piix4_pm_initfn(PCIDevice *dev) 411 { 412 PIIX4PMState *s = PIIX4_PM(dev); 413 uint8_t *pci_conf; 414 415 pci_conf = dev->config; 416 pci_conf[0x06] = 0x80; 417 pci_conf[0x07] = 0x02; 418 pci_conf[0x09] = 0x00; 419 pci_conf[0x3d] = 0x01; // interrupt pin 1 420 421 /* APM */ 422 apm_init(dev, &s->apm, apm_ctrl_changed, s); 423 424 if (s->kvm_enabled) { 425 /* Mark SMM as already inited to prevent SMM from running. KVM does not 426 * support SMM mode. */ 427 pci_conf[0x5B] = 0x02; 428 } 429 430 /* XXX: which specification is used ? The i82731AB has different 431 mappings */ 432 pci_conf[0x90] = s->smb_io_base | 1; 433 pci_conf[0x91] = s->smb_io_base >> 8; 434 pci_conf[0xd2] = 0x09; 435 pm_smbus_init(DEVICE(dev), &s->smb); 436 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 437 memory_region_add_subregion(pci_address_space_io(dev), 438 s->smb_io_base, &s->smb.io); 439 440 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 441 memory_region_set_enabled(&s->io, false); 442 memory_region_add_subregion(pci_address_space_io(dev), 443 0, &s->io); 444 445 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 446 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 447 acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val); 448 acpi_gpe_init(&s->ar, GPE_LEN); 449 450 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 451 qemu_register_powerdown_notifier(&s->powerdown_notifier); 452 453 s->machine_ready.notify = piix4_pm_machine_ready; 454 qemu_add_machine_init_done_notifier(&s->machine_ready); 455 qemu_register_reset(piix4_reset, s); 456 457 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s); 458 459 return 0; 460 } 461 462 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 463 qemu_irq sci_irq, qemu_irq smi_irq, 464 int kvm_enabled, FWCfgState *fw_cfg) 465 { 466 DeviceState *dev; 467 PIIX4PMState *s; 468 469 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); 470 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 471 472 s = PIIX4_PM(dev); 473 s->irq = sci_irq; 474 s->smi_irq = smi_irq; 475 s->kvm_enabled = kvm_enabled; 476 477 qdev_init_nofail(dev); 478 479 if (fw_cfg) { 480 uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; 481 suspend[3] = 1 | ((!s->disable_s3) << 7); 482 suspend[4] = s->s4_val | ((!s->disable_s4) << 7); 483 484 fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); 485 } 486 487 return s->smb.smbus; 488 } 489 490 static Property piix4_pm_properties[] = { 491 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 492 DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0), 493 DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0), 494 DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2), 495 DEFINE_PROP_END_OF_LIST(), 496 }; 497 498 static void piix4_pm_class_init(ObjectClass *klass, void *data) 499 { 500 DeviceClass *dc = DEVICE_CLASS(klass); 501 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 502 503 k->no_hotplug = 1; 504 k->init = piix4_pm_initfn; 505 k->config_write = pm_write_config; 506 k->vendor_id = PCI_VENDOR_ID_INTEL; 507 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 508 k->revision = 0x03; 509 k->class_id = PCI_CLASS_BRIDGE_OTHER; 510 dc->desc = "PM"; 511 dc->no_user = 1; 512 dc->vmsd = &vmstate_acpi; 513 dc->props = piix4_pm_properties; 514 } 515 516 static const TypeInfo piix4_pm_info = { 517 .name = TYPE_PIIX4_PM, 518 .parent = TYPE_PCI_DEVICE, 519 .instance_size = sizeof(PIIX4PMState), 520 .class_init = piix4_pm_class_init, 521 }; 522 523 static void piix4_pm_register_types(void) 524 { 525 type_register_static(&piix4_pm_info); 526 } 527 528 type_init(piix4_pm_register_types) 529 530 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 531 { 532 PIIX4PMState *s = opaque; 533 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 534 535 PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); 536 return val; 537 } 538 539 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 540 unsigned width) 541 { 542 PIIX4PMState *s = opaque; 543 544 acpi_gpe_ioport_writeb(&s->ar, addr, val); 545 pm_update_sci(s); 546 547 PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); 548 } 549 550 static const MemoryRegionOps piix4_gpe_ops = { 551 .read = gpe_readb, 552 .write = gpe_writeb, 553 .valid.min_access_size = 1, 554 .valid.max_access_size = 4, 555 .impl.min_access_size = 1, 556 .impl.max_access_size = 1, 557 .endianness = DEVICE_LITTLE_ENDIAN, 558 }; 559 560 static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) 561 { 562 PIIX4PMState *s = opaque; 563 uint32_t val = 0; 564 565 switch (addr) { 566 case PCI_UP_BASE - PCI_HOTPLUG_ADDR: 567 /* Manufacture an "up" value to cause a device check on any hotplug 568 * slot with a device. Extra device checks are harmless. */ 569 val = s->pci0_slot_device_present & s->pci0_hotplug_enable; 570 PIIX4_DPRINTF("pci_up_read %" PRIu32 "\n", val); 571 break; 572 case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR: 573 val = s->pci0_status.down; 574 PIIX4_DPRINTF("pci_down_read %" PRIu32 "\n", val); 575 break; 576 case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: 577 /* No feature defined yet */ 578 PIIX4_DPRINTF("pci_features_read %" PRIu32 "\n", val); 579 break; 580 case PCI_RMV_BASE - PCI_HOTPLUG_ADDR: 581 val = s->pci0_hotplug_enable; 582 break; 583 default: 584 break; 585 } 586 587 return val; 588 } 589 590 static void pci_write(void *opaque, hwaddr addr, uint64_t data, 591 unsigned int size) 592 { 593 switch (addr) { 594 case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: 595 acpi_piix_eject_slot(opaque, (uint32_t)data); 596 PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n", 597 addr, data); 598 break; 599 default: 600 break; 601 } 602 } 603 604 static const MemoryRegionOps piix4_pci_ops = { 605 .read = pci_read, 606 .write = pci_write, 607 .endianness = DEVICE_LITTLE_ENDIAN, 608 .valid = { 609 .min_access_size = 4, 610 .max_access_size = 4, 611 }, 612 }; 613 614 static uint64_t cpu_status_read(void *opaque, hwaddr addr, unsigned int size) 615 { 616 PIIX4PMState *s = opaque; 617 CPUStatus *cpus = &s->gpe_cpu; 618 uint64_t val = cpus->sts[addr]; 619 620 return val; 621 } 622 623 static void cpu_status_write(void *opaque, hwaddr addr, uint64_t data, 624 unsigned int size) 625 { 626 /* TODO: implement VCPU removal on guest signal that CPU can be removed */ 627 } 628 629 static const MemoryRegionOps cpu_hotplug_ops = { 630 .read = cpu_status_read, 631 .write = cpu_status_write, 632 .endianness = DEVICE_LITTLE_ENDIAN, 633 .valid = { 634 .min_access_size = 1, 635 .max_access_size = 1, 636 }, 637 }; 638 639 typedef enum { 640 PLUG, 641 UNPLUG, 642 } HotplugEventType; 643 644 static void piix4_cpu_hotplug_req(PIIX4PMState *s, CPUState *cpu, 645 HotplugEventType action) 646 { 647 CPUStatus *g = &s->gpe_cpu; 648 ACPIGPE *gpe = &s->ar.gpe; 649 CPUClass *k = CPU_GET_CLASS(cpu); 650 int64_t cpu_id; 651 652 assert(s != NULL); 653 654 *gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS; 655 cpu_id = k->get_arch_id(CPU(cpu)); 656 if (action == PLUG) { 657 g->sts[cpu_id / 8] |= (1 << (cpu_id % 8)); 658 } else { 659 g->sts[cpu_id / 8] &= ~(1 << (cpu_id % 8)); 660 } 661 pm_update_sci(s); 662 } 663 664 static void piix4_cpu_added_req(Notifier *n, void *opaque) 665 { 666 PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier); 667 668 piix4_cpu_hotplug_req(s, CPU(opaque), PLUG); 669 } 670 671 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, 672 PCIHotplugState state); 673 674 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 675 PCIBus *bus, PIIX4PMState *s) 676 { 677 CPUState *cpu; 678 679 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 680 "acpi-gpe0", GPE_LEN); 681 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 682 683 memory_region_init_io(&s->io_pci, OBJECT(s), &piix4_pci_ops, s, 684 "acpi-pci-hotplug", PCI_HOTPLUG_SIZE); 685 memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR, 686 &s->io_pci); 687 pci_bus_hotplug(bus, piix4_device_hotplug, DEVICE(s)); 688 689 CPU_FOREACH(cpu) { 690 CPUClass *cc = CPU_GET_CLASS(cpu); 691 int64_t id = cc->get_arch_id(cpu); 692 693 g_assert((id / 8) < PIIX4_PROC_LEN); 694 s->gpe_cpu.sts[id / 8] |= (1 << (id % 8)); 695 } 696 memory_region_init_io(&s->io_cpu, OBJECT(s), &cpu_hotplug_ops, s, 697 "acpi-cpu-hotplug", PIIX4_PROC_LEN); 698 memory_region_add_subregion(parent, PIIX4_PROC_BASE, &s->io_cpu); 699 s->cpu_added_notifier.notify = piix4_cpu_added_req; 700 qemu_register_cpu_added_notifier(&s->cpu_added_notifier); 701 } 702 703 static void enable_device(PIIX4PMState *s, int slot) 704 { 705 s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; 706 s->pci0_slot_device_present |= (1U << slot); 707 } 708 709 static void disable_device(PIIX4PMState *s, int slot) 710 { 711 s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; 712 s->pci0_status.down |= (1U << slot); 713 } 714 715 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, 716 PCIHotplugState state) 717 { 718 int slot = PCI_SLOT(dev->devfn); 719 PIIX4PMState *s = PIIX4_PM(qdev); 720 721 /* Don't send event when device is enabled during qemu machine creation: 722 * it is present on boot, no hotplug event is necessary. We do send an 723 * event when the device is disabled later. */ 724 if (state == PCI_COLDPLUG_ENABLED) { 725 s->pci0_slot_device_present |= (1U << slot); 726 return 0; 727 } 728 729 if (state == PCI_HOTPLUG_ENABLED) { 730 enable_device(s, slot); 731 } else { 732 disable_device(s, slot); 733 } 734 735 pm_update_sci(s); 736 737 return 0; 738 } 739