1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/i386/pc.h" 24 #include "hw/southbridge/piix.h" 25 #include "hw/irq.h" 26 #include "hw/isa/apm.h" 27 #include "hw/i2c/pm_smbus.h" 28 #include "hw/pci/pci.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/acpi/acpi.h" 31 #include "sysemu/runstate.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/xen.h" 34 #include "qapi/error.h" 35 #include "qemu/range.h" 36 #include "exec/address-spaces.h" 37 #include "hw/acpi/pcihp.h" 38 #include "hw/acpi/cpu_hotplug.h" 39 #include "hw/acpi/cpu.h" 40 #include "hw/hotplug.h" 41 #include "hw/mem/pc-dimm.h" 42 #include "hw/mem/nvdimm.h" 43 #include "hw/acpi/memory_hotplug.h" 44 #include "hw/acpi/acpi_dev_interface.h" 45 #include "migration/vmstate.h" 46 #include "hw/core/cpu.h" 47 #include "trace.h" 48 #include "qom/object.h" 49 50 #define GPE_BASE 0xafe0 51 #define GPE_LEN 4 52 53 struct pci_status { 54 uint32_t up; /* deprecated, maintained for migration compatibility */ 55 uint32_t down; 56 }; 57 58 struct PIIX4PMState { 59 /*< private >*/ 60 PCIDevice parent_obj; 61 /*< public >*/ 62 63 MemoryRegion io; 64 uint32_t io_base; 65 66 MemoryRegion io_gpe; 67 ACPIREGS ar; 68 69 APMState apm; 70 71 PMSMBus smb; 72 uint32_t smb_io_base; 73 74 qemu_irq irq; 75 qemu_irq smi_irq; 76 int smm_enabled; 77 Notifier machine_ready; 78 Notifier powerdown_notifier; 79 80 AcpiPciHpState acpi_pci_hotplug; 81 bool use_acpi_hotplug_bridge; 82 bool use_acpi_root_pci_hotplug; 83 84 uint8_t disable_s3; 85 uint8_t disable_s4; 86 uint8_t s4_val; 87 88 bool cpu_hotplug_legacy; 89 AcpiCpuHotplug gpe_cpu; 90 CPUHotplugState cpuhp_state; 91 92 MemHotplugState acpi_memory_hotplug; 93 }; 94 typedef struct PIIX4PMState PIIX4PMState; 95 96 DECLARE_INSTANCE_CHECKER(PIIX4PMState, PIIX4_PM, 97 TYPE_PIIX4_PM) 98 99 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 100 PCIBus *bus, PIIX4PMState *s); 101 102 #define ACPI_ENABLE 0xf1 103 #define ACPI_DISABLE 0xf0 104 105 static void pm_tmr_timer(ACPIREGS *ar) 106 { 107 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 108 acpi_update_sci(&s->ar, s->irq); 109 } 110 111 static void apm_ctrl_changed(uint32_t val, void *arg) 112 { 113 PIIX4PMState *s = arg; 114 PCIDevice *d = PCI_DEVICE(s); 115 116 /* ACPI specs 3.0, 4.7.2.5 */ 117 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 118 if (val == ACPI_ENABLE || val == ACPI_DISABLE) { 119 return; 120 } 121 122 if (d->config[0x5b] & (1 << 1)) { 123 if (s->smi_irq) { 124 qemu_irq_raise(s->smi_irq); 125 } 126 } 127 } 128 129 static void pm_io_space_update(PIIX4PMState *s) 130 { 131 PCIDevice *d = PCI_DEVICE(s); 132 133 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 134 s->io_base &= 0xffc0; 135 136 memory_region_transaction_begin(); 137 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 138 memory_region_set_address(&s->io, s->io_base); 139 memory_region_transaction_commit(); 140 } 141 142 static void smbus_io_space_update(PIIX4PMState *s) 143 { 144 PCIDevice *d = PCI_DEVICE(s); 145 146 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 147 s->smb_io_base &= 0xffc0; 148 149 memory_region_transaction_begin(); 150 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 151 memory_region_set_address(&s->smb.io, s->smb_io_base); 152 memory_region_transaction_commit(); 153 } 154 155 static void pm_write_config(PCIDevice *d, 156 uint32_t address, uint32_t val, int len) 157 { 158 pci_default_write_config(d, address, val, len); 159 if (range_covers_byte(address, len, 0x80) || 160 ranges_overlap(address, len, 0x40, 4)) { 161 pm_io_space_update((PIIX4PMState *)d); 162 } 163 if (range_covers_byte(address, len, 0xd2) || 164 ranges_overlap(address, len, 0x90, 4)) { 165 smbus_io_space_update((PIIX4PMState *)d); 166 } 167 } 168 169 static int vmstate_acpi_post_load(void *opaque, int version_id) 170 { 171 PIIX4PMState *s = opaque; 172 173 pm_io_space_update(s); 174 smbus_io_space_update(s); 175 return 0; 176 } 177 178 #define VMSTATE_GPE_ARRAY(_field, _state) \ 179 { \ 180 .name = (stringify(_field)), \ 181 .version_id = 0, \ 182 .info = &vmstate_info_uint16, \ 183 .size = sizeof(uint16_t), \ 184 .flags = VMS_SINGLE | VMS_POINTER, \ 185 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 186 } 187 188 static const VMStateDescription vmstate_gpe = { 189 .name = "gpe", 190 .version_id = 1, 191 .minimum_version_id = 1, 192 .fields = (VMStateField[]) { 193 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 194 VMSTATE_GPE_ARRAY(en, ACPIGPE), 195 VMSTATE_END_OF_LIST() 196 } 197 }; 198 199 static const VMStateDescription vmstate_pci_status = { 200 .name = "pci_status", 201 .version_id = 1, 202 .minimum_version_id = 1, 203 .fields = (VMStateField[]) { 204 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), 205 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), 206 VMSTATE_END_OF_LIST() 207 } 208 }; 209 210 static bool vmstate_test_use_acpi_hotplug_bridge(void *opaque, int version_id) 211 { 212 PIIX4PMState *s = opaque; 213 return s->use_acpi_hotplug_bridge; 214 } 215 216 static bool vmstate_test_no_use_acpi_hotplug_bridge(void *opaque, 217 int version_id) 218 { 219 PIIX4PMState *s = opaque; 220 return !s->use_acpi_hotplug_bridge; 221 } 222 223 static bool vmstate_test_use_memhp(void *opaque) 224 { 225 PIIX4PMState *s = opaque; 226 return s->acpi_memory_hotplug.is_enabled; 227 } 228 229 static const VMStateDescription vmstate_memhp_state = { 230 .name = "piix4_pm/memhp", 231 .version_id = 1, 232 .minimum_version_id = 1, 233 .minimum_version_id_old = 1, 234 .needed = vmstate_test_use_memhp, 235 .fields = (VMStateField[]) { 236 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), 237 VMSTATE_END_OF_LIST() 238 } 239 }; 240 241 static bool vmstate_test_use_cpuhp(void *opaque) 242 { 243 PIIX4PMState *s = opaque; 244 return !s->cpu_hotplug_legacy; 245 } 246 247 static int vmstate_cpuhp_pre_load(void *opaque) 248 { 249 Object *obj = OBJECT(opaque); 250 object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort); 251 return 0; 252 } 253 254 static const VMStateDescription vmstate_cpuhp_state = { 255 .name = "piix4_pm/cpuhp", 256 .version_id = 1, 257 .minimum_version_id = 1, 258 .minimum_version_id_old = 1, 259 .needed = vmstate_test_use_cpuhp, 260 .pre_load = vmstate_cpuhp_pre_load, 261 .fields = (VMStateField[]) { 262 VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), 263 VMSTATE_END_OF_LIST() 264 } 265 }; 266 267 static bool piix4_vmstate_need_smbus(void *opaque, int version_id) 268 { 269 return pm_smbus_vmstate_needed(); 270 } 271 272 /* qemu-kvm 1.2 uses version 3 but advertised as 2 273 * To support incoming qemu-kvm 1.2 migration, change version_id 274 * and minimum_version_id to 2 below (which breaks migration from 275 * qemu 1.2). 276 * 277 */ 278 static const VMStateDescription vmstate_acpi = { 279 .name = "piix4_pm", 280 .version_id = 3, 281 .minimum_version_id = 3, 282 .post_load = vmstate_acpi_post_load, 283 .fields = (VMStateField[]) { 284 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 285 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 286 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 287 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 288 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 289 VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3, 290 pmsmb_vmstate, PMSMBus), 291 VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), 292 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 293 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 294 VMSTATE_STRUCT_TEST( 295 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 296 PIIX4PMState, 297 vmstate_test_no_use_acpi_hotplug_bridge, 298 2, vmstate_pci_status, 299 struct AcpiPciHpPciStatus), 300 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 301 vmstate_test_use_acpi_hotplug_bridge), 302 VMSTATE_END_OF_LIST() 303 }, 304 .subsections = (const VMStateDescription*[]) { 305 &vmstate_memhp_state, 306 &vmstate_cpuhp_state, 307 NULL 308 } 309 }; 310 311 static void piix4_pm_reset(DeviceState *dev) 312 { 313 PIIX4PMState *s = PIIX4_PM(dev); 314 PCIDevice *d = PCI_DEVICE(s); 315 uint8_t *pci_conf = d->config; 316 317 pci_conf[0x58] = 0; 318 pci_conf[0x59] = 0; 319 pci_conf[0x5a] = 0; 320 pci_conf[0x5b] = 0; 321 322 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 323 pci_conf[0x80] = 0; 324 325 if (!s->smm_enabled) { 326 /* Mark SMM as already inited (until KVM supports SMM). */ 327 pci_conf[0x5B] = 0x02; 328 } 329 pm_io_space_update(s); 330 acpi_pcihp_reset(&s->acpi_pci_hotplug, !s->use_acpi_root_pci_hotplug); 331 } 332 333 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 334 { 335 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 336 337 assert(s != NULL); 338 acpi_pm1_evt_power_down(&s->ar); 339 } 340 341 static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev, 342 DeviceState *dev, Error **errp) 343 { 344 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 345 346 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 347 acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp); 348 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 349 if (!s->acpi_memory_hotplug.is_enabled) { 350 error_setg(errp, 351 "memory hotplug is not enabled: %s.memory-hotplug-support " 352 "is not set", object_get_typename(OBJECT(s))); 353 } 354 } else if ( 355 !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 356 error_setg(errp, "acpi: device pre plug request for not supported" 357 " device type: %s", object_get_typename(OBJECT(dev))); 358 } 359 } 360 361 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, 362 DeviceState *dev, Error **errp) 363 { 364 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 365 366 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 367 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 368 nvdimm_acpi_plug_cb(hotplug_dev, dev); 369 } else { 370 acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug, 371 dev, errp); 372 } 373 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 374 acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); 375 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 376 if (s->cpu_hotplug_legacy) { 377 legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp); 378 } else { 379 acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 380 } 381 } else { 382 g_assert_not_reached(); 383 } 384 } 385 386 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, 387 DeviceState *dev, Error **errp) 388 { 389 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 390 391 if (s->acpi_memory_hotplug.is_enabled && 392 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 393 acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug, 394 dev, errp); 395 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 396 acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug, 397 dev, errp); 398 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 399 !s->cpu_hotplug_legacy) { 400 acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 401 } else { 402 error_setg(errp, "acpi: device unplug request for not supported device" 403 " type: %s", object_get_typename(OBJECT(dev))); 404 } 405 } 406 407 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, 408 DeviceState *dev, Error **errp) 409 { 410 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 411 412 if (s->acpi_memory_hotplug.is_enabled && 413 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 414 acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); 415 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 416 acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, 417 errp); 418 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 419 !s->cpu_hotplug_legacy) { 420 acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); 421 } else { 422 error_setg(errp, "acpi: device unplug for not supported device" 423 " type: %s", object_get_typename(OBJECT(dev))); 424 } 425 } 426 427 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 428 { 429 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 430 PCIDevice *d = PCI_DEVICE(s); 431 MemoryRegion *io_as = pci_address_space_io(d); 432 uint8_t *pci_conf; 433 434 pci_conf = d->config; 435 pci_conf[0x5f] = 0x10 | 436 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 437 pci_conf[0x63] = 0x60; 438 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 439 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 440 } 441 442 static void piix4_pm_add_propeties(PIIX4PMState *s) 443 { 444 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 445 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 446 static const uint32_t gpe0_blk = GPE_BASE; 447 static const uint32_t gpe0_blk_len = GPE_LEN; 448 static const uint16_t sci_int = 9; 449 450 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 451 &acpi_enable_cmd, OBJ_PROP_FLAG_READ); 452 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 453 &acpi_disable_cmd, OBJ_PROP_FLAG_READ); 454 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 455 &gpe0_blk, OBJ_PROP_FLAG_READ); 456 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 457 &gpe0_blk_len, OBJ_PROP_FLAG_READ); 458 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 459 &sci_int, OBJ_PROP_FLAG_READ); 460 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 461 &s->io_base, OBJ_PROP_FLAG_READ); 462 } 463 464 static void piix4_pm_realize(PCIDevice *dev, Error **errp) 465 { 466 PIIX4PMState *s = PIIX4_PM(dev); 467 uint8_t *pci_conf; 468 469 pci_conf = dev->config; 470 pci_conf[0x06] = 0x80; 471 pci_conf[0x07] = 0x02; 472 pci_conf[0x09] = 0x00; 473 pci_conf[0x3d] = 0x01; // interrupt pin 1 474 475 /* APM */ 476 apm_init(dev, &s->apm, apm_ctrl_changed, s); 477 478 if (!s->smm_enabled) { 479 /* Mark SMM as already inited to prevent SMM from running. KVM does not 480 * support SMM mode. */ 481 pci_conf[0x5B] = 0x02; 482 } 483 484 /* XXX: which specification is used ? The i82731AB has different 485 mappings */ 486 pci_conf[0x90] = s->smb_io_base | 1; 487 pci_conf[0x91] = s->smb_io_base >> 8; 488 pci_conf[0xd2] = 0x09; 489 pm_smbus_init(DEVICE(dev), &s->smb, true); 490 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 491 memory_region_add_subregion(pci_address_space_io(dev), 492 s->smb_io_base, &s->smb.io); 493 494 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 495 memory_region_set_enabled(&s->io, false); 496 memory_region_add_subregion(pci_address_space_io(dev), 497 0, &s->io); 498 499 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 500 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 501 acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val); 502 acpi_gpe_init(&s->ar, GPE_LEN); 503 504 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 505 qemu_register_powerdown_notifier(&s->powerdown_notifier); 506 507 s->machine_ready.notify = piix4_pm_machine_ready; 508 qemu_add_machine_init_done_notifier(&s->machine_ready); 509 510 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), 511 pci_get_bus(dev), s); 512 qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s)); 513 514 piix4_pm_add_propeties(s); 515 } 516 517 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 518 qemu_irq sci_irq, qemu_irq smi_irq, 519 int smm_enabled, DeviceState **piix4_pm) 520 { 521 PCIDevice *pci_dev; 522 DeviceState *dev; 523 PIIX4PMState *s; 524 525 pci_dev = pci_new(devfn, TYPE_PIIX4_PM); 526 dev = DEVICE(pci_dev); 527 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 528 if (piix4_pm) { 529 *piix4_pm = dev; 530 } 531 532 s = PIIX4_PM(dev); 533 s->irq = sci_irq; 534 s->smi_irq = smi_irq; 535 s->smm_enabled = smm_enabled; 536 if (xen_enabled()) { 537 s->use_acpi_hotplug_bridge = false; 538 } 539 540 pci_realize_and_unref(pci_dev, bus, &error_fatal); 541 542 return s->smb.smbus; 543 } 544 545 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 546 { 547 PIIX4PMState *s = opaque; 548 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 549 550 trace_piix4_gpe_readb(addr, width, val); 551 return val; 552 } 553 554 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 555 unsigned width) 556 { 557 PIIX4PMState *s = opaque; 558 559 trace_piix4_gpe_writeb(addr, width, val); 560 acpi_gpe_ioport_writeb(&s->ar, addr, val); 561 acpi_update_sci(&s->ar, s->irq); 562 } 563 564 static const MemoryRegionOps piix4_gpe_ops = { 565 .read = gpe_readb, 566 .write = gpe_writeb, 567 .valid.min_access_size = 1, 568 .valid.max_access_size = 4, 569 .impl.min_access_size = 1, 570 .impl.max_access_size = 1, 571 .endianness = DEVICE_LITTLE_ENDIAN, 572 }; 573 574 575 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp) 576 { 577 PIIX4PMState *s = PIIX4_PM(obj); 578 579 return s->cpu_hotplug_legacy; 580 } 581 582 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp) 583 { 584 PIIX4PMState *s = PIIX4_PM(obj); 585 586 assert(!value); 587 if (s->cpu_hotplug_legacy && value == false) { 588 acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state, 589 PIIX4_CPU_HOTPLUG_IO_BASE); 590 } 591 s->cpu_hotplug_legacy = value; 592 } 593 594 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 595 PCIBus *bus, PIIX4PMState *s) 596 { 597 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 598 "acpi-gpe0", GPE_LEN); 599 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 600 601 acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, 602 s->use_acpi_hotplug_bridge); 603 604 s->cpu_hotplug_legacy = true; 605 object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", 606 piix4_get_cpu_hotplug_legacy, 607 piix4_set_cpu_hotplug_legacy); 608 legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, 609 PIIX4_CPU_HOTPLUG_IO_BASE); 610 611 if (s->acpi_memory_hotplug.is_enabled) { 612 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug, 613 ACPI_MEMORY_HOTPLUG_BASE); 614 } 615 } 616 617 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) 618 { 619 PIIX4PMState *s = PIIX4_PM(adev); 620 621 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); 622 if (!s->cpu_hotplug_legacy) { 623 acpi_cpu_ospm_status(&s->cpuhp_state, list); 624 } 625 } 626 627 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 628 { 629 PIIX4PMState *s = PIIX4_PM(adev); 630 631 acpi_send_gpe_event(&s->ar, s->irq, ev); 632 } 633 634 static Property piix4_pm_properties[] = { 635 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 636 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 637 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 638 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 639 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, 640 use_acpi_hotplug_bridge, true), 641 DEFINE_PROP_BOOL("acpi-root-pci-hotplug", PIIX4PMState, 642 use_acpi_root_pci_hotplug, true), 643 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, 644 acpi_memory_hotplug.is_enabled, true), 645 DEFINE_PROP_END_OF_LIST(), 646 }; 647 648 static void piix4_pm_class_init(ObjectClass *klass, void *data) 649 { 650 DeviceClass *dc = DEVICE_CLASS(klass); 651 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 652 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 653 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 654 655 k->realize = piix4_pm_realize; 656 k->config_write = pm_write_config; 657 k->vendor_id = PCI_VENDOR_ID_INTEL; 658 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 659 k->revision = 0x03; 660 k->class_id = PCI_CLASS_BRIDGE_OTHER; 661 dc->reset = piix4_pm_reset; 662 dc->desc = "PM"; 663 dc->vmsd = &vmstate_acpi; 664 device_class_set_props(dc, piix4_pm_properties); 665 /* 666 * Reason: part of PIIX4 southbridge, needs to be wired up, 667 * e.g. by mips_malta_init() 668 */ 669 dc->user_creatable = false; 670 dc->hotpluggable = false; 671 hc->pre_plug = piix4_device_pre_plug_cb; 672 hc->plug = piix4_device_plug_cb; 673 hc->unplug_request = piix4_device_unplug_request_cb; 674 hc->unplug = piix4_device_unplug_cb; 675 adevc->ospm_status = piix4_ospm_status; 676 adevc->send_event = piix4_send_gpe; 677 adevc->madt_cpu = pc_madt_cpu_entry; 678 } 679 680 static const TypeInfo piix4_pm_info = { 681 .name = TYPE_PIIX4_PM, 682 .parent = TYPE_PCI_DEVICE, 683 .instance_size = sizeof(PIIX4PMState), 684 .class_init = piix4_pm_class_init, 685 .interfaces = (InterfaceInfo[]) { 686 { TYPE_HOTPLUG_HANDLER }, 687 { TYPE_ACPI_DEVICE_IF }, 688 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 689 { } 690 } 691 }; 692 693 static void piix4_pm_register_types(void) 694 { 695 type_register_static(&piix4_pm_info); 696 } 697 698 type_init(piix4_pm_register_types) 699