1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/i386/pc.h" 24 #include "hw/southbridge/piix.h" 25 #include "hw/irq.h" 26 #include "hw/isa/apm.h" 27 #include "hw/i2c/pm_smbus.h" 28 #include "hw/pci/pci.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/acpi/acpi.h" 31 #include "sysemu/runstate.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/xen.h" 34 #include "qapi/error.h" 35 #include "qemu/range.h" 36 #include "exec/address-spaces.h" 37 #include "hw/acpi/pcihp.h" 38 #include "hw/acpi/cpu_hotplug.h" 39 #include "hw/acpi/cpu.h" 40 #include "hw/hotplug.h" 41 #include "hw/mem/pc-dimm.h" 42 #include "hw/mem/nvdimm.h" 43 #include "hw/acpi/memory_hotplug.h" 44 #include "hw/acpi/acpi_dev_interface.h" 45 #include "migration/vmstate.h" 46 #include "hw/core/cpu.h" 47 #include "trace.h" 48 49 #define GPE_BASE 0xafe0 50 #define GPE_LEN 4 51 52 struct pci_status { 53 uint32_t up; /* deprecated, maintained for migration compatibility */ 54 uint32_t down; 55 }; 56 57 typedef struct PIIX4PMState { 58 /*< private >*/ 59 PCIDevice parent_obj; 60 /*< public >*/ 61 62 MemoryRegion io; 63 uint32_t io_base; 64 65 MemoryRegion io_gpe; 66 ACPIREGS ar; 67 68 APMState apm; 69 70 PMSMBus smb; 71 uint32_t smb_io_base; 72 73 qemu_irq irq; 74 qemu_irq smi_irq; 75 int smm_enabled; 76 Notifier machine_ready; 77 Notifier powerdown_notifier; 78 79 AcpiPciHpState acpi_pci_hotplug; 80 bool use_acpi_hotplug_bridge; 81 82 uint8_t disable_s3; 83 uint8_t disable_s4; 84 uint8_t s4_val; 85 86 bool cpu_hotplug_legacy; 87 AcpiCpuHotplug gpe_cpu; 88 CPUHotplugState cpuhp_state; 89 90 MemHotplugState acpi_memory_hotplug; 91 } PIIX4PMState; 92 93 #define PIIX4_PM(obj) \ 94 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) 95 96 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 97 PCIBus *bus, PIIX4PMState *s); 98 99 #define ACPI_ENABLE 0xf1 100 #define ACPI_DISABLE 0xf0 101 102 static void pm_tmr_timer(ACPIREGS *ar) 103 { 104 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 105 acpi_update_sci(&s->ar, s->irq); 106 } 107 108 static void apm_ctrl_changed(uint32_t val, void *arg) 109 { 110 PIIX4PMState *s = arg; 111 PCIDevice *d = PCI_DEVICE(s); 112 113 /* ACPI specs 3.0, 4.7.2.5 */ 114 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 115 if (val == ACPI_ENABLE || val == ACPI_DISABLE) { 116 return; 117 } 118 119 if (d->config[0x5b] & (1 << 1)) { 120 if (s->smi_irq) { 121 qemu_irq_raise(s->smi_irq); 122 } 123 } 124 } 125 126 static void pm_io_space_update(PIIX4PMState *s) 127 { 128 PCIDevice *d = PCI_DEVICE(s); 129 130 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 131 s->io_base &= 0xffc0; 132 133 memory_region_transaction_begin(); 134 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 135 memory_region_set_address(&s->io, s->io_base); 136 memory_region_transaction_commit(); 137 } 138 139 static void smbus_io_space_update(PIIX4PMState *s) 140 { 141 PCIDevice *d = PCI_DEVICE(s); 142 143 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 144 s->smb_io_base &= 0xffc0; 145 146 memory_region_transaction_begin(); 147 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 148 memory_region_set_address(&s->smb.io, s->smb_io_base); 149 memory_region_transaction_commit(); 150 } 151 152 static void pm_write_config(PCIDevice *d, 153 uint32_t address, uint32_t val, int len) 154 { 155 pci_default_write_config(d, address, val, len); 156 if (range_covers_byte(address, len, 0x80) || 157 ranges_overlap(address, len, 0x40, 4)) { 158 pm_io_space_update((PIIX4PMState *)d); 159 } 160 if (range_covers_byte(address, len, 0xd2) || 161 ranges_overlap(address, len, 0x90, 4)) { 162 smbus_io_space_update((PIIX4PMState *)d); 163 } 164 } 165 166 static int vmstate_acpi_post_load(void *opaque, int version_id) 167 { 168 PIIX4PMState *s = opaque; 169 170 pm_io_space_update(s); 171 smbus_io_space_update(s); 172 return 0; 173 } 174 175 #define VMSTATE_GPE_ARRAY(_field, _state) \ 176 { \ 177 .name = (stringify(_field)), \ 178 .version_id = 0, \ 179 .info = &vmstate_info_uint16, \ 180 .size = sizeof(uint16_t), \ 181 .flags = VMS_SINGLE | VMS_POINTER, \ 182 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 183 } 184 185 static const VMStateDescription vmstate_gpe = { 186 .name = "gpe", 187 .version_id = 1, 188 .minimum_version_id = 1, 189 .fields = (VMStateField[]) { 190 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 191 VMSTATE_GPE_ARRAY(en, ACPIGPE), 192 VMSTATE_END_OF_LIST() 193 } 194 }; 195 196 static const VMStateDescription vmstate_pci_status = { 197 .name = "pci_status", 198 .version_id = 1, 199 .minimum_version_id = 1, 200 .fields = (VMStateField[]) { 201 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), 202 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), 203 VMSTATE_END_OF_LIST() 204 } 205 }; 206 207 static bool vmstate_test_use_acpi_hotplug_bridge(void *opaque, int version_id) 208 { 209 PIIX4PMState *s = opaque; 210 return s->use_acpi_hotplug_bridge; 211 } 212 213 static bool vmstate_test_no_use_acpi_hotplug_bridge(void *opaque, 214 int version_id) 215 { 216 PIIX4PMState *s = opaque; 217 return !s->use_acpi_hotplug_bridge; 218 } 219 220 static bool vmstate_test_use_memhp(void *opaque) 221 { 222 PIIX4PMState *s = opaque; 223 return s->acpi_memory_hotplug.is_enabled; 224 } 225 226 static const VMStateDescription vmstate_memhp_state = { 227 .name = "piix4_pm/memhp", 228 .version_id = 1, 229 .minimum_version_id = 1, 230 .minimum_version_id_old = 1, 231 .needed = vmstate_test_use_memhp, 232 .fields = (VMStateField[]) { 233 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), 234 VMSTATE_END_OF_LIST() 235 } 236 }; 237 238 static bool vmstate_test_use_cpuhp(void *opaque) 239 { 240 PIIX4PMState *s = opaque; 241 return !s->cpu_hotplug_legacy; 242 } 243 244 static int vmstate_cpuhp_pre_load(void *opaque) 245 { 246 Object *obj = OBJECT(opaque); 247 object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort); 248 return 0; 249 } 250 251 static const VMStateDescription vmstate_cpuhp_state = { 252 .name = "piix4_pm/cpuhp", 253 .version_id = 1, 254 .minimum_version_id = 1, 255 .minimum_version_id_old = 1, 256 .needed = vmstate_test_use_cpuhp, 257 .pre_load = vmstate_cpuhp_pre_load, 258 .fields = (VMStateField[]) { 259 VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), 260 VMSTATE_END_OF_LIST() 261 } 262 }; 263 264 static bool piix4_vmstate_need_smbus(void *opaque, int version_id) 265 { 266 return pm_smbus_vmstate_needed(); 267 } 268 269 /* qemu-kvm 1.2 uses version 3 but advertised as 2 270 * To support incoming qemu-kvm 1.2 migration, change version_id 271 * and minimum_version_id to 2 below (which breaks migration from 272 * qemu 1.2). 273 * 274 */ 275 static const VMStateDescription vmstate_acpi = { 276 .name = "piix4_pm", 277 .version_id = 3, 278 .minimum_version_id = 3, 279 .post_load = vmstate_acpi_post_load, 280 .fields = (VMStateField[]) { 281 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 282 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 283 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 284 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 285 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 286 VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3, 287 pmsmb_vmstate, PMSMBus), 288 VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), 289 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 290 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 291 VMSTATE_STRUCT_TEST( 292 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 293 PIIX4PMState, 294 vmstate_test_no_use_acpi_hotplug_bridge, 295 2, vmstate_pci_status, 296 struct AcpiPciHpPciStatus), 297 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 298 vmstate_test_use_acpi_hotplug_bridge), 299 VMSTATE_END_OF_LIST() 300 }, 301 .subsections = (const VMStateDescription*[]) { 302 &vmstate_memhp_state, 303 &vmstate_cpuhp_state, 304 NULL 305 } 306 }; 307 308 static void piix4_pm_reset(DeviceState *dev) 309 { 310 PIIX4PMState *s = PIIX4_PM(dev); 311 PCIDevice *d = PCI_DEVICE(s); 312 uint8_t *pci_conf = d->config; 313 314 pci_conf[0x58] = 0; 315 pci_conf[0x59] = 0; 316 pci_conf[0x5a] = 0; 317 pci_conf[0x5b] = 0; 318 319 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 320 pci_conf[0x80] = 0; 321 322 if (!s->smm_enabled) { 323 /* Mark SMM as already inited (until KVM supports SMM). */ 324 pci_conf[0x5B] = 0x02; 325 } 326 pm_io_space_update(s); 327 acpi_pcihp_reset(&s->acpi_pci_hotplug); 328 } 329 330 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 331 { 332 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 333 334 assert(s != NULL); 335 acpi_pm1_evt_power_down(&s->ar); 336 } 337 338 static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev, 339 DeviceState *dev, Error **errp) 340 { 341 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 342 343 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 344 acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp); 345 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 346 if (!s->acpi_memory_hotplug.is_enabled) { 347 error_setg(errp, 348 "memory hotplug is not enabled: %s.memory-hotplug-support " 349 "is not set", object_get_typename(OBJECT(s))); 350 } 351 } else if ( 352 !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 353 error_setg(errp, "acpi: device pre plug request for not supported" 354 " device type: %s", object_get_typename(OBJECT(dev))); 355 } 356 } 357 358 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, 359 DeviceState *dev, Error **errp) 360 { 361 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 362 363 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 364 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 365 nvdimm_acpi_plug_cb(hotplug_dev, dev); 366 } else { 367 acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug, 368 dev, errp); 369 } 370 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 371 acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); 372 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 373 if (s->cpu_hotplug_legacy) { 374 legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp); 375 } else { 376 acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 377 } 378 } else { 379 g_assert_not_reached(); 380 } 381 } 382 383 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, 384 DeviceState *dev, Error **errp) 385 { 386 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 387 388 if (s->acpi_memory_hotplug.is_enabled && 389 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 390 acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug, 391 dev, errp); 392 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 393 acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug, 394 dev, errp); 395 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 396 !s->cpu_hotplug_legacy) { 397 acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 398 } else { 399 error_setg(errp, "acpi: device unplug request for not supported device" 400 " type: %s", object_get_typename(OBJECT(dev))); 401 } 402 } 403 404 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, 405 DeviceState *dev, Error **errp) 406 { 407 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 408 409 if (s->acpi_memory_hotplug.is_enabled && 410 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 411 acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); 412 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 413 acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, 414 errp); 415 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 416 !s->cpu_hotplug_legacy) { 417 acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); 418 } else { 419 error_setg(errp, "acpi: device unplug for not supported device" 420 " type: %s", object_get_typename(OBJECT(dev))); 421 } 422 } 423 424 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 425 { 426 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 427 PCIDevice *d = PCI_DEVICE(s); 428 MemoryRegion *io_as = pci_address_space_io(d); 429 uint8_t *pci_conf; 430 431 pci_conf = d->config; 432 pci_conf[0x5f] = 0x10 | 433 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 434 pci_conf[0x63] = 0x60; 435 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 436 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 437 } 438 439 static void piix4_pm_add_propeties(PIIX4PMState *s) 440 { 441 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 442 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 443 static const uint32_t gpe0_blk = GPE_BASE; 444 static const uint32_t gpe0_blk_len = GPE_LEN; 445 static const uint16_t sci_int = 9; 446 447 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 448 &acpi_enable_cmd, OBJ_PROP_FLAG_READ); 449 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 450 &acpi_disable_cmd, OBJ_PROP_FLAG_READ); 451 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 452 &gpe0_blk, OBJ_PROP_FLAG_READ); 453 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 454 &gpe0_blk_len, OBJ_PROP_FLAG_READ); 455 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 456 &sci_int, OBJ_PROP_FLAG_READ); 457 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 458 &s->io_base, OBJ_PROP_FLAG_READ); 459 } 460 461 static void piix4_pm_realize(PCIDevice *dev, Error **errp) 462 { 463 PIIX4PMState *s = PIIX4_PM(dev); 464 uint8_t *pci_conf; 465 466 pci_conf = dev->config; 467 pci_conf[0x06] = 0x80; 468 pci_conf[0x07] = 0x02; 469 pci_conf[0x09] = 0x00; 470 pci_conf[0x3d] = 0x01; // interrupt pin 1 471 472 /* APM */ 473 apm_init(dev, &s->apm, apm_ctrl_changed, s); 474 475 if (!s->smm_enabled) { 476 /* Mark SMM as already inited to prevent SMM from running. KVM does not 477 * support SMM mode. */ 478 pci_conf[0x5B] = 0x02; 479 } 480 481 /* XXX: which specification is used ? The i82731AB has different 482 mappings */ 483 pci_conf[0x90] = s->smb_io_base | 1; 484 pci_conf[0x91] = s->smb_io_base >> 8; 485 pci_conf[0xd2] = 0x09; 486 pm_smbus_init(DEVICE(dev), &s->smb, true); 487 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 488 memory_region_add_subregion(pci_address_space_io(dev), 489 s->smb_io_base, &s->smb.io); 490 491 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 492 memory_region_set_enabled(&s->io, false); 493 memory_region_add_subregion(pci_address_space_io(dev), 494 0, &s->io); 495 496 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 497 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 498 acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val); 499 acpi_gpe_init(&s->ar, GPE_LEN); 500 501 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 502 qemu_register_powerdown_notifier(&s->powerdown_notifier); 503 504 s->machine_ready.notify = piix4_pm_machine_ready; 505 qemu_add_machine_init_done_notifier(&s->machine_ready); 506 507 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), 508 pci_get_bus(dev), s); 509 qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s)); 510 511 piix4_pm_add_propeties(s); 512 } 513 514 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 515 qemu_irq sci_irq, qemu_irq smi_irq, 516 int smm_enabled, DeviceState **piix4_pm) 517 { 518 PCIDevice *pci_dev; 519 DeviceState *dev; 520 PIIX4PMState *s; 521 522 pci_dev = pci_new(devfn, TYPE_PIIX4_PM); 523 dev = DEVICE(pci_dev); 524 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 525 if (piix4_pm) { 526 *piix4_pm = dev; 527 } 528 529 s = PIIX4_PM(dev); 530 s->irq = sci_irq; 531 s->smi_irq = smi_irq; 532 s->smm_enabled = smm_enabled; 533 if (xen_enabled()) { 534 s->use_acpi_hotplug_bridge = false; 535 } 536 537 pci_realize_and_unref(pci_dev, bus, &error_fatal); 538 539 return s->smb.smbus; 540 } 541 542 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 543 { 544 PIIX4PMState *s = opaque; 545 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 546 547 trace_piix4_gpe_readb(addr, width, val); 548 return val; 549 } 550 551 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 552 unsigned width) 553 { 554 PIIX4PMState *s = opaque; 555 556 trace_piix4_gpe_writeb(addr, width, val); 557 acpi_gpe_ioport_writeb(&s->ar, addr, val); 558 acpi_update_sci(&s->ar, s->irq); 559 } 560 561 static const MemoryRegionOps piix4_gpe_ops = { 562 .read = gpe_readb, 563 .write = gpe_writeb, 564 .valid.min_access_size = 1, 565 .valid.max_access_size = 4, 566 .impl.min_access_size = 1, 567 .impl.max_access_size = 1, 568 .endianness = DEVICE_LITTLE_ENDIAN, 569 }; 570 571 572 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp) 573 { 574 PIIX4PMState *s = PIIX4_PM(obj); 575 576 return s->cpu_hotplug_legacy; 577 } 578 579 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp) 580 { 581 PIIX4PMState *s = PIIX4_PM(obj); 582 583 assert(!value); 584 if (s->cpu_hotplug_legacy && value == false) { 585 acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state, 586 PIIX4_CPU_HOTPLUG_IO_BASE); 587 } 588 s->cpu_hotplug_legacy = value; 589 } 590 591 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 592 PCIBus *bus, PIIX4PMState *s) 593 { 594 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 595 "acpi-gpe0", GPE_LEN); 596 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 597 598 acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, 599 s->use_acpi_hotplug_bridge); 600 601 s->cpu_hotplug_legacy = true; 602 object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", 603 piix4_get_cpu_hotplug_legacy, 604 piix4_set_cpu_hotplug_legacy); 605 legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, 606 PIIX4_CPU_HOTPLUG_IO_BASE); 607 608 if (s->acpi_memory_hotplug.is_enabled) { 609 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug, 610 ACPI_MEMORY_HOTPLUG_BASE); 611 } 612 } 613 614 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) 615 { 616 PIIX4PMState *s = PIIX4_PM(adev); 617 618 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); 619 if (!s->cpu_hotplug_legacy) { 620 acpi_cpu_ospm_status(&s->cpuhp_state, list); 621 } 622 } 623 624 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 625 { 626 PIIX4PMState *s = PIIX4_PM(adev); 627 628 acpi_send_gpe_event(&s->ar, s->irq, ev); 629 } 630 631 static Property piix4_pm_properties[] = { 632 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 633 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 634 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 635 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 636 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, 637 use_acpi_hotplug_bridge, true), 638 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, 639 acpi_memory_hotplug.is_enabled, true), 640 DEFINE_PROP_END_OF_LIST(), 641 }; 642 643 static void piix4_pm_class_init(ObjectClass *klass, void *data) 644 { 645 DeviceClass *dc = DEVICE_CLASS(klass); 646 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 647 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 648 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 649 650 k->realize = piix4_pm_realize; 651 k->config_write = pm_write_config; 652 k->vendor_id = PCI_VENDOR_ID_INTEL; 653 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 654 k->revision = 0x03; 655 k->class_id = PCI_CLASS_BRIDGE_OTHER; 656 dc->reset = piix4_pm_reset; 657 dc->desc = "PM"; 658 dc->vmsd = &vmstate_acpi; 659 device_class_set_props(dc, piix4_pm_properties); 660 /* 661 * Reason: part of PIIX4 southbridge, needs to be wired up, 662 * e.g. by mips_malta_init() 663 */ 664 dc->user_creatable = false; 665 dc->hotpluggable = false; 666 hc->pre_plug = piix4_device_pre_plug_cb; 667 hc->plug = piix4_device_plug_cb; 668 hc->unplug_request = piix4_device_unplug_request_cb; 669 hc->unplug = piix4_device_unplug_cb; 670 adevc->ospm_status = piix4_ospm_status; 671 adevc->send_event = piix4_send_gpe; 672 adevc->madt_cpu = pc_madt_cpu_entry; 673 } 674 675 static const TypeInfo piix4_pm_info = { 676 .name = TYPE_PIIX4_PM, 677 .parent = TYPE_PCI_DEVICE, 678 .instance_size = sizeof(PIIX4PMState), 679 .class_init = piix4_pm_class_init, 680 .interfaces = (InterfaceInfo[]) { 681 { TYPE_HOTPLUG_HANDLER }, 682 { TYPE_ACPI_DEVICE_IF }, 683 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 684 { } 685 } 686 }; 687 688 static void piix4_pm_register_types(void) 689 { 690 type_register_static(&piix4_pm_info); 691 } 692 693 type_init(piix4_pm_register_types) 694