1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 #include "qemu/osdep.h" 22 #include "hw/hw.h" 23 #include "hw/i386/pc.h" 24 #include "hw/isa/apm.h" 25 #include "hw/i2c/pm_smbus.h" 26 #include "hw/pci/pci.h" 27 #include "hw/acpi/acpi.h" 28 #include "sysemu/sysemu.h" 29 #include "qapi/error.h" 30 #include "qemu/range.h" 31 #include "hw/nvram/fw_cfg.h" 32 #include "exec/address-spaces.h" 33 #include "hw/acpi/piix4.h" 34 #include "hw/acpi/pcihp.h" 35 #include "hw/acpi/cpu_hotplug.h" 36 #include "hw/acpi/cpu.h" 37 #include "hw/hotplug.h" 38 #include "hw/mem/pc-dimm.h" 39 #include "hw/acpi/memory_hotplug.h" 40 #include "hw/acpi/acpi_dev_interface.h" 41 #include "hw/xen/xen.h" 42 #include "qom/cpu.h" 43 44 //#define DEBUG 45 46 #ifdef DEBUG 47 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 48 #else 49 # define PIIX4_DPRINTF(format, ...) do { } while (0) 50 #endif 51 52 #define GPE_BASE 0xafe0 53 #define GPE_LEN 4 54 55 struct pci_status { 56 uint32_t up; /* deprecated, maintained for migration compatibility */ 57 uint32_t down; 58 }; 59 60 typedef struct PIIX4PMState { 61 /*< private >*/ 62 PCIDevice parent_obj; 63 /*< public >*/ 64 65 MemoryRegion io; 66 uint32_t io_base; 67 68 MemoryRegion io_gpe; 69 ACPIREGS ar; 70 71 APMState apm; 72 73 PMSMBus smb; 74 uint32_t smb_io_base; 75 76 qemu_irq irq; 77 qemu_irq smi_irq; 78 int smm_enabled; 79 Notifier machine_ready; 80 Notifier powerdown_notifier; 81 82 AcpiPciHpState acpi_pci_hotplug; 83 bool use_acpi_pci_hotplug; 84 85 uint8_t disable_s3; 86 uint8_t disable_s4; 87 uint8_t s4_val; 88 89 bool cpu_hotplug_legacy; 90 AcpiCpuHotplug gpe_cpu; 91 CPUHotplugState cpuhp_state; 92 93 MemHotplugState acpi_memory_hotplug; 94 } PIIX4PMState; 95 96 #define TYPE_PIIX4_PM "PIIX4_PM" 97 98 #define PIIX4_PM(obj) \ 99 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) 100 101 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 102 PCIBus *bus, PIIX4PMState *s); 103 104 #define ACPI_ENABLE 0xf1 105 #define ACPI_DISABLE 0xf0 106 107 static void pm_tmr_timer(ACPIREGS *ar) 108 { 109 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 110 acpi_update_sci(&s->ar, s->irq); 111 } 112 113 static void apm_ctrl_changed(uint32_t val, void *arg) 114 { 115 PIIX4PMState *s = arg; 116 PCIDevice *d = PCI_DEVICE(s); 117 118 /* ACPI specs 3.0, 4.7.2.5 */ 119 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 120 if (val == ACPI_ENABLE || val == ACPI_DISABLE) { 121 return; 122 } 123 124 if (d->config[0x5b] & (1 << 1)) { 125 if (s->smi_irq) { 126 qemu_irq_raise(s->smi_irq); 127 } 128 } 129 } 130 131 static void pm_io_space_update(PIIX4PMState *s) 132 { 133 PCIDevice *d = PCI_DEVICE(s); 134 135 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 136 s->io_base &= 0xffc0; 137 138 memory_region_transaction_begin(); 139 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 140 memory_region_set_address(&s->io, s->io_base); 141 memory_region_transaction_commit(); 142 } 143 144 static void smbus_io_space_update(PIIX4PMState *s) 145 { 146 PCIDevice *d = PCI_DEVICE(s); 147 148 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 149 s->smb_io_base &= 0xffc0; 150 151 memory_region_transaction_begin(); 152 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 153 memory_region_set_address(&s->smb.io, s->smb_io_base); 154 memory_region_transaction_commit(); 155 } 156 157 static void pm_write_config(PCIDevice *d, 158 uint32_t address, uint32_t val, int len) 159 { 160 pci_default_write_config(d, address, val, len); 161 if (range_covers_byte(address, len, 0x80) || 162 ranges_overlap(address, len, 0x40, 4)) { 163 pm_io_space_update((PIIX4PMState *)d); 164 } 165 if (range_covers_byte(address, len, 0xd2) || 166 ranges_overlap(address, len, 0x90, 4)) { 167 smbus_io_space_update((PIIX4PMState *)d); 168 } 169 } 170 171 static int vmstate_acpi_post_load(void *opaque, int version_id) 172 { 173 PIIX4PMState *s = opaque; 174 175 pm_io_space_update(s); 176 smbus_io_space_update(s); 177 return 0; 178 } 179 180 #define VMSTATE_GPE_ARRAY(_field, _state) \ 181 { \ 182 .name = (stringify(_field)), \ 183 .version_id = 0, \ 184 .info = &vmstate_info_uint16, \ 185 .size = sizeof(uint16_t), \ 186 .flags = VMS_SINGLE | VMS_POINTER, \ 187 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 188 } 189 190 static const VMStateDescription vmstate_gpe = { 191 .name = "gpe", 192 .version_id = 1, 193 .minimum_version_id = 1, 194 .fields = (VMStateField[]) { 195 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 196 VMSTATE_GPE_ARRAY(en, ACPIGPE), 197 VMSTATE_END_OF_LIST() 198 } 199 }; 200 201 static const VMStateDescription vmstate_pci_status = { 202 .name = "pci_status", 203 .version_id = 1, 204 .minimum_version_id = 1, 205 .fields = (VMStateField[]) { 206 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), 207 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), 208 VMSTATE_END_OF_LIST() 209 } 210 }; 211 212 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) 213 { 214 PIIX4PMState *s = opaque; 215 int ret, i; 216 uint16_t temp; 217 218 ret = pci_device_load(PCI_DEVICE(s), f); 219 if (ret < 0) { 220 return ret; 221 } 222 qemu_get_be16s(f, &s->ar.pm1.evt.sts); 223 qemu_get_be16s(f, &s->ar.pm1.evt.en); 224 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); 225 226 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); 227 if (ret) { 228 return ret; 229 } 230 231 timer_get(f, s->ar.tmr.timer); 232 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); 233 234 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); 235 for (i = 0; i < 3; i++) { 236 qemu_get_be16s(f, &temp); 237 } 238 239 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); 240 for (i = 0; i < 3; i++) { 241 qemu_get_be16s(f, &temp); 242 } 243 244 ret = vmstate_load_state(f, &vmstate_pci_status, 245 &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1); 246 return ret; 247 } 248 249 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) 250 { 251 PIIX4PMState *s = opaque; 252 return s->use_acpi_pci_hotplug; 253 } 254 255 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id) 256 { 257 PIIX4PMState *s = opaque; 258 return !s->use_acpi_pci_hotplug; 259 } 260 261 static bool vmstate_test_use_memhp(void *opaque) 262 { 263 PIIX4PMState *s = opaque; 264 return s->acpi_memory_hotplug.is_enabled; 265 } 266 267 static const VMStateDescription vmstate_memhp_state = { 268 .name = "piix4_pm/memhp", 269 .version_id = 1, 270 .minimum_version_id = 1, 271 .minimum_version_id_old = 1, 272 .needed = vmstate_test_use_memhp, 273 .fields = (VMStateField[]) { 274 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), 275 VMSTATE_END_OF_LIST() 276 } 277 }; 278 279 static bool vmstate_test_use_cpuhp(void *opaque) 280 { 281 PIIX4PMState *s = opaque; 282 return !s->cpu_hotplug_legacy; 283 } 284 285 static int vmstate_cpuhp_pre_load(void *opaque) 286 { 287 Object *obj = OBJECT(opaque); 288 object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort); 289 return 0; 290 } 291 292 static const VMStateDescription vmstate_cpuhp_state = { 293 .name = "piix4_pm/cpuhp", 294 .version_id = 1, 295 .minimum_version_id = 1, 296 .minimum_version_id_old = 1, 297 .needed = vmstate_test_use_cpuhp, 298 .pre_load = vmstate_cpuhp_pre_load, 299 .fields = (VMStateField[]) { 300 VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), 301 VMSTATE_END_OF_LIST() 302 } 303 }; 304 305 static bool piix4_vmstate_need_smbus(void *opaque, int version_id) 306 { 307 return pm_smbus_vmstate_needed(); 308 } 309 310 /* qemu-kvm 1.2 uses version 3 but advertised as 2 311 * To support incoming qemu-kvm 1.2 migration, change version_id 312 * and minimum_version_id to 2 below (which breaks migration from 313 * qemu 1.2). 314 * 315 */ 316 static const VMStateDescription vmstate_acpi = { 317 .name = "piix4_pm", 318 .version_id = 3, 319 .minimum_version_id = 3, 320 .minimum_version_id_old = 1, 321 .load_state_old = acpi_load_old, 322 .post_load = vmstate_acpi_post_load, 323 .fields = (VMStateField[]) { 324 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 325 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 326 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 327 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 328 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 329 VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3, 330 pmsmb_vmstate, PMSMBus), 331 VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), 332 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 333 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 334 VMSTATE_STRUCT_TEST( 335 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 336 PIIX4PMState, 337 vmstate_test_no_use_acpi_pci_hotplug, 338 2, vmstate_pci_status, 339 struct AcpiPciHpPciStatus), 340 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 341 vmstate_test_use_acpi_pci_hotplug), 342 VMSTATE_END_OF_LIST() 343 }, 344 .subsections = (const VMStateDescription*[]) { 345 &vmstate_memhp_state, 346 &vmstate_cpuhp_state, 347 NULL 348 } 349 }; 350 351 static void piix4_reset(void *opaque) 352 { 353 PIIX4PMState *s = opaque; 354 PCIDevice *d = PCI_DEVICE(s); 355 uint8_t *pci_conf = d->config; 356 357 pci_conf[0x58] = 0; 358 pci_conf[0x59] = 0; 359 pci_conf[0x5a] = 0; 360 pci_conf[0x5b] = 0; 361 362 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 363 pci_conf[0x80] = 0; 364 365 if (!s->smm_enabled) { 366 /* Mark SMM as already inited (until KVM supports SMM). */ 367 pci_conf[0x5B] = 0x02; 368 } 369 pm_io_space_update(s); 370 acpi_pcihp_reset(&s->acpi_pci_hotplug); 371 } 372 373 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 374 { 375 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 376 377 assert(s != NULL); 378 acpi_pm1_evt_power_down(&s->ar); 379 } 380 381 static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev, 382 DeviceState *dev, Error **errp) 383 { 384 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 385 acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp); 386 } else if (!object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 387 !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 388 error_setg(errp, "acpi: device pre plug request for not supported" 389 " device type: %s", object_get_typename(OBJECT(dev))); 390 } 391 } 392 393 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, 394 DeviceState *dev, Error **errp) 395 { 396 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 397 398 if (s->acpi_memory_hotplug.is_enabled && 399 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 400 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 401 nvdimm_acpi_plug_cb(hotplug_dev, dev); 402 } else { 403 acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug, 404 dev, errp); 405 } 406 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 407 acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); 408 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 409 if (s->cpu_hotplug_legacy) { 410 legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp); 411 } else { 412 acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 413 } 414 } else { 415 g_assert_not_reached(); 416 } 417 } 418 419 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, 420 DeviceState *dev, Error **errp) 421 { 422 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 423 424 if (s->acpi_memory_hotplug.is_enabled && 425 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 426 acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug, 427 dev, errp); 428 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 429 acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug, 430 dev, errp); 431 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 432 !s->cpu_hotplug_legacy) { 433 acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 434 } else { 435 error_setg(errp, "acpi: device unplug request for not supported device" 436 " type: %s", object_get_typename(OBJECT(dev))); 437 } 438 } 439 440 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, 441 DeviceState *dev, Error **errp) 442 { 443 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 444 445 if (s->acpi_memory_hotplug.is_enabled && 446 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 447 acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); 448 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 449 acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, 450 errp); 451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 452 !s->cpu_hotplug_legacy) { 453 acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); 454 } else { 455 error_setg(errp, "acpi: device unplug for not supported device" 456 " type: %s", object_get_typename(OBJECT(dev))); 457 } 458 } 459 460 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 461 { 462 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 463 PCIDevice *d = PCI_DEVICE(s); 464 MemoryRegion *io_as = pci_address_space_io(d); 465 uint8_t *pci_conf; 466 467 pci_conf = d->config; 468 pci_conf[0x5f] = 0x10 | 469 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 470 pci_conf[0x63] = 0x60; 471 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 472 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 473 } 474 475 static void piix4_pm_add_propeties(PIIX4PMState *s) 476 { 477 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 478 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 479 static const uint32_t gpe0_blk = GPE_BASE; 480 static const uint32_t gpe0_blk_len = GPE_LEN; 481 static const uint16_t sci_int = 9; 482 483 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 484 &acpi_enable_cmd, NULL); 485 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 486 &acpi_disable_cmd, NULL); 487 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 488 &gpe0_blk, NULL); 489 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 490 &gpe0_blk_len, NULL); 491 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 492 &sci_int, NULL); 493 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 494 &s->io_base, NULL); 495 } 496 497 static void piix4_pm_realize(PCIDevice *dev, Error **errp) 498 { 499 PIIX4PMState *s = PIIX4_PM(dev); 500 uint8_t *pci_conf; 501 502 pci_conf = dev->config; 503 pci_conf[0x06] = 0x80; 504 pci_conf[0x07] = 0x02; 505 pci_conf[0x09] = 0x00; 506 pci_conf[0x3d] = 0x01; // interrupt pin 1 507 508 /* APM */ 509 apm_init(dev, &s->apm, apm_ctrl_changed, s); 510 511 if (!s->smm_enabled) { 512 /* Mark SMM as already inited to prevent SMM from running. KVM does not 513 * support SMM mode. */ 514 pci_conf[0x5B] = 0x02; 515 } 516 517 /* XXX: which specification is used ? The i82731AB has different 518 mappings */ 519 pci_conf[0x90] = s->smb_io_base | 1; 520 pci_conf[0x91] = s->smb_io_base >> 8; 521 pci_conf[0xd2] = 0x09; 522 pm_smbus_init(DEVICE(dev), &s->smb, true); 523 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 524 memory_region_add_subregion(pci_address_space_io(dev), 525 s->smb_io_base, &s->smb.io); 526 527 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 528 memory_region_set_enabled(&s->io, false); 529 memory_region_add_subregion(pci_address_space_io(dev), 530 0, &s->io); 531 532 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 533 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 534 acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val); 535 acpi_gpe_init(&s->ar, GPE_LEN); 536 537 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 538 qemu_register_powerdown_notifier(&s->powerdown_notifier); 539 540 s->machine_ready.notify = piix4_pm_machine_ready; 541 qemu_add_machine_init_done_notifier(&s->machine_ready); 542 qemu_register_reset(piix4_reset, s); 543 544 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), 545 pci_get_bus(dev), s); 546 qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s), &error_abort); 547 548 piix4_pm_add_propeties(s); 549 } 550 551 Object *piix4_pm_find(void) 552 { 553 bool ambig; 554 Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig); 555 556 if (ambig || !o) { 557 return NULL; 558 } 559 return o; 560 } 561 562 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 563 qemu_irq sci_irq, qemu_irq smi_irq, 564 int smm_enabled, DeviceState **piix4_pm) 565 { 566 DeviceState *dev; 567 PIIX4PMState *s; 568 569 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); 570 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 571 if (piix4_pm) { 572 *piix4_pm = dev; 573 } 574 575 s = PIIX4_PM(dev); 576 s->irq = sci_irq; 577 s->smi_irq = smi_irq; 578 s->smm_enabled = smm_enabled; 579 if (xen_enabled()) { 580 s->use_acpi_pci_hotplug = false; 581 } 582 583 qdev_init_nofail(dev); 584 585 return s->smb.smbus; 586 } 587 588 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 589 { 590 PIIX4PMState *s = opaque; 591 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 592 593 PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); 594 return val; 595 } 596 597 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 598 unsigned width) 599 { 600 PIIX4PMState *s = opaque; 601 602 acpi_gpe_ioport_writeb(&s->ar, addr, val); 603 acpi_update_sci(&s->ar, s->irq); 604 605 PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); 606 } 607 608 static const MemoryRegionOps piix4_gpe_ops = { 609 .read = gpe_readb, 610 .write = gpe_writeb, 611 .valid.min_access_size = 1, 612 .valid.max_access_size = 4, 613 .impl.min_access_size = 1, 614 .impl.max_access_size = 1, 615 .endianness = DEVICE_LITTLE_ENDIAN, 616 }; 617 618 619 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp) 620 { 621 PIIX4PMState *s = PIIX4_PM(obj); 622 623 return s->cpu_hotplug_legacy; 624 } 625 626 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp) 627 { 628 PIIX4PMState *s = PIIX4_PM(obj); 629 630 assert(!value); 631 if (s->cpu_hotplug_legacy && value == false) { 632 acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state, 633 PIIX4_CPU_HOTPLUG_IO_BASE); 634 } 635 s->cpu_hotplug_legacy = value; 636 } 637 638 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 639 PCIBus *bus, PIIX4PMState *s) 640 { 641 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 642 "acpi-gpe0", GPE_LEN); 643 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 644 645 acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, 646 s->use_acpi_pci_hotplug); 647 648 s->cpu_hotplug_legacy = true; 649 object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", 650 piix4_get_cpu_hotplug_legacy, 651 piix4_set_cpu_hotplug_legacy, 652 NULL); 653 legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, 654 PIIX4_CPU_HOTPLUG_IO_BASE); 655 656 if (s->acpi_memory_hotplug.is_enabled) { 657 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug, 658 ACPI_MEMORY_HOTPLUG_BASE); 659 } 660 } 661 662 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) 663 { 664 PIIX4PMState *s = PIIX4_PM(adev); 665 666 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); 667 if (!s->cpu_hotplug_legacy) { 668 acpi_cpu_ospm_status(&s->cpuhp_state, list); 669 } 670 } 671 672 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 673 { 674 PIIX4PMState *s = PIIX4_PM(adev); 675 676 acpi_send_gpe_event(&s->ar, s->irq, ev); 677 } 678 679 static Property piix4_pm_properties[] = { 680 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 681 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 682 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 683 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 684 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, 685 use_acpi_pci_hotplug, true), 686 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, 687 acpi_memory_hotplug.is_enabled, true), 688 DEFINE_PROP_END_OF_LIST(), 689 }; 690 691 static void piix4_pm_class_init(ObjectClass *klass, void *data) 692 { 693 DeviceClass *dc = DEVICE_CLASS(klass); 694 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 695 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 696 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 697 698 k->realize = piix4_pm_realize; 699 k->config_write = pm_write_config; 700 k->vendor_id = PCI_VENDOR_ID_INTEL; 701 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 702 k->revision = 0x03; 703 k->class_id = PCI_CLASS_BRIDGE_OTHER; 704 dc->desc = "PM"; 705 dc->vmsd = &vmstate_acpi; 706 dc->props = piix4_pm_properties; 707 /* 708 * Reason: part of PIIX4 southbridge, needs to be wired up, 709 * e.g. by mips_malta_init() 710 */ 711 dc->user_creatable = false; 712 dc->hotpluggable = false; 713 hc->pre_plug = piix4_device_pre_plug_cb; 714 hc->plug = piix4_device_plug_cb; 715 hc->unplug_request = piix4_device_unplug_request_cb; 716 hc->unplug = piix4_device_unplug_cb; 717 adevc->ospm_status = piix4_ospm_status; 718 adevc->send_event = piix4_send_gpe; 719 adevc->madt_cpu = pc_madt_cpu_entry; 720 } 721 722 static const TypeInfo piix4_pm_info = { 723 .name = TYPE_PIIX4_PM, 724 .parent = TYPE_PCI_DEVICE, 725 .instance_size = sizeof(PIIX4PMState), 726 .class_init = piix4_pm_class_init, 727 .interfaces = (InterfaceInfo[]) { 728 { TYPE_HOTPLUG_HANDLER }, 729 { TYPE_ACPI_DEVICE_IF }, 730 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 731 { } 732 } 733 }; 734 735 static void piix4_pm_register_types(void) 736 { 737 type_register_static(&piix4_pm_info); 738 } 739 740 type_init(piix4_pm_register_types) 741