1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 #include "qemu/osdep.h" 22 #include "hw/hw.h" 23 #include "hw/i386/pc.h" 24 #include "hw/isa/apm.h" 25 #include "hw/i2c/pm_smbus.h" 26 #include "hw/pci/pci.h" 27 #include "hw/acpi/acpi.h" 28 #include "sysemu/sysemu.h" 29 #include "qapi/error.h" 30 #include "qemu/range.h" 31 #include "exec/address-spaces.h" 32 #include "hw/acpi/piix4.h" 33 #include "hw/acpi/pcihp.h" 34 #include "hw/acpi/cpu_hotplug.h" 35 #include "hw/acpi/cpu.h" 36 #include "hw/hotplug.h" 37 #include "hw/mem/pc-dimm.h" 38 #include "hw/acpi/memory_hotplug.h" 39 #include "hw/acpi/acpi_dev_interface.h" 40 #include "hw/xen/xen.h" 41 #include "qom/cpu.h" 42 43 //#define DEBUG 44 45 #ifdef DEBUG 46 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 47 #else 48 # define PIIX4_DPRINTF(format, ...) do { } while (0) 49 #endif 50 51 #define GPE_BASE 0xafe0 52 #define GPE_LEN 4 53 54 struct pci_status { 55 uint32_t up; /* deprecated, maintained for migration compatibility */ 56 uint32_t down; 57 }; 58 59 typedef struct PIIX4PMState { 60 /*< private >*/ 61 PCIDevice parent_obj; 62 /*< public >*/ 63 64 MemoryRegion io; 65 uint32_t io_base; 66 67 MemoryRegion io_gpe; 68 ACPIREGS ar; 69 70 APMState apm; 71 72 PMSMBus smb; 73 uint32_t smb_io_base; 74 75 qemu_irq irq; 76 qemu_irq smi_irq; 77 int smm_enabled; 78 Notifier machine_ready; 79 Notifier powerdown_notifier; 80 81 AcpiPciHpState acpi_pci_hotplug; 82 bool use_acpi_pci_hotplug; 83 84 uint8_t disable_s3; 85 uint8_t disable_s4; 86 uint8_t s4_val; 87 88 bool cpu_hotplug_legacy; 89 AcpiCpuHotplug gpe_cpu; 90 CPUHotplugState cpuhp_state; 91 92 MemHotplugState acpi_memory_hotplug; 93 } PIIX4PMState; 94 95 #define PIIX4_PM(obj) \ 96 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) 97 98 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 99 PCIBus *bus, PIIX4PMState *s); 100 101 #define ACPI_ENABLE 0xf1 102 #define ACPI_DISABLE 0xf0 103 104 static void pm_tmr_timer(ACPIREGS *ar) 105 { 106 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 107 acpi_update_sci(&s->ar, s->irq); 108 } 109 110 static void apm_ctrl_changed(uint32_t val, void *arg) 111 { 112 PIIX4PMState *s = arg; 113 PCIDevice *d = PCI_DEVICE(s); 114 115 /* ACPI specs 3.0, 4.7.2.5 */ 116 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 117 if (val == ACPI_ENABLE || val == ACPI_DISABLE) { 118 return; 119 } 120 121 if (d->config[0x5b] & (1 << 1)) { 122 if (s->smi_irq) { 123 qemu_irq_raise(s->smi_irq); 124 } 125 } 126 } 127 128 static void pm_io_space_update(PIIX4PMState *s) 129 { 130 PCIDevice *d = PCI_DEVICE(s); 131 132 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 133 s->io_base &= 0xffc0; 134 135 memory_region_transaction_begin(); 136 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 137 memory_region_set_address(&s->io, s->io_base); 138 memory_region_transaction_commit(); 139 } 140 141 static void smbus_io_space_update(PIIX4PMState *s) 142 { 143 PCIDevice *d = PCI_DEVICE(s); 144 145 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 146 s->smb_io_base &= 0xffc0; 147 148 memory_region_transaction_begin(); 149 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 150 memory_region_set_address(&s->smb.io, s->smb_io_base); 151 memory_region_transaction_commit(); 152 } 153 154 static void pm_write_config(PCIDevice *d, 155 uint32_t address, uint32_t val, int len) 156 { 157 pci_default_write_config(d, address, val, len); 158 if (range_covers_byte(address, len, 0x80) || 159 ranges_overlap(address, len, 0x40, 4)) { 160 pm_io_space_update((PIIX4PMState *)d); 161 } 162 if (range_covers_byte(address, len, 0xd2) || 163 ranges_overlap(address, len, 0x90, 4)) { 164 smbus_io_space_update((PIIX4PMState *)d); 165 } 166 } 167 168 static int vmstate_acpi_post_load(void *opaque, int version_id) 169 { 170 PIIX4PMState *s = opaque; 171 172 pm_io_space_update(s); 173 smbus_io_space_update(s); 174 return 0; 175 } 176 177 #define VMSTATE_GPE_ARRAY(_field, _state) \ 178 { \ 179 .name = (stringify(_field)), \ 180 .version_id = 0, \ 181 .info = &vmstate_info_uint16, \ 182 .size = sizeof(uint16_t), \ 183 .flags = VMS_SINGLE | VMS_POINTER, \ 184 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 185 } 186 187 static const VMStateDescription vmstate_gpe = { 188 .name = "gpe", 189 .version_id = 1, 190 .minimum_version_id = 1, 191 .fields = (VMStateField[]) { 192 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 193 VMSTATE_GPE_ARRAY(en, ACPIGPE), 194 VMSTATE_END_OF_LIST() 195 } 196 }; 197 198 static const VMStateDescription vmstate_pci_status = { 199 .name = "pci_status", 200 .version_id = 1, 201 .minimum_version_id = 1, 202 .fields = (VMStateField[]) { 203 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), 204 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), 205 VMSTATE_END_OF_LIST() 206 } 207 }; 208 209 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) 210 { 211 PIIX4PMState *s = opaque; 212 int ret, i; 213 uint16_t temp; 214 215 ret = pci_device_load(PCI_DEVICE(s), f); 216 if (ret < 0) { 217 return ret; 218 } 219 qemu_get_be16s(f, &s->ar.pm1.evt.sts); 220 qemu_get_be16s(f, &s->ar.pm1.evt.en); 221 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); 222 223 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); 224 if (ret) { 225 return ret; 226 } 227 228 timer_get(f, s->ar.tmr.timer); 229 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); 230 231 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); 232 for (i = 0; i < 3; i++) { 233 qemu_get_be16s(f, &temp); 234 } 235 236 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); 237 for (i = 0; i < 3; i++) { 238 qemu_get_be16s(f, &temp); 239 } 240 241 ret = vmstate_load_state(f, &vmstate_pci_status, 242 &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1); 243 return ret; 244 } 245 246 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) 247 { 248 PIIX4PMState *s = opaque; 249 return s->use_acpi_pci_hotplug; 250 } 251 252 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id) 253 { 254 PIIX4PMState *s = opaque; 255 return !s->use_acpi_pci_hotplug; 256 } 257 258 static bool vmstate_test_use_memhp(void *opaque) 259 { 260 PIIX4PMState *s = opaque; 261 return s->acpi_memory_hotplug.is_enabled; 262 } 263 264 static const VMStateDescription vmstate_memhp_state = { 265 .name = "piix4_pm/memhp", 266 .version_id = 1, 267 .minimum_version_id = 1, 268 .minimum_version_id_old = 1, 269 .needed = vmstate_test_use_memhp, 270 .fields = (VMStateField[]) { 271 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), 272 VMSTATE_END_OF_LIST() 273 } 274 }; 275 276 static bool vmstate_test_use_cpuhp(void *opaque) 277 { 278 PIIX4PMState *s = opaque; 279 return !s->cpu_hotplug_legacy; 280 } 281 282 static int vmstate_cpuhp_pre_load(void *opaque) 283 { 284 Object *obj = OBJECT(opaque); 285 object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort); 286 return 0; 287 } 288 289 static const VMStateDescription vmstate_cpuhp_state = { 290 .name = "piix4_pm/cpuhp", 291 .version_id = 1, 292 .minimum_version_id = 1, 293 .minimum_version_id_old = 1, 294 .needed = vmstate_test_use_cpuhp, 295 .pre_load = vmstate_cpuhp_pre_load, 296 .fields = (VMStateField[]) { 297 VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), 298 VMSTATE_END_OF_LIST() 299 } 300 }; 301 302 static bool piix4_vmstate_need_smbus(void *opaque, int version_id) 303 { 304 return pm_smbus_vmstate_needed(); 305 } 306 307 /* qemu-kvm 1.2 uses version 3 but advertised as 2 308 * To support incoming qemu-kvm 1.2 migration, change version_id 309 * and minimum_version_id to 2 below (which breaks migration from 310 * qemu 1.2). 311 * 312 */ 313 static const VMStateDescription vmstate_acpi = { 314 .name = "piix4_pm", 315 .version_id = 3, 316 .minimum_version_id = 3, 317 .minimum_version_id_old = 1, 318 .load_state_old = acpi_load_old, 319 .post_load = vmstate_acpi_post_load, 320 .fields = (VMStateField[]) { 321 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 322 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 323 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 324 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 325 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 326 VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3, 327 pmsmb_vmstate, PMSMBus), 328 VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), 329 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 330 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 331 VMSTATE_STRUCT_TEST( 332 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 333 PIIX4PMState, 334 vmstate_test_no_use_acpi_pci_hotplug, 335 2, vmstate_pci_status, 336 struct AcpiPciHpPciStatus), 337 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 338 vmstate_test_use_acpi_pci_hotplug), 339 VMSTATE_END_OF_LIST() 340 }, 341 .subsections = (const VMStateDescription*[]) { 342 &vmstate_memhp_state, 343 &vmstate_cpuhp_state, 344 NULL 345 } 346 }; 347 348 static void piix4_reset(void *opaque) 349 { 350 PIIX4PMState *s = opaque; 351 PCIDevice *d = PCI_DEVICE(s); 352 uint8_t *pci_conf = d->config; 353 354 pci_conf[0x58] = 0; 355 pci_conf[0x59] = 0; 356 pci_conf[0x5a] = 0; 357 pci_conf[0x5b] = 0; 358 359 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 360 pci_conf[0x80] = 0; 361 362 if (!s->smm_enabled) { 363 /* Mark SMM as already inited (until KVM supports SMM). */ 364 pci_conf[0x5B] = 0x02; 365 } 366 pm_io_space_update(s); 367 acpi_pcihp_reset(&s->acpi_pci_hotplug); 368 } 369 370 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 371 { 372 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 373 374 assert(s != NULL); 375 acpi_pm1_evt_power_down(&s->ar); 376 } 377 378 static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev, 379 DeviceState *dev, Error **errp) 380 { 381 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 382 383 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 384 acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp); 385 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 386 if (!s->acpi_memory_hotplug.is_enabled) { 387 error_setg(errp, 388 "memory hotplug is not enabled: %s.memory-hotplug-support " 389 "is not set", object_get_typename(OBJECT(s))); 390 } 391 } else if ( 392 !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 393 error_setg(errp, "acpi: device pre plug request for not supported" 394 " device type: %s", object_get_typename(OBJECT(dev))); 395 } 396 } 397 398 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, 399 DeviceState *dev, Error **errp) 400 { 401 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 402 403 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 404 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 405 nvdimm_acpi_plug_cb(hotplug_dev, dev); 406 } else { 407 acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug, 408 dev, errp); 409 } 410 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 411 acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); 412 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 413 if (s->cpu_hotplug_legacy) { 414 legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp); 415 } else { 416 acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 417 } 418 } else { 419 g_assert_not_reached(); 420 } 421 } 422 423 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, 424 DeviceState *dev, Error **errp) 425 { 426 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 427 428 if (s->acpi_memory_hotplug.is_enabled && 429 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 430 acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug, 431 dev, errp); 432 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 433 acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug, 434 dev, errp); 435 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 436 !s->cpu_hotplug_legacy) { 437 acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 438 } else { 439 error_setg(errp, "acpi: device unplug request for not supported device" 440 " type: %s", object_get_typename(OBJECT(dev))); 441 } 442 } 443 444 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, 445 DeviceState *dev, Error **errp) 446 { 447 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 448 449 if (s->acpi_memory_hotplug.is_enabled && 450 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 451 acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); 452 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 453 acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, 454 errp); 455 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 456 !s->cpu_hotplug_legacy) { 457 acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); 458 } else { 459 error_setg(errp, "acpi: device unplug for not supported device" 460 " type: %s", object_get_typename(OBJECT(dev))); 461 } 462 } 463 464 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 465 { 466 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 467 PCIDevice *d = PCI_DEVICE(s); 468 MemoryRegion *io_as = pci_address_space_io(d); 469 uint8_t *pci_conf; 470 471 pci_conf = d->config; 472 pci_conf[0x5f] = 0x10 | 473 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 474 pci_conf[0x63] = 0x60; 475 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 476 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 477 } 478 479 static void piix4_pm_add_propeties(PIIX4PMState *s) 480 { 481 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 482 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 483 static const uint32_t gpe0_blk = GPE_BASE; 484 static const uint32_t gpe0_blk_len = GPE_LEN; 485 static const uint16_t sci_int = 9; 486 487 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 488 &acpi_enable_cmd, NULL); 489 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 490 &acpi_disable_cmd, NULL); 491 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 492 &gpe0_blk, NULL); 493 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 494 &gpe0_blk_len, NULL); 495 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 496 &sci_int, NULL); 497 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 498 &s->io_base, NULL); 499 } 500 501 static void piix4_pm_realize(PCIDevice *dev, Error **errp) 502 { 503 PIIX4PMState *s = PIIX4_PM(dev); 504 uint8_t *pci_conf; 505 506 pci_conf = dev->config; 507 pci_conf[0x06] = 0x80; 508 pci_conf[0x07] = 0x02; 509 pci_conf[0x09] = 0x00; 510 pci_conf[0x3d] = 0x01; // interrupt pin 1 511 512 /* APM */ 513 apm_init(dev, &s->apm, apm_ctrl_changed, s); 514 515 if (!s->smm_enabled) { 516 /* Mark SMM as already inited to prevent SMM from running. KVM does not 517 * support SMM mode. */ 518 pci_conf[0x5B] = 0x02; 519 } 520 521 /* XXX: which specification is used ? The i82731AB has different 522 mappings */ 523 pci_conf[0x90] = s->smb_io_base | 1; 524 pci_conf[0x91] = s->smb_io_base >> 8; 525 pci_conf[0xd2] = 0x09; 526 pm_smbus_init(DEVICE(dev), &s->smb, true); 527 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 528 memory_region_add_subregion(pci_address_space_io(dev), 529 s->smb_io_base, &s->smb.io); 530 531 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 532 memory_region_set_enabled(&s->io, false); 533 memory_region_add_subregion(pci_address_space_io(dev), 534 0, &s->io); 535 536 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 537 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 538 acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val); 539 acpi_gpe_init(&s->ar, GPE_LEN); 540 541 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 542 qemu_register_powerdown_notifier(&s->powerdown_notifier); 543 544 s->machine_ready.notify = piix4_pm_machine_ready; 545 qemu_add_machine_init_done_notifier(&s->machine_ready); 546 qemu_register_reset(piix4_reset, s); 547 548 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), 549 pci_get_bus(dev), s); 550 qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s), &error_abort); 551 552 piix4_pm_add_propeties(s); 553 } 554 555 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 556 qemu_irq sci_irq, qemu_irq smi_irq, 557 int smm_enabled, DeviceState **piix4_pm) 558 { 559 DeviceState *dev; 560 PIIX4PMState *s; 561 562 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); 563 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 564 if (piix4_pm) { 565 *piix4_pm = dev; 566 } 567 568 s = PIIX4_PM(dev); 569 s->irq = sci_irq; 570 s->smi_irq = smi_irq; 571 s->smm_enabled = smm_enabled; 572 if (xen_enabled()) { 573 s->use_acpi_pci_hotplug = false; 574 } 575 576 qdev_init_nofail(dev); 577 578 return s->smb.smbus; 579 } 580 581 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 582 { 583 PIIX4PMState *s = opaque; 584 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 585 586 PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); 587 return val; 588 } 589 590 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 591 unsigned width) 592 { 593 PIIX4PMState *s = opaque; 594 595 acpi_gpe_ioport_writeb(&s->ar, addr, val); 596 acpi_update_sci(&s->ar, s->irq); 597 598 PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); 599 } 600 601 static const MemoryRegionOps piix4_gpe_ops = { 602 .read = gpe_readb, 603 .write = gpe_writeb, 604 .valid.min_access_size = 1, 605 .valid.max_access_size = 4, 606 .impl.min_access_size = 1, 607 .impl.max_access_size = 1, 608 .endianness = DEVICE_LITTLE_ENDIAN, 609 }; 610 611 612 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp) 613 { 614 PIIX4PMState *s = PIIX4_PM(obj); 615 616 return s->cpu_hotplug_legacy; 617 } 618 619 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp) 620 { 621 PIIX4PMState *s = PIIX4_PM(obj); 622 623 assert(!value); 624 if (s->cpu_hotplug_legacy && value == false) { 625 acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state, 626 PIIX4_CPU_HOTPLUG_IO_BASE); 627 } 628 s->cpu_hotplug_legacy = value; 629 } 630 631 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 632 PCIBus *bus, PIIX4PMState *s) 633 { 634 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 635 "acpi-gpe0", GPE_LEN); 636 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 637 638 acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, 639 s->use_acpi_pci_hotplug); 640 641 s->cpu_hotplug_legacy = true; 642 object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", 643 piix4_get_cpu_hotplug_legacy, 644 piix4_set_cpu_hotplug_legacy, 645 NULL); 646 legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, 647 PIIX4_CPU_HOTPLUG_IO_BASE); 648 649 if (s->acpi_memory_hotplug.is_enabled) { 650 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug, 651 ACPI_MEMORY_HOTPLUG_BASE); 652 } 653 } 654 655 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) 656 { 657 PIIX4PMState *s = PIIX4_PM(adev); 658 659 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); 660 if (!s->cpu_hotplug_legacy) { 661 acpi_cpu_ospm_status(&s->cpuhp_state, list); 662 } 663 } 664 665 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 666 { 667 PIIX4PMState *s = PIIX4_PM(adev); 668 669 acpi_send_gpe_event(&s->ar, s->irq, ev); 670 } 671 672 static Property piix4_pm_properties[] = { 673 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 674 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 675 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 676 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 677 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, 678 use_acpi_pci_hotplug, true), 679 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, 680 acpi_memory_hotplug.is_enabled, true), 681 DEFINE_PROP_END_OF_LIST(), 682 }; 683 684 static void piix4_pm_class_init(ObjectClass *klass, void *data) 685 { 686 DeviceClass *dc = DEVICE_CLASS(klass); 687 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 688 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 689 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 690 691 k->realize = piix4_pm_realize; 692 k->config_write = pm_write_config; 693 k->vendor_id = PCI_VENDOR_ID_INTEL; 694 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 695 k->revision = 0x03; 696 k->class_id = PCI_CLASS_BRIDGE_OTHER; 697 dc->desc = "PM"; 698 dc->vmsd = &vmstate_acpi; 699 dc->props = piix4_pm_properties; 700 /* 701 * Reason: part of PIIX4 southbridge, needs to be wired up, 702 * e.g. by mips_malta_init() 703 */ 704 dc->user_creatable = false; 705 dc->hotpluggable = false; 706 hc->pre_plug = piix4_device_pre_plug_cb; 707 hc->plug = piix4_device_plug_cb; 708 hc->unplug_request = piix4_device_unplug_request_cb; 709 hc->unplug = piix4_device_unplug_cb; 710 adevc->ospm_status = piix4_ospm_status; 711 adevc->send_event = piix4_send_gpe; 712 adevc->madt_cpu = pc_madt_cpu_entry; 713 } 714 715 static const TypeInfo piix4_pm_info = { 716 .name = TYPE_PIIX4_PM, 717 .parent = TYPE_PCI_DEVICE, 718 .instance_size = sizeof(PIIX4PMState), 719 .class_init = piix4_pm_class_init, 720 .interfaces = (InterfaceInfo[]) { 721 { TYPE_HOTPLUG_HANDLER }, 722 { TYPE_ACPI_DEVICE_IF }, 723 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 724 { } 725 } 726 }; 727 728 static void piix4_pm_register_types(void) 729 { 730 type_register_static(&piix4_pm_info); 731 } 732 733 type_init(piix4_pm_register_types) 734