1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/hw.h" 24 #include "hw/i386/pc.h" 25 #include "hw/irq.h" 26 #include "hw/isa/apm.h" 27 #include "hw/i2c/pm_smbus.h" 28 #include "hw/pci/pci.h" 29 #include "hw/acpi/acpi.h" 30 #include "sysemu/reset.h" 31 #include "sysemu/sysemu.h" 32 #include "qapi/error.h" 33 #include "qemu/range.h" 34 #include "exec/address-spaces.h" 35 #include "hw/acpi/piix4.h" 36 #include "hw/acpi/pcihp.h" 37 #include "hw/acpi/cpu_hotplug.h" 38 #include "hw/acpi/cpu.h" 39 #include "hw/hotplug.h" 40 #include "hw/mem/pc-dimm.h" 41 #include "hw/acpi/memory_hotplug.h" 42 #include "hw/acpi/acpi_dev_interface.h" 43 #include "hw/xen/xen.h" 44 #include "migration/qemu-file-types.h" 45 #include "qom/cpu.h" 46 #include "trace.h" 47 48 #define GPE_BASE 0xafe0 49 #define GPE_LEN 4 50 51 struct pci_status { 52 uint32_t up; /* deprecated, maintained for migration compatibility */ 53 uint32_t down; 54 }; 55 56 typedef struct PIIX4PMState { 57 /*< private >*/ 58 PCIDevice parent_obj; 59 /*< public >*/ 60 61 MemoryRegion io; 62 uint32_t io_base; 63 64 MemoryRegion io_gpe; 65 ACPIREGS ar; 66 67 APMState apm; 68 69 PMSMBus smb; 70 uint32_t smb_io_base; 71 72 qemu_irq irq; 73 qemu_irq smi_irq; 74 int smm_enabled; 75 Notifier machine_ready; 76 Notifier powerdown_notifier; 77 78 AcpiPciHpState acpi_pci_hotplug; 79 bool use_acpi_pci_hotplug; 80 81 uint8_t disable_s3; 82 uint8_t disable_s4; 83 uint8_t s4_val; 84 85 bool cpu_hotplug_legacy; 86 AcpiCpuHotplug gpe_cpu; 87 CPUHotplugState cpuhp_state; 88 89 MemHotplugState acpi_memory_hotplug; 90 } PIIX4PMState; 91 92 #define PIIX4_PM(obj) \ 93 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) 94 95 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 96 PCIBus *bus, PIIX4PMState *s); 97 98 #define ACPI_ENABLE 0xf1 99 #define ACPI_DISABLE 0xf0 100 101 static void pm_tmr_timer(ACPIREGS *ar) 102 { 103 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 104 acpi_update_sci(&s->ar, s->irq); 105 } 106 107 static void apm_ctrl_changed(uint32_t val, void *arg) 108 { 109 PIIX4PMState *s = arg; 110 PCIDevice *d = PCI_DEVICE(s); 111 112 /* ACPI specs 3.0, 4.7.2.5 */ 113 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 114 if (val == ACPI_ENABLE || val == ACPI_DISABLE) { 115 return; 116 } 117 118 if (d->config[0x5b] & (1 << 1)) { 119 if (s->smi_irq) { 120 qemu_irq_raise(s->smi_irq); 121 } 122 } 123 } 124 125 static void pm_io_space_update(PIIX4PMState *s) 126 { 127 PCIDevice *d = PCI_DEVICE(s); 128 129 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 130 s->io_base &= 0xffc0; 131 132 memory_region_transaction_begin(); 133 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 134 memory_region_set_address(&s->io, s->io_base); 135 memory_region_transaction_commit(); 136 } 137 138 static void smbus_io_space_update(PIIX4PMState *s) 139 { 140 PCIDevice *d = PCI_DEVICE(s); 141 142 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 143 s->smb_io_base &= 0xffc0; 144 145 memory_region_transaction_begin(); 146 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 147 memory_region_set_address(&s->smb.io, s->smb_io_base); 148 memory_region_transaction_commit(); 149 } 150 151 static void pm_write_config(PCIDevice *d, 152 uint32_t address, uint32_t val, int len) 153 { 154 pci_default_write_config(d, address, val, len); 155 if (range_covers_byte(address, len, 0x80) || 156 ranges_overlap(address, len, 0x40, 4)) { 157 pm_io_space_update((PIIX4PMState *)d); 158 } 159 if (range_covers_byte(address, len, 0xd2) || 160 ranges_overlap(address, len, 0x90, 4)) { 161 smbus_io_space_update((PIIX4PMState *)d); 162 } 163 } 164 165 static int vmstate_acpi_post_load(void *opaque, int version_id) 166 { 167 PIIX4PMState *s = opaque; 168 169 pm_io_space_update(s); 170 smbus_io_space_update(s); 171 return 0; 172 } 173 174 #define VMSTATE_GPE_ARRAY(_field, _state) \ 175 { \ 176 .name = (stringify(_field)), \ 177 .version_id = 0, \ 178 .info = &vmstate_info_uint16, \ 179 .size = sizeof(uint16_t), \ 180 .flags = VMS_SINGLE | VMS_POINTER, \ 181 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 182 } 183 184 static const VMStateDescription vmstate_gpe = { 185 .name = "gpe", 186 .version_id = 1, 187 .minimum_version_id = 1, 188 .fields = (VMStateField[]) { 189 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 190 VMSTATE_GPE_ARRAY(en, ACPIGPE), 191 VMSTATE_END_OF_LIST() 192 } 193 }; 194 195 static const VMStateDescription vmstate_pci_status = { 196 .name = "pci_status", 197 .version_id = 1, 198 .minimum_version_id = 1, 199 .fields = (VMStateField[]) { 200 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), 201 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), 202 VMSTATE_END_OF_LIST() 203 } 204 }; 205 206 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) 207 { 208 PIIX4PMState *s = opaque; 209 int ret, i; 210 uint16_t temp; 211 212 ret = pci_device_load(PCI_DEVICE(s), f); 213 if (ret < 0) { 214 return ret; 215 } 216 qemu_get_be16s(f, &s->ar.pm1.evt.sts); 217 qemu_get_be16s(f, &s->ar.pm1.evt.en); 218 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); 219 220 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); 221 if (ret) { 222 return ret; 223 } 224 225 timer_get(f, s->ar.tmr.timer); 226 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); 227 228 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); 229 for (i = 0; i < 3; i++) { 230 qemu_get_be16s(f, &temp); 231 } 232 233 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); 234 for (i = 0; i < 3; i++) { 235 qemu_get_be16s(f, &temp); 236 } 237 238 ret = vmstate_load_state(f, &vmstate_pci_status, 239 &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1); 240 return ret; 241 } 242 243 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) 244 { 245 PIIX4PMState *s = opaque; 246 return s->use_acpi_pci_hotplug; 247 } 248 249 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id) 250 { 251 PIIX4PMState *s = opaque; 252 return !s->use_acpi_pci_hotplug; 253 } 254 255 static bool vmstate_test_use_memhp(void *opaque) 256 { 257 PIIX4PMState *s = opaque; 258 return s->acpi_memory_hotplug.is_enabled; 259 } 260 261 static const VMStateDescription vmstate_memhp_state = { 262 .name = "piix4_pm/memhp", 263 .version_id = 1, 264 .minimum_version_id = 1, 265 .minimum_version_id_old = 1, 266 .needed = vmstate_test_use_memhp, 267 .fields = (VMStateField[]) { 268 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), 269 VMSTATE_END_OF_LIST() 270 } 271 }; 272 273 static bool vmstate_test_use_cpuhp(void *opaque) 274 { 275 PIIX4PMState *s = opaque; 276 return !s->cpu_hotplug_legacy; 277 } 278 279 static int vmstate_cpuhp_pre_load(void *opaque) 280 { 281 Object *obj = OBJECT(opaque); 282 object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort); 283 return 0; 284 } 285 286 static const VMStateDescription vmstate_cpuhp_state = { 287 .name = "piix4_pm/cpuhp", 288 .version_id = 1, 289 .minimum_version_id = 1, 290 .minimum_version_id_old = 1, 291 .needed = vmstate_test_use_cpuhp, 292 .pre_load = vmstate_cpuhp_pre_load, 293 .fields = (VMStateField[]) { 294 VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), 295 VMSTATE_END_OF_LIST() 296 } 297 }; 298 299 static bool piix4_vmstate_need_smbus(void *opaque, int version_id) 300 { 301 return pm_smbus_vmstate_needed(); 302 } 303 304 /* qemu-kvm 1.2 uses version 3 but advertised as 2 305 * To support incoming qemu-kvm 1.2 migration, change version_id 306 * and minimum_version_id to 2 below (which breaks migration from 307 * qemu 1.2). 308 * 309 */ 310 static const VMStateDescription vmstate_acpi = { 311 .name = "piix4_pm", 312 .version_id = 3, 313 .minimum_version_id = 3, 314 .minimum_version_id_old = 1, 315 .load_state_old = acpi_load_old, 316 .post_load = vmstate_acpi_post_load, 317 .fields = (VMStateField[]) { 318 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 319 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 320 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 321 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 322 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 323 VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3, 324 pmsmb_vmstate, PMSMBus), 325 VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), 326 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 327 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 328 VMSTATE_STRUCT_TEST( 329 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 330 PIIX4PMState, 331 vmstate_test_no_use_acpi_pci_hotplug, 332 2, vmstate_pci_status, 333 struct AcpiPciHpPciStatus), 334 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 335 vmstate_test_use_acpi_pci_hotplug), 336 VMSTATE_END_OF_LIST() 337 }, 338 .subsections = (const VMStateDescription*[]) { 339 &vmstate_memhp_state, 340 &vmstate_cpuhp_state, 341 NULL 342 } 343 }; 344 345 static void piix4_reset(void *opaque) 346 { 347 PIIX4PMState *s = opaque; 348 PCIDevice *d = PCI_DEVICE(s); 349 uint8_t *pci_conf = d->config; 350 351 pci_conf[0x58] = 0; 352 pci_conf[0x59] = 0; 353 pci_conf[0x5a] = 0; 354 pci_conf[0x5b] = 0; 355 356 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 357 pci_conf[0x80] = 0; 358 359 if (!s->smm_enabled) { 360 /* Mark SMM as already inited (until KVM supports SMM). */ 361 pci_conf[0x5B] = 0x02; 362 } 363 pm_io_space_update(s); 364 acpi_pcihp_reset(&s->acpi_pci_hotplug); 365 } 366 367 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 368 { 369 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 370 371 assert(s != NULL); 372 acpi_pm1_evt_power_down(&s->ar); 373 } 374 375 static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev, 376 DeviceState *dev, Error **errp) 377 { 378 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 379 380 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 381 acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp); 382 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 383 if (!s->acpi_memory_hotplug.is_enabled) { 384 error_setg(errp, 385 "memory hotplug is not enabled: %s.memory-hotplug-support " 386 "is not set", object_get_typename(OBJECT(s))); 387 } 388 } else if ( 389 !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 390 error_setg(errp, "acpi: device pre plug request for not supported" 391 " device type: %s", object_get_typename(OBJECT(dev))); 392 } 393 } 394 395 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, 396 DeviceState *dev, Error **errp) 397 { 398 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 399 400 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 401 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 402 nvdimm_acpi_plug_cb(hotplug_dev, dev); 403 } else { 404 acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug, 405 dev, errp); 406 } 407 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 408 acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); 409 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 410 if (s->cpu_hotplug_legacy) { 411 legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp); 412 } else { 413 acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 414 } 415 } else { 416 g_assert_not_reached(); 417 } 418 } 419 420 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, 421 DeviceState *dev, Error **errp) 422 { 423 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 424 425 if (s->acpi_memory_hotplug.is_enabled && 426 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 427 acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug, 428 dev, errp); 429 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 430 acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug, 431 dev, errp); 432 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 433 !s->cpu_hotplug_legacy) { 434 acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 435 } else { 436 error_setg(errp, "acpi: device unplug request for not supported device" 437 " type: %s", object_get_typename(OBJECT(dev))); 438 } 439 } 440 441 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, 442 DeviceState *dev, Error **errp) 443 { 444 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 445 446 if (s->acpi_memory_hotplug.is_enabled && 447 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 448 acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); 449 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 450 acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, 451 errp); 452 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 453 !s->cpu_hotplug_legacy) { 454 acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); 455 } else { 456 error_setg(errp, "acpi: device unplug for not supported device" 457 " type: %s", object_get_typename(OBJECT(dev))); 458 } 459 } 460 461 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 462 { 463 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 464 PCIDevice *d = PCI_DEVICE(s); 465 MemoryRegion *io_as = pci_address_space_io(d); 466 uint8_t *pci_conf; 467 468 pci_conf = d->config; 469 pci_conf[0x5f] = 0x10 | 470 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 471 pci_conf[0x63] = 0x60; 472 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 473 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 474 } 475 476 static void piix4_pm_add_propeties(PIIX4PMState *s) 477 { 478 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 479 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 480 static const uint32_t gpe0_blk = GPE_BASE; 481 static const uint32_t gpe0_blk_len = GPE_LEN; 482 static const uint16_t sci_int = 9; 483 484 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 485 &acpi_enable_cmd, NULL); 486 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 487 &acpi_disable_cmd, NULL); 488 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 489 &gpe0_blk, NULL); 490 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 491 &gpe0_blk_len, NULL); 492 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 493 &sci_int, NULL); 494 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 495 &s->io_base, NULL); 496 } 497 498 static void piix4_pm_realize(PCIDevice *dev, Error **errp) 499 { 500 PIIX4PMState *s = PIIX4_PM(dev); 501 uint8_t *pci_conf; 502 503 pci_conf = dev->config; 504 pci_conf[0x06] = 0x80; 505 pci_conf[0x07] = 0x02; 506 pci_conf[0x09] = 0x00; 507 pci_conf[0x3d] = 0x01; // interrupt pin 1 508 509 /* APM */ 510 apm_init(dev, &s->apm, apm_ctrl_changed, s); 511 512 if (!s->smm_enabled) { 513 /* Mark SMM as already inited to prevent SMM from running. KVM does not 514 * support SMM mode. */ 515 pci_conf[0x5B] = 0x02; 516 } 517 518 /* XXX: which specification is used ? The i82731AB has different 519 mappings */ 520 pci_conf[0x90] = s->smb_io_base | 1; 521 pci_conf[0x91] = s->smb_io_base >> 8; 522 pci_conf[0xd2] = 0x09; 523 pm_smbus_init(DEVICE(dev), &s->smb, true); 524 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 525 memory_region_add_subregion(pci_address_space_io(dev), 526 s->smb_io_base, &s->smb.io); 527 528 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 529 memory_region_set_enabled(&s->io, false); 530 memory_region_add_subregion(pci_address_space_io(dev), 531 0, &s->io); 532 533 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 534 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 535 acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val); 536 acpi_gpe_init(&s->ar, GPE_LEN); 537 538 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 539 qemu_register_powerdown_notifier(&s->powerdown_notifier); 540 541 s->machine_ready.notify = piix4_pm_machine_ready; 542 qemu_add_machine_init_done_notifier(&s->machine_ready); 543 qemu_register_reset(piix4_reset, s); 544 545 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), 546 pci_get_bus(dev), s); 547 qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s), &error_abort); 548 549 piix4_pm_add_propeties(s); 550 } 551 552 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 553 qemu_irq sci_irq, qemu_irq smi_irq, 554 int smm_enabled, DeviceState **piix4_pm) 555 { 556 DeviceState *dev; 557 PIIX4PMState *s; 558 559 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); 560 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 561 if (piix4_pm) { 562 *piix4_pm = dev; 563 } 564 565 s = PIIX4_PM(dev); 566 s->irq = sci_irq; 567 s->smi_irq = smi_irq; 568 s->smm_enabled = smm_enabled; 569 if (xen_enabled()) { 570 s->use_acpi_pci_hotplug = false; 571 } 572 573 qdev_init_nofail(dev); 574 575 return s->smb.smbus; 576 } 577 578 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 579 { 580 PIIX4PMState *s = opaque; 581 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 582 583 trace_piix4_gpe_readb(addr, width, val); 584 return val; 585 } 586 587 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 588 unsigned width) 589 { 590 PIIX4PMState *s = opaque; 591 592 trace_piix4_gpe_writeb(addr, width, val); 593 acpi_gpe_ioport_writeb(&s->ar, addr, val); 594 acpi_update_sci(&s->ar, s->irq); 595 } 596 597 static const MemoryRegionOps piix4_gpe_ops = { 598 .read = gpe_readb, 599 .write = gpe_writeb, 600 .valid.min_access_size = 1, 601 .valid.max_access_size = 4, 602 .impl.min_access_size = 1, 603 .impl.max_access_size = 1, 604 .endianness = DEVICE_LITTLE_ENDIAN, 605 }; 606 607 608 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp) 609 { 610 PIIX4PMState *s = PIIX4_PM(obj); 611 612 return s->cpu_hotplug_legacy; 613 } 614 615 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp) 616 { 617 PIIX4PMState *s = PIIX4_PM(obj); 618 619 assert(!value); 620 if (s->cpu_hotplug_legacy && value == false) { 621 acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state, 622 PIIX4_CPU_HOTPLUG_IO_BASE); 623 } 624 s->cpu_hotplug_legacy = value; 625 } 626 627 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 628 PCIBus *bus, PIIX4PMState *s) 629 { 630 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 631 "acpi-gpe0", GPE_LEN); 632 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 633 634 acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, 635 s->use_acpi_pci_hotplug); 636 637 s->cpu_hotplug_legacy = true; 638 object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", 639 piix4_get_cpu_hotplug_legacy, 640 piix4_set_cpu_hotplug_legacy, 641 NULL); 642 legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, 643 PIIX4_CPU_HOTPLUG_IO_BASE); 644 645 if (s->acpi_memory_hotplug.is_enabled) { 646 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug, 647 ACPI_MEMORY_HOTPLUG_BASE); 648 } 649 } 650 651 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) 652 { 653 PIIX4PMState *s = PIIX4_PM(adev); 654 655 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); 656 if (!s->cpu_hotplug_legacy) { 657 acpi_cpu_ospm_status(&s->cpuhp_state, list); 658 } 659 } 660 661 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 662 { 663 PIIX4PMState *s = PIIX4_PM(adev); 664 665 acpi_send_gpe_event(&s->ar, s->irq, ev); 666 } 667 668 static Property piix4_pm_properties[] = { 669 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 670 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 671 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 672 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 673 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, 674 use_acpi_pci_hotplug, true), 675 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, 676 acpi_memory_hotplug.is_enabled, true), 677 DEFINE_PROP_END_OF_LIST(), 678 }; 679 680 static void piix4_pm_class_init(ObjectClass *klass, void *data) 681 { 682 DeviceClass *dc = DEVICE_CLASS(klass); 683 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 684 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 685 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 686 687 k->realize = piix4_pm_realize; 688 k->config_write = pm_write_config; 689 k->vendor_id = PCI_VENDOR_ID_INTEL; 690 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 691 k->revision = 0x03; 692 k->class_id = PCI_CLASS_BRIDGE_OTHER; 693 dc->desc = "PM"; 694 dc->vmsd = &vmstate_acpi; 695 dc->props = piix4_pm_properties; 696 /* 697 * Reason: part of PIIX4 southbridge, needs to be wired up, 698 * e.g. by mips_malta_init() 699 */ 700 dc->user_creatable = false; 701 dc->hotpluggable = false; 702 hc->pre_plug = piix4_device_pre_plug_cb; 703 hc->plug = piix4_device_plug_cb; 704 hc->unplug_request = piix4_device_unplug_request_cb; 705 hc->unplug = piix4_device_unplug_cb; 706 adevc->ospm_status = piix4_ospm_status; 707 adevc->send_event = piix4_send_gpe; 708 adevc->madt_cpu = pc_madt_cpu_entry; 709 } 710 711 static const TypeInfo piix4_pm_info = { 712 .name = TYPE_PIIX4_PM, 713 .parent = TYPE_PCI_DEVICE, 714 .instance_size = sizeof(PIIX4PMState), 715 .class_init = piix4_pm_class_init, 716 .interfaces = (InterfaceInfo[]) { 717 { TYPE_HOTPLUG_HANDLER }, 718 { TYPE_ACPI_DEVICE_IF }, 719 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 720 { } 721 } 722 }; 723 724 static void piix4_pm_register_types(void) 725 { 726 type_register_static(&piix4_pm_info); 727 } 728 729 type_init(piix4_pm_register_types) 730