1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2.1 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/i386/pc.h" 24 #include "hw/southbridge/piix.h" 25 #include "hw/irq.h" 26 #include "hw/isa/apm.h" 27 #include "hw/i2c/pm_smbus.h" 28 #include "hw/pci/pci.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/acpi/acpi.h" 31 #include "sysemu/runstate.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/xen.h" 34 #include "qapi/error.h" 35 #include "qemu/range.h" 36 #include "exec/address-spaces.h" 37 #include "hw/acpi/pcihp.h" 38 #include "hw/acpi/cpu_hotplug.h" 39 #include "hw/acpi/cpu.h" 40 #include "hw/hotplug.h" 41 #include "hw/mem/pc-dimm.h" 42 #include "hw/mem/nvdimm.h" 43 #include "hw/acpi/memory_hotplug.h" 44 #include "hw/acpi/acpi_dev_interface.h" 45 #include "migration/vmstate.h" 46 #include "hw/core/cpu.h" 47 #include "trace.h" 48 #include "qom/object.h" 49 50 #define GPE_BASE 0xafe0 51 #define GPE_LEN 4 52 53 struct pci_status { 54 uint32_t up; /* deprecated, maintained for migration compatibility */ 55 uint32_t down; 56 }; 57 58 struct PIIX4PMState { 59 /*< private >*/ 60 PCIDevice parent_obj; 61 /*< public >*/ 62 63 MemoryRegion io; 64 uint32_t io_base; 65 66 MemoryRegion io_gpe; 67 ACPIREGS ar; 68 69 APMState apm; 70 71 PMSMBus smb; 72 uint32_t smb_io_base; 73 74 qemu_irq irq; 75 qemu_irq smi_irq; 76 int smm_enabled; 77 Notifier machine_ready; 78 Notifier powerdown_notifier; 79 80 AcpiPciHpState acpi_pci_hotplug; 81 bool use_acpi_hotplug_bridge; 82 bool use_acpi_root_pci_hotplug; 83 84 uint8_t disable_s3; 85 uint8_t disable_s4; 86 uint8_t s4_val; 87 88 bool cpu_hotplug_legacy; 89 AcpiCpuHotplug gpe_cpu; 90 CPUHotplugState cpuhp_state; 91 92 MemHotplugState acpi_memory_hotplug; 93 }; 94 95 OBJECT_DECLARE_SIMPLE_TYPE(PIIX4PMState, PIIX4_PM) 96 97 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 98 PCIBus *bus, PIIX4PMState *s); 99 100 #define ACPI_ENABLE 0xf1 101 #define ACPI_DISABLE 0xf0 102 103 static void pm_tmr_timer(ACPIREGS *ar) 104 { 105 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 106 acpi_update_sci(&s->ar, s->irq); 107 } 108 109 static void apm_ctrl_changed(uint32_t val, void *arg) 110 { 111 PIIX4PMState *s = arg; 112 PCIDevice *d = PCI_DEVICE(s); 113 114 /* ACPI specs 3.0, 4.7.2.5 */ 115 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 116 if (val == ACPI_ENABLE || val == ACPI_DISABLE) { 117 return; 118 } 119 120 if (d->config[0x5b] & (1 << 1)) { 121 if (s->smi_irq) { 122 qemu_irq_raise(s->smi_irq); 123 } 124 } 125 } 126 127 static void pm_io_space_update(PIIX4PMState *s) 128 { 129 PCIDevice *d = PCI_DEVICE(s); 130 131 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 132 s->io_base &= 0xffc0; 133 134 memory_region_transaction_begin(); 135 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 136 memory_region_set_address(&s->io, s->io_base); 137 memory_region_transaction_commit(); 138 } 139 140 static void smbus_io_space_update(PIIX4PMState *s) 141 { 142 PCIDevice *d = PCI_DEVICE(s); 143 144 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 145 s->smb_io_base &= 0xffc0; 146 147 memory_region_transaction_begin(); 148 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 149 memory_region_set_address(&s->smb.io, s->smb_io_base); 150 memory_region_transaction_commit(); 151 } 152 153 static void pm_write_config(PCIDevice *d, 154 uint32_t address, uint32_t val, int len) 155 { 156 pci_default_write_config(d, address, val, len); 157 if (range_covers_byte(address, len, 0x80) || 158 ranges_overlap(address, len, 0x40, 4)) { 159 pm_io_space_update((PIIX4PMState *)d); 160 } 161 if (range_covers_byte(address, len, 0xd2) || 162 ranges_overlap(address, len, 0x90, 4)) { 163 smbus_io_space_update((PIIX4PMState *)d); 164 } 165 } 166 167 static int vmstate_acpi_post_load(void *opaque, int version_id) 168 { 169 PIIX4PMState *s = opaque; 170 171 pm_io_space_update(s); 172 smbus_io_space_update(s); 173 return 0; 174 } 175 176 #define VMSTATE_GPE_ARRAY(_field, _state) \ 177 { \ 178 .name = (stringify(_field)), \ 179 .version_id = 0, \ 180 .info = &vmstate_info_uint16, \ 181 .size = sizeof(uint16_t), \ 182 .flags = VMS_SINGLE | VMS_POINTER, \ 183 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 184 } 185 186 static const VMStateDescription vmstate_gpe = { 187 .name = "gpe", 188 .version_id = 1, 189 .minimum_version_id = 1, 190 .fields = (VMStateField[]) { 191 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 192 VMSTATE_GPE_ARRAY(en, ACPIGPE), 193 VMSTATE_END_OF_LIST() 194 } 195 }; 196 197 static const VMStateDescription vmstate_pci_status = { 198 .name = "pci_status", 199 .version_id = 1, 200 .minimum_version_id = 1, 201 .fields = (VMStateField[]) { 202 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), 203 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), 204 VMSTATE_END_OF_LIST() 205 } 206 }; 207 208 static bool vmstate_test_use_acpi_hotplug_bridge(void *opaque, int version_id) 209 { 210 PIIX4PMState *s = opaque; 211 return s->use_acpi_hotplug_bridge; 212 } 213 214 static bool vmstate_test_no_use_acpi_hotplug_bridge(void *opaque, 215 int version_id) 216 { 217 PIIX4PMState *s = opaque; 218 return !s->use_acpi_hotplug_bridge; 219 } 220 221 static bool vmstate_test_use_memhp(void *opaque) 222 { 223 PIIX4PMState *s = opaque; 224 return s->acpi_memory_hotplug.is_enabled; 225 } 226 227 static const VMStateDescription vmstate_memhp_state = { 228 .name = "piix4_pm/memhp", 229 .version_id = 1, 230 .minimum_version_id = 1, 231 .minimum_version_id_old = 1, 232 .needed = vmstate_test_use_memhp, 233 .fields = (VMStateField[]) { 234 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), 235 VMSTATE_END_OF_LIST() 236 } 237 }; 238 239 static bool vmstate_test_use_cpuhp(void *opaque) 240 { 241 PIIX4PMState *s = opaque; 242 return !s->cpu_hotplug_legacy; 243 } 244 245 static int vmstate_cpuhp_pre_load(void *opaque) 246 { 247 Object *obj = OBJECT(opaque); 248 object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort); 249 return 0; 250 } 251 252 static const VMStateDescription vmstate_cpuhp_state = { 253 .name = "piix4_pm/cpuhp", 254 .version_id = 1, 255 .minimum_version_id = 1, 256 .minimum_version_id_old = 1, 257 .needed = vmstate_test_use_cpuhp, 258 .pre_load = vmstate_cpuhp_pre_load, 259 .fields = (VMStateField[]) { 260 VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), 261 VMSTATE_END_OF_LIST() 262 } 263 }; 264 265 static bool piix4_vmstate_need_smbus(void *opaque, int version_id) 266 { 267 return pm_smbus_vmstate_needed(); 268 } 269 270 /* qemu-kvm 1.2 uses version 3 but advertised as 2 271 * To support incoming qemu-kvm 1.2 migration, change version_id 272 * and minimum_version_id to 2 below (which breaks migration from 273 * qemu 1.2). 274 * 275 */ 276 static const VMStateDescription vmstate_acpi = { 277 .name = "piix4_pm", 278 .version_id = 3, 279 .minimum_version_id = 3, 280 .post_load = vmstate_acpi_post_load, 281 .fields = (VMStateField[]) { 282 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 283 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 284 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 285 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 286 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 287 VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3, 288 pmsmb_vmstate, PMSMBus), 289 VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), 290 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 291 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 292 VMSTATE_STRUCT_TEST( 293 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 294 PIIX4PMState, 295 vmstate_test_no_use_acpi_hotplug_bridge, 296 2, vmstate_pci_status, 297 struct AcpiPciHpPciStatus), 298 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 299 vmstate_test_use_acpi_hotplug_bridge), 300 VMSTATE_END_OF_LIST() 301 }, 302 .subsections = (const VMStateDescription*[]) { 303 &vmstate_memhp_state, 304 &vmstate_cpuhp_state, 305 NULL 306 } 307 }; 308 309 static void piix4_pm_reset(DeviceState *dev) 310 { 311 PIIX4PMState *s = PIIX4_PM(dev); 312 PCIDevice *d = PCI_DEVICE(s); 313 uint8_t *pci_conf = d->config; 314 315 pci_conf[0x58] = 0; 316 pci_conf[0x59] = 0; 317 pci_conf[0x5a] = 0; 318 pci_conf[0x5b] = 0; 319 320 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 321 pci_conf[0x80] = 0; 322 323 if (!s->smm_enabled) { 324 /* Mark SMM as already inited (until KVM supports SMM). */ 325 pci_conf[0x5B] = 0x02; 326 } 327 pm_io_space_update(s); 328 acpi_pcihp_reset(&s->acpi_pci_hotplug, !s->use_acpi_root_pci_hotplug); 329 } 330 331 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 332 { 333 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 334 335 assert(s != NULL); 336 acpi_pm1_evt_power_down(&s->ar); 337 } 338 339 static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev, 340 DeviceState *dev, Error **errp) 341 { 342 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 343 344 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 345 acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp); 346 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 347 if (!s->acpi_memory_hotplug.is_enabled) { 348 error_setg(errp, 349 "memory hotplug is not enabled: %s.memory-hotplug-support " 350 "is not set", object_get_typename(OBJECT(s))); 351 } 352 } else if ( 353 !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 354 error_setg(errp, "acpi: device pre plug request for not supported" 355 " device type: %s", object_get_typename(OBJECT(dev))); 356 } 357 } 358 359 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, 360 DeviceState *dev, Error **errp) 361 { 362 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 363 364 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 365 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 366 nvdimm_acpi_plug_cb(hotplug_dev, dev); 367 } else { 368 acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug, 369 dev, errp); 370 } 371 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 372 acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); 373 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 374 if (s->cpu_hotplug_legacy) { 375 legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp); 376 } else { 377 acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 378 } 379 } else { 380 g_assert_not_reached(); 381 } 382 } 383 384 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, 385 DeviceState *dev, Error **errp) 386 { 387 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 388 389 if (s->acpi_memory_hotplug.is_enabled && 390 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 391 acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug, 392 dev, errp); 393 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 394 acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug, 395 dev, errp); 396 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 397 !s->cpu_hotplug_legacy) { 398 acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 399 } else { 400 error_setg(errp, "acpi: device unplug request for not supported device" 401 " type: %s", object_get_typename(OBJECT(dev))); 402 } 403 } 404 405 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, 406 DeviceState *dev, Error **errp) 407 { 408 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 409 410 if (s->acpi_memory_hotplug.is_enabled && 411 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 412 acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); 413 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 414 acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, 415 errp); 416 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 417 !s->cpu_hotplug_legacy) { 418 acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); 419 } else { 420 error_setg(errp, "acpi: device unplug for not supported device" 421 " type: %s", object_get_typename(OBJECT(dev))); 422 } 423 } 424 425 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 426 { 427 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 428 PCIDevice *d = PCI_DEVICE(s); 429 MemoryRegion *io_as = pci_address_space_io(d); 430 uint8_t *pci_conf; 431 432 pci_conf = d->config; 433 pci_conf[0x5f] = 0x10 | 434 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 435 pci_conf[0x63] = 0x60; 436 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 437 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 438 } 439 440 static void piix4_pm_add_properties(PIIX4PMState *s) 441 { 442 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 443 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 444 static const uint32_t gpe0_blk = GPE_BASE; 445 static const uint32_t gpe0_blk_len = GPE_LEN; 446 static const uint16_t sci_int = 9; 447 448 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 449 &acpi_enable_cmd, OBJ_PROP_FLAG_READ); 450 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 451 &acpi_disable_cmd, OBJ_PROP_FLAG_READ); 452 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 453 &gpe0_blk, OBJ_PROP_FLAG_READ); 454 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 455 &gpe0_blk_len, OBJ_PROP_FLAG_READ); 456 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 457 &sci_int, OBJ_PROP_FLAG_READ); 458 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 459 &s->io_base, OBJ_PROP_FLAG_READ); 460 } 461 462 static void piix4_pm_realize(PCIDevice *dev, Error **errp) 463 { 464 PIIX4PMState *s = PIIX4_PM(dev); 465 uint8_t *pci_conf; 466 467 pci_conf = dev->config; 468 pci_conf[0x06] = 0x80; 469 pci_conf[0x07] = 0x02; 470 pci_conf[0x09] = 0x00; 471 pci_conf[0x3d] = 0x01; // interrupt pin 1 472 473 /* APM */ 474 apm_init(dev, &s->apm, apm_ctrl_changed, s); 475 476 if (!s->smm_enabled) { 477 /* Mark SMM as already inited to prevent SMM from running. KVM does not 478 * support SMM mode. */ 479 pci_conf[0x5B] = 0x02; 480 } 481 482 /* XXX: which specification is used ? The i82731AB has different 483 mappings */ 484 pci_conf[0x90] = s->smb_io_base | 1; 485 pci_conf[0x91] = s->smb_io_base >> 8; 486 pci_conf[0xd2] = 0x09; 487 pm_smbus_init(DEVICE(dev), &s->smb, true); 488 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 489 memory_region_add_subregion(pci_address_space_io(dev), 490 s->smb_io_base, &s->smb.io); 491 492 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 493 memory_region_set_enabled(&s->io, false); 494 memory_region_add_subregion(pci_address_space_io(dev), 495 0, &s->io); 496 497 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 498 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 499 acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val); 500 acpi_gpe_init(&s->ar, GPE_LEN); 501 502 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 503 qemu_register_powerdown_notifier(&s->powerdown_notifier); 504 505 s->machine_ready.notify = piix4_pm_machine_ready; 506 qemu_add_machine_init_done_notifier(&s->machine_ready); 507 508 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), 509 pci_get_bus(dev), s); 510 qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s)); 511 512 piix4_pm_add_properties(s); 513 } 514 515 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 516 qemu_irq sci_irq, qemu_irq smi_irq, 517 int smm_enabled, DeviceState **piix4_pm) 518 { 519 PCIDevice *pci_dev; 520 DeviceState *dev; 521 PIIX4PMState *s; 522 523 pci_dev = pci_new(devfn, TYPE_PIIX4_PM); 524 dev = DEVICE(pci_dev); 525 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 526 if (piix4_pm) { 527 *piix4_pm = dev; 528 } 529 530 s = PIIX4_PM(dev); 531 s->irq = sci_irq; 532 s->smi_irq = smi_irq; 533 s->smm_enabled = smm_enabled; 534 if (xen_enabled()) { 535 s->use_acpi_hotplug_bridge = false; 536 } 537 538 pci_realize_and_unref(pci_dev, bus, &error_fatal); 539 540 return s->smb.smbus; 541 } 542 543 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 544 { 545 PIIX4PMState *s = opaque; 546 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 547 548 trace_piix4_gpe_readb(addr, width, val); 549 return val; 550 } 551 552 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 553 unsigned width) 554 { 555 PIIX4PMState *s = opaque; 556 557 trace_piix4_gpe_writeb(addr, width, val); 558 acpi_gpe_ioport_writeb(&s->ar, addr, val); 559 acpi_update_sci(&s->ar, s->irq); 560 } 561 562 static const MemoryRegionOps piix4_gpe_ops = { 563 .read = gpe_readb, 564 .write = gpe_writeb, 565 .valid.min_access_size = 1, 566 .valid.max_access_size = 4, 567 .impl.min_access_size = 1, 568 .impl.max_access_size = 1, 569 .endianness = DEVICE_LITTLE_ENDIAN, 570 }; 571 572 573 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp) 574 { 575 PIIX4PMState *s = PIIX4_PM(obj); 576 577 return s->cpu_hotplug_legacy; 578 } 579 580 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp) 581 { 582 PIIX4PMState *s = PIIX4_PM(obj); 583 584 assert(!value); 585 if (s->cpu_hotplug_legacy && value == false) { 586 acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state, 587 PIIX4_CPU_HOTPLUG_IO_BASE); 588 } 589 s->cpu_hotplug_legacy = value; 590 } 591 592 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 593 PCIBus *bus, PIIX4PMState *s) 594 { 595 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 596 "acpi-gpe0", GPE_LEN); 597 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 598 599 if (s->use_acpi_hotplug_bridge || s->use_acpi_root_pci_hotplug) { 600 acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, 601 s->use_acpi_hotplug_bridge); 602 } 603 604 s->cpu_hotplug_legacy = true; 605 object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", 606 piix4_get_cpu_hotplug_legacy, 607 piix4_set_cpu_hotplug_legacy); 608 legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, 609 PIIX4_CPU_HOTPLUG_IO_BASE); 610 611 if (s->acpi_memory_hotplug.is_enabled) { 612 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug, 613 ACPI_MEMORY_HOTPLUG_BASE); 614 } 615 } 616 617 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) 618 { 619 PIIX4PMState *s = PIIX4_PM(adev); 620 621 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); 622 if (!s->cpu_hotplug_legacy) { 623 acpi_cpu_ospm_status(&s->cpuhp_state, list); 624 } 625 } 626 627 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 628 { 629 PIIX4PMState *s = PIIX4_PM(adev); 630 631 acpi_send_gpe_event(&s->ar, s->irq, ev); 632 } 633 634 static Property piix4_pm_properties[] = { 635 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 636 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 637 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 638 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 639 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, 640 use_acpi_hotplug_bridge, true), 641 DEFINE_PROP_BOOL("acpi-root-pci-hotplug", PIIX4PMState, 642 use_acpi_root_pci_hotplug, true), 643 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, 644 acpi_memory_hotplug.is_enabled, true), 645 DEFINE_PROP_END_OF_LIST(), 646 }; 647 648 static void piix4_pm_class_init(ObjectClass *klass, void *data) 649 { 650 DeviceClass *dc = DEVICE_CLASS(klass); 651 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 652 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 653 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 654 655 k->realize = piix4_pm_realize; 656 k->config_write = pm_write_config; 657 k->vendor_id = PCI_VENDOR_ID_INTEL; 658 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 659 k->revision = 0x03; 660 k->class_id = PCI_CLASS_BRIDGE_OTHER; 661 dc->reset = piix4_pm_reset; 662 dc->desc = "PM"; 663 dc->vmsd = &vmstate_acpi; 664 device_class_set_props(dc, piix4_pm_properties); 665 /* 666 * Reason: part of PIIX4 southbridge, needs to be wired up, 667 * e.g. by mips_malta_init() 668 */ 669 dc->user_creatable = false; 670 dc->hotpluggable = false; 671 hc->pre_plug = piix4_device_pre_plug_cb; 672 hc->plug = piix4_device_plug_cb; 673 hc->unplug_request = piix4_device_unplug_request_cb; 674 hc->unplug = piix4_device_unplug_cb; 675 adevc->ospm_status = piix4_ospm_status; 676 adevc->send_event = piix4_send_gpe; 677 adevc->madt_cpu = pc_madt_cpu_entry; 678 } 679 680 static const TypeInfo piix4_pm_info = { 681 .name = TYPE_PIIX4_PM, 682 .parent = TYPE_PCI_DEVICE, 683 .instance_size = sizeof(PIIX4PMState), 684 .class_init = piix4_pm_class_init, 685 .interfaces = (InterfaceInfo[]) { 686 { TYPE_HOTPLUG_HANDLER }, 687 { TYPE_ACPI_DEVICE_IF }, 688 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 689 { } 690 } 691 }; 692 693 static void piix4_pm_register_types(void) 694 { 695 type_register_static(&piix4_pm_info); 696 } 697 698 type_init(piix4_pm_register_types) 699