1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 #include "hw/hw.h" 22 #include "hw/i386/pc.h" 23 #include "hw/isa/apm.h" 24 #include "hw/i2c/pm_smbus.h" 25 #include "hw/pci/pci.h" 26 #include "hw/acpi/acpi.h" 27 #include "sysemu/sysemu.h" 28 #include "qemu/range.h" 29 #include "exec/ioport.h" 30 #include "hw/nvram/fw_cfg.h" 31 #include "exec/address-spaces.h" 32 #include "hw/acpi/piix4.h" 33 #include "hw/acpi/pcihp.h" 34 #include "hw/acpi/cpu_hotplug.h" 35 #include "hw/hotplug.h" 36 #include "hw/mem/pc-dimm.h" 37 #include "hw/acpi/memory_hotplug.h" 38 #include "hw/acpi/acpi_dev_interface.h" 39 40 //#define DEBUG 41 42 #ifdef DEBUG 43 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 44 #else 45 # define PIIX4_DPRINTF(format, ...) do { } while (0) 46 #endif 47 48 #define GPE_BASE 0xafe0 49 #define GPE_LEN 4 50 51 struct pci_status { 52 uint32_t up; /* deprecated, maintained for migration compatibility */ 53 uint32_t down; 54 }; 55 56 typedef struct PIIX4PMState { 57 /*< private >*/ 58 PCIDevice parent_obj; 59 /*< public >*/ 60 61 MemoryRegion io; 62 uint32_t io_base; 63 64 MemoryRegion io_gpe; 65 ACPIREGS ar; 66 67 APMState apm; 68 69 PMSMBus smb; 70 uint32_t smb_io_base; 71 72 qemu_irq irq; 73 qemu_irq smi_irq; 74 int kvm_enabled; 75 Notifier machine_ready; 76 Notifier powerdown_notifier; 77 78 AcpiPciHpState acpi_pci_hotplug; 79 bool use_acpi_pci_hotplug; 80 81 uint8_t disable_s3; 82 uint8_t disable_s4; 83 uint8_t s4_val; 84 85 AcpiCpuHotplug gpe_cpu; 86 Notifier cpu_added_notifier; 87 88 MemHotplugState acpi_memory_hotplug; 89 } PIIX4PMState; 90 91 #define TYPE_PIIX4_PM "PIIX4_PM" 92 93 #define PIIX4_PM(obj) \ 94 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) 95 96 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 97 PCIBus *bus, PIIX4PMState *s); 98 99 #define ACPI_ENABLE 0xf1 100 #define ACPI_DISABLE 0xf0 101 102 static void pm_tmr_timer(ACPIREGS *ar) 103 { 104 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 105 acpi_update_sci(&s->ar, s->irq); 106 } 107 108 static void apm_ctrl_changed(uint32_t val, void *arg) 109 { 110 PIIX4PMState *s = arg; 111 PCIDevice *d = PCI_DEVICE(s); 112 113 /* ACPI specs 3.0, 4.7.2.5 */ 114 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 115 116 if (d->config[0x5b] & (1 << 1)) { 117 if (s->smi_irq) { 118 qemu_irq_raise(s->smi_irq); 119 } 120 } 121 } 122 123 static void pm_io_space_update(PIIX4PMState *s) 124 { 125 PCIDevice *d = PCI_DEVICE(s); 126 127 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 128 s->io_base &= 0xffc0; 129 130 memory_region_transaction_begin(); 131 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 132 memory_region_set_address(&s->io, s->io_base); 133 memory_region_transaction_commit(); 134 } 135 136 static void smbus_io_space_update(PIIX4PMState *s) 137 { 138 PCIDevice *d = PCI_DEVICE(s); 139 140 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 141 s->smb_io_base &= 0xffc0; 142 143 memory_region_transaction_begin(); 144 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 145 memory_region_set_address(&s->smb.io, s->smb_io_base); 146 memory_region_transaction_commit(); 147 } 148 149 static void pm_write_config(PCIDevice *d, 150 uint32_t address, uint32_t val, int len) 151 { 152 pci_default_write_config(d, address, val, len); 153 if (range_covers_byte(address, len, 0x80) || 154 ranges_overlap(address, len, 0x40, 4)) { 155 pm_io_space_update((PIIX4PMState *)d); 156 } 157 if (range_covers_byte(address, len, 0xd2) || 158 ranges_overlap(address, len, 0x90, 4)) { 159 smbus_io_space_update((PIIX4PMState *)d); 160 } 161 } 162 163 static int vmstate_acpi_post_load(void *opaque, int version_id) 164 { 165 PIIX4PMState *s = opaque; 166 167 pm_io_space_update(s); 168 return 0; 169 } 170 171 #define VMSTATE_GPE_ARRAY(_field, _state) \ 172 { \ 173 .name = (stringify(_field)), \ 174 .version_id = 0, \ 175 .info = &vmstate_info_uint16, \ 176 .size = sizeof(uint16_t), \ 177 .flags = VMS_SINGLE | VMS_POINTER, \ 178 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 179 } 180 181 static const VMStateDescription vmstate_gpe = { 182 .name = "gpe", 183 .version_id = 1, 184 .minimum_version_id = 1, 185 .fields = (VMStateField[]) { 186 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 187 VMSTATE_GPE_ARRAY(en, ACPIGPE), 188 VMSTATE_END_OF_LIST() 189 } 190 }; 191 192 static const VMStateDescription vmstate_pci_status = { 193 .name = "pci_status", 194 .version_id = 1, 195 .minimum_version_id = 1, 196 .fields = (VMStateField[]) { 197 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), 198 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), 199 VMSTATE_END_OF_LIST() 200 } 201 }; 202 203 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) 204 { 205 PIIX4PMState *s = opaque; 206 int ret, i; 207 uint16_t temp; 208 209 ret = pci_device_load(PCI_DEVICE(s), f); 210 if (ret < 0) { 211 return ret; 212 } 213 qemu_get_be16s(f, &s->ar.pm1.evt.sts); 214 qemu_get_be16s(f, &s->ar.pm1.evt.en); 215 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); 216 217 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); 218 if (ret) { 219 return ret; 220 } 221 222 timer_get(f, s->ar.tmr.timer); 223 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); 224 225 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); 226 for (i = 0; i < 3; i++) { 227 qemu_get_be16s(f, &temp); 228 } 229 230 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); 231 for (i = 0; i < 3; i++) { 232 qemu_get_be16s(f, &temp); 233 } 234 235 ret = vmstate_load_state(f, &vmstate_pci_status, 236 &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1); 237 return ret; 238 } 239 240 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) 241 { 242 PIIX4PMState *s = opaque; 243 return s->use_acpi_pci_hotplug; 244 } 245 246 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id) 247 { 248 PIIX4PMState *s = opaque; 249 return !s->use_acpi_pci_hotplug; 250 } 251 252 static bool vmstate_test_use_memhp(void *opaque) 253 { 254 PIIX4PMState *s = opaque; 255 return s->acpi_memory_hotplug.is_enabled; 256 } 257 258 static const VMStateDescription vmstate_memhp_state = { 259 .name = "piix4_pm/memhp", 260 .version_id = 1, 261 .minimum_version_id = 1, 262 .minimum_version_id_old = 1, 263 .fields = (VMStateField[]) { 264 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), 265 VMSTATE_END_OF_LIST() 266 } 267 }; 268 269 /* qemu-kvm 1.2 uses version 3 but advertised as 2 270 * To support incoming qemu-kvm 1.2 migration, change version_id 271 * and minimum_version_id to 2 below (which breaks migration from 272 * qemu 1.2). 273 * 274 */ 275 static const VMStateDescription vmstate_acpi = { 276 .name = "piix4_pm", 277 .version_id = 3, 278 .minimum_version_id = 3, 279 .minimum_version_id_old = 1, 280 .load_state_old = acpi_load_old, 281 .post_load = vmstate_acpi_post_load, 282 .fields = (VMStateField[]) { 283 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 284 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 285 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 286 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 287 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 288 VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), 289 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 290 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 291 VMSTATE_STRUCT_TEST( 292 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 293 PIIX4PMState, 294 vmstate_test_no_use_acpi_pci_hotplug, 295 2, vmstate_pci_status, 296 struct AcpiPciHpPciStatus), 297 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 298 vmstate_test_use_acpi_pci_hotplug), 299 VMSTATE_END_OF_LIST() 300 }, 301 .subsections = (VMStateSubsection[]) { 302 { 303 .vmsd = &vmstate_memhp_state, 304 .needed = vmstate_test_use_memhp, 305 }, 306 VMSTATE_END_OF_LIST() 307 } 308 }; 309 310 static void piix4_reset(void *opaque) 311 { 312 PIIX4PMState *s = opaque; 313 PCIDevice *d = PCI_DEVICE(s); 314 uint8_t *pci_conf = d->config; 315 316 pci_conf[0x58] = 0; 317 pci_conf[0x59] = 0; 318 pci_conf[0x5a] = 0; 319 pci_conf[0x5b] = 0; 320 321 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 322 pci_conf[0x80] = 0; 323 324 if (s->kvm_enabled) { 325 /* Mark SMM as already inited (until KVM supports SMM). */ 326 pci_conf[0x5B] = 0x02; 327 } 328 pm_io_space_update(s); 329 acpi_pcihp_reset(&s->acpi_pci_hotplug); 330 } 331 332 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 333 { 334 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 335 336 assert(s != NULL); 337 acpi_pm1_evt_power_down(&s->ar); 338 } 339 340 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, 341 DeviceState *dev, Error **errp) 342 { 343 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 344 345 if (s->acpi_memory_hotplug.is_enabled && 346 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 347 acpi_memory_plug_cb(&s->ar, s->irq, &s->acpi_memory_hotplug, dev, errp); 348 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 349 acpi_pcihp_device_plug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev, 350 errp); 351 } else { 352 error_setg(errp, "acpi: device plug request for not supported device" 353 " type: %s", object_get_typename(OBJECT(dev))); 354 } 355 } 356 357 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, 358 DeviceState *dev, Error **errp) 359 { 360 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 361 362 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 363 acpi_pcihp_device_unplug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev, 364 errp); 365 } else { 366 error_setg(errp, "acpi: device unplug request for not supported device" 367 " type: %s", object_get_typename(OBJECT(dev))); 368 } 369 } 370 371 static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque) 372 { 373 PIIX4PMState *s = opaque; 374 375 qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort); 376 } 377 378 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 379 { 380 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 381 PCIDevice *d = PCI_DEVICE(s); 382 MemoryRegion *io_as = pci_address_space_io(d); 383 uint8_t *pci_conf; 384 385 pci_conf = d->config; 386 pci_conf[0x5f] = 0x10 | 387 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 388 pci_conf[0x63] = 0x60; 389 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 390 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 391 392 if (s->use_acpi_pci_hotplug) { 393 pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s); 394 } else { 395 piix4_update_bus_hotplug(d->bus, s); 396 } 397 } 398 399 static void piix4_pm_add_propeties(PIIX4PMState *s) 400 { 401 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 402 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 403 static const uint32_t gpe0_blk = GPE_BASE; 404 static const uint32_t gpe0_blk_len = GPE_LEN; 405 static const uint16_t sci_int = 9; 406 407 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 408 &acpi_enable_cmd, NULL); 409 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 410 &acpi_disable_cmd, NULL); 411 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 412 &gpe0_blk, NULL); 413 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 414 &gpe0_blk_len, NULL); 415 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 416 &sci_int, NULL); 417 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 418 &s->io_base, NULL); 419 } 420 421 static int piix4_pm_initfn(PCIDevice *dev) 422 { 423 PIIX4PMState *s = PIIX4_PM(dev); 424 uint8_t *pci_conf; 425 426 pci_conf = dev->config; 427 pci_conf[0x06] = 0x80; 428 pci_conf[0x07] = 0x02; 429 pci_conf[0x09] = 0x00; 430 pci_conf[0x3d] = 0x01; // interrupt pin 1 431 432 /* APM */ 433 apm_init(dev, &s->apm, apm_ctrl_changed, s); 434 435 if (s->kvm_enabled) { 436 /* Mark SMM as already inited to prevent SMM from running. KVM does not 437 * support SMM mode. */ 438 pci_conf[0x5B] = 0x02; 439 } 440 441 /* XXX: which specification is used ? The i82731AB has different 442 mappings */ 443 pci_conf[0x90] = s->smb_io_base | 1; 444 pci_conf[0x91] = s->smb_io_base >> 8; 445 pci_conf[0xd2] = 0x09; 446 pm_smbus_init(DEVICE(dev), &s->smb); 447 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 448 memory_region_add_subregion(pci_address_space_io(dev), 449 s->smb_io_base, &s->smb.io); 450 451 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 452 memory_region_set_enabled(&s->io, false); 453 memory_region_add_subregion(pci_address_space_io(dev), 454 0, &s->io); 455 456 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 457 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 458 acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val); 459 acpi_gpe_init(&s->ar, GPE_LEN); 460 461 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 462 qemu_register_powerdown_notifier(&s->powerdown_notifier); 463 464 s->machine_ready.notify = piix4_pm_machine_ready; 465 qemu_add_machine_init_done_notifier(&s->machine_ready); 466 qemu_register_reset(piix4_reset, s); 467 468 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s); 469 470 piix4_pm_add_propeties(s); 471 return 0; 472 } 473 474 Object *piix4_pm_find(void) 475 { 476 bool ambig; 477 Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig); 478 479 if (ambig || !o) { 480 return NULL; 481 } 482 return o; 483 } 484 485 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 486 qemu_irq sci_irq, qemu_irq smi_irq, 487 int kvm_enabled, FWCfgState *fw_cfg, 488 DeviceState **piix4_pm) 489 { 490 DeviceState *dev; 491 PIIX4PMState *s; 492 493 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); 494 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 495 if (piix4_pm) { 496 *piix4_pm = dev; 497 } 498 499 s = PIIX4_PM(dev); 500 s->irq = sci_irq; 501 s->smi_irq = smi_irq; 502 s->kvm_enabled = kvm_enabled; 503 504 qdev_init_nofail(dev); 505 506 if (fw_cfg) { 507 uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; 508 suspend[3] = 1 | ((!s->disable_s3) << 7); 509 suspend[4] = s->s4_val | ((!s->disable_s4) << 7); 510 511 fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); 512 } 513 514 return s->smb.smbus; 515 } 516 517 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 518 { 519 PIIX4PMState *s = opaque; 520 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 521 522 PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); 523 return val; 524 } 525 526 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 527 unsigned width) 528 { 529 PIIX4PMState *s = opaque; 530 531 acpi_gpe_ioport_writeb(&s->ar, addr, val); 532 acpi_update_sci(&s->ar, s->irq); 533 534 PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); 535 } 536 537 static const MemoryRegionOps piix4_gpe_ops = { 538 .read = gpe_readb, 539 .write = gpe_writeb, 540 .valid.min_access_size = 1, 541 .valid.max_access_size = 4, 542 .impl.min_access_size = 1, 543 .impl.max_access_size = 1, 544 .endianness = DEVICE_LITTLE_ENDIAN, 545 }; 546 547 static void piix4_cpu_added_req(Notifier *n, void *opaque) 548 { 549 PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier); 550 551 assert(s != NULL); 552 AcpiCpuHotplug_add(&s->ar.gpe, &s->gpe_cpu, CPU(opaque)); 553 acpi_update_sci(&s->ar, s->irq); 554 } 555 556 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 557 PCIBus *bus, PIIX4PMState *s) 558 { 559 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 560 "acpi-gpe0", GPE_LEN); 561 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 562 563 acpi_pcihp_init(&s->acpi_pci_hotplug, bus, parent, 564 s->use_acpi_pci_hotplug); 565 566 AcpiCpuHotplug_init(parent, OBJECT(s), &s->gpe_cpu, 567 PIIX4_CPU_HOTPLUG_IO_BASE); 568 s->cpu_added_notifier.notify = piix4_cpu_added_req; 569 qemu_register_cpu_added_notifier(&s->cpu_added_notifier); 570 571 if (s->acpi_memory_hotplug.is_enabled) { 572 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug); 573 } 574 } 575 576 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) 577 { 578 PIIX4PMState *s = PIIX4_PM(adev); 579 580 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); 581 } 582 583 static Property piix4_pm_properties[] = { 584 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 585 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 586 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 587 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 588 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, 589 use_acpi_pci_hotplug, true), 590 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, 591 acpi_memory_hotplug.is_enabled, true), 592 DEFINE_PROP_END_OF_LIST(), 593 }; 594 595 static void piix4_pm_class_init(ObjectClass *klass, void *data) 596 { 597 DeviceClass *dc = DEVICE_CLASS(klass); 598 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 599 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 600 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 601 602 k->init = piix4_pm_initfn; 603 k->config_write = pm_write_config; 604 k->vendor_id = PCI_VENDOR_ID_INTEL; 605 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 606 k->revision = 0x03; 607 k->class_id = PCI_CLASS_BRIDGE_OTHER; 608 dc->desc = "PM"; 609 dc->vmsd = &vmstate_acpi; 610 dc->props = piix4_pm_properties; 611 /* 612 * Reason: part of PIIX4 southbridge, needs to be wired up, 613 * e.g. by mips_malta_init() 614 */ 615 dc->cannot_instantiate_with_device_add_yet = true; 616 dc->hotpluggable = false; 617 hc->plug = piix4_device_plug_cb; 618 hc->unplug = piix4_device_unplug_cb; 619 adevc->ospm_status = piix4_ospm_status; 620 } 621 622 static const TypeInfo piix4_pm_info = { 623 .name = TYPE_PIIX4_PM, 624 .parent = TYPE_PCI_DEVICE, 625 .instance_size = sizeof(PIIX4PMState), 626 .class_init = piix4_pm_class_init, 627 .interfaces = (InterfaceInfo[]) { 628 { TYPE_HOTPLUG_HANDLER }, 629 { TYPE_ACPI_DEVICE_IF }, 630 { } 631 } 632 }; 633 634 static void piix4_pm_register_types(void) 635 { 636 type_register_static(&piix4_pm_info); 637 } 638 639 type_init(piix4_pm_register_types) 640