1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 #include "hw/hw.h" 22 #include "hw/i386/pc.h" 23 #include "hw/isa/apm.h" 24 #include "hw/i2c/pm_smbus.h" 25 #include "hw/pci/pci.h" 26 #include "hw/acpi/acpi.h" 27 #include "sysemu/sysemu.h" 28 #include "qemu/range.h" 29 #include "exec/ioport.h" 30 #include "hw/nvram/fw_cfg.h" 31 #include "exec/address-spaces.h" 32 #include "hw/acpi/piix4.h" 33 34 //#define DEBUG 35 36 #ifdef DEBUG 37 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 38 #else 39 # define PIIX4_DPRINTF(format, ...) do { } while (0) 40 #endif 41 42 #define GPE_BASE 0xafe0 43 #define GPE_LEN 4 44 45 #define PCI_HOTPLUG_ADDR 0xae00 46 #define PCI_HOTPLUG_SIZE 0x000f 47 #define PCI_UP_BASE 0xae00 48 #define PCI_DOWN_BASE 0xae04 49 #define PCI_EJ_BASE 0xae08 50 #define PCI_RMV_BASE 0xae0c 51 52 #define PIIX4_PROC_BASE 0xaf00 53 #define PIIX4_PROC_LEN 32 54 55 #define PIIX4_PCI_HOTPLUG_STATUS 2 56 #define PIIX4_CPU_HOTPLUG_STATUS 4 57 58 struct pci_status { 59 uint32_t up; /* deprecated, maintained for migration compatibility */ 60 uint32_t down; 61 }; 62 63 typedef struct CPUStatus { 64 uint8_t sts[PIIX4_PROC_LEN]; 65 } CPUStatus; 66 67 typedef struct PIIX4PMState { 68 /*< private >*/ 69 PCIDevice parent_obj; 70 /*< public >*/ 71 72 MemoryRegion io; 73 uint32_t io_base; 74 75 MemoryRegion io_gpe; 76 MemoryRegion io_pci; 77 MemoryRegion io_cpu; 78 ACPIREGS ar; 79 80 APMState apm; 81 82 PMSMBus smb; 83 uint32_t smb_io_base; 84 85 qemu_irq irq; 86 qemu_irq smi_irq; 87 int kvm_enabled; 88 Notifier machine_ready; 89 Notifier powerdown_notifier; 90 91 /* for pci hotplug */ 92 struct pci_status pci0_status; 93 uint32_t pci0_hotplug_enable; 94 uint32_t pci0_slot_device_present; 95 96 uint8_t disable_s3; 97 uint8_t disable_s4; 98 uint8_t s4_val; 99 100 CPUStatus gpe_cpu; 101 Notifier cpu_added_notifier; 102 } PIIX4PMState; 103 104 #define TYPE_PIIX4_PM "PIIX4_PM" 105 106 #define PIIX4_PM(obj) \ 107 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) 108 109 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 110 PCIBus *bus, PIIX4PMState *s); 111 112 #define ACPI_ENABLE 0xf1 113 #define ACPI_DISABLE 0xf0 114 115 static void pm_update_sci(PIIX4PMState *s) 116 { 117 int sci_level, pmsts; 118 119 pmsts = acpi_pm1_evt_get_sts(&s->ar); 120 sci_level = (((pmsts & s->ar.pm1.evt.en) & 121 (ACPI_BITMASK_RT_CLOCK_ENABLE | 122 ACPI_BITMASK_POWER_BUTTON_ENABLE | 123 ACPI_BITMASK_GLOBAL_LOCK_ENABLE | 124 ACPI_BITMASK_TIMER_ENABLE)) != 0) || 125 (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) & 126 (PIIX4_PCI_HOTPLUG_STATUS | PIIX4_CPU_HOTPLUG_STATUS)) != 0); 127 128 qemu_set_irq(s->irq, sci_level); 129 /* schedule a timer interruption if needed */ 130 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && 131 !(pmsts & ACPI_BITMASK_TIMER_STATUS)); 132 } 133 134 static void pm_tmr_timer(ACPIREGS *ar) 135 { 136 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 137 pm_update_sci(s); 138 } 139 140 static void apm_ctrl_changed(uint32_t val, void *arg) 141 { 142 PIIX4PMState *s = arg; 143 PCIDevice *d = PCI_DEVICE(s); 144 145 /* ACPI specs 3.0, 4.7.2.5 */ 146 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 147 148 if (d->config[0x5b] & (1 << 1)) { 149 if (s->smi_irq) { 150 qemu_irq_raise(s->smi_irq); 151 } 152 } 153 } 154 155 static void pm_io_space_update(PIIX4PMState *s) 156 { 157 PCIDevice *d = PCI_DEVICE(s); 158 159 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 160 s->io_base &= 0xffc0; 161 162 memory_region_transaction_begin(); 163 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 164 memory_region_set_address(&s->io, s->io_base); 165 memory_region_transaction_commit(); 166 } 167 168 static void smbus_io_space_update(PIIX4PMState *s) 169 { 170 PCIDevice *d = PCI_DEVICE(s); 171 172 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 173 s->smb_io_base &= 0xffc0; 174 175 memory_region_transaction_begin(); 176 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 177 memory_region_set_address(&s->smb.io, s->smb_io_base); 178 memory_region_transaction_commit(); 179 } 180 181 static void pm_write_config(PCIDevice *d, 182 uint32_t address, uint32_t val, int len) 183 { 184 pci_default_write_config(d, address, val, len); 185 if (range_covers_byte(address, len, 0x80) || 186 ranges_overlap(address, len, 0x40, 4)) { 187 pm_io_space_update((PIIX4PMState *)d); 188 } 189 if (range_covers_byte(address, len, 0xd2) || 190 ranges_overlap(address, len, 0x90, 4)) { 191 smbus_io_space_update((PIIX4PMState *)d); 192 } 193 } 194 195 static void vmstate_pci_status_pre_save(void *opaque) 196 { 197 struct pci_status *pci0_status = opaque; 198 PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status); 199 200 /* We no longer track up, so build a safe value for migrating 201 * to a version that still does... of course these might get lost 202 * by an old buggy implementation, but we try. */ 203 pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable; 204 } 205 206 static int vmstate_acpi_post_load(void *opaque, int version_id) 207 { 208 PIIX4PMState *s = opaque; 209 210 pm_io_space_update(s); 211 return 0; 212 } 213 214 #define VMSTATE_GPE_ARRAY(_field, _state) \ 215 { \ 216 .name = (stringify(_field)), \ 217 .version_id = 0, \ 218 .info = &vmstate_info_uint16, \ 219 .size = sizeof(uint16_t), \ 220 .flags = VMS_SINGLE | VMS_POINTER, \ 221 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 222 } 223 224 static const VMStateDescription vmstate_gpe = { 225 .name = "gpe", 226 .version_id = 1, 227 .minimum_version_id = 1, 228 .minimum_version_id_old = 1, 229 .fields = (VMStateField []) { 230 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 231 VMSTATE_GPE_ARRAY(en, ACPIGPE), 232 VMSTATE_END_OF_LIST() 233 } 234 }; 235 236 static const VMStateDescription vmstate_pci_status = { 237 .name = "pci_status", 238 .version_id = 1, 239 .minimum_version_id = 1, 240 .minimum_version_id_old = 1, 241 .pre_save = vmstate_pci_status_pre_save, 242 .fields = (VMStateField []) { 243 VMSTATE_UINT32(up, struct pci_status), 244 VMSTATE_UINT32(down, struct pci_status), 245 VMSTATE_END_OF_LIST() 246 } 247 }; 248 249 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) 250 { 251 PIIX4PMState *s = opaque; 252 int ret, i; 253 uint16_t temp; 254 255 ret = pci_device_load(PCI_DEVICE(s), f); 256 if (ret < 0) { 257 return ret; 258 } 259 qemu_get_be16s(f, &s->ar.pm1.evt.sts); 260 qemu_get_be16s(f, &s->ar.pm1.evt.en); 261 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); 262 263 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); 264 if (ret) { 265 return ret; 266 } 267 268 timer_get(f, s->ar.tmr.timer); 269 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); 270 271 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); 272 for (i = 0; i < 3; i++) { 273 qemu_get_be16s(f, &temp); 274 } 275 276 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); 277 for (i = 0; i < 3; i++) { 278 qemu_get_be16s(f, &temp); 279 } 280 281 ret = vmstate_load_state(f, &vmstate_pci_status, &s->pci0_status, 1); 282 return ret; 283 } 284 285 /* qemu-kvm 1.2 uses version 3 but advertised as 2 286 * To support incoming qemu-kvm 1.2 migration, change version_id 287 * and minimum_version_id to 2 below (which breaks migration from 288 * qemu 1.2). 289 * 290 */ 291 static const VMStateDescription vmstate_acpi = { 292 .name = "piix4_pm", 293 .version_id = 3, 294 .minimum_version_id = 3, 295 .minimum_version_id_old = 1, 296 .load_state_old = acpi_load_old, 297 .post_load = vmstate_acpi_post_load, 298 .fields = (VMStateField []) { 299 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 300 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 301 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 302 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 303 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 304 VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), 305 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 306 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 307 VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status, 308 struct pci_status), 309 VMSTATE_END_OF_LIST() 310 } 311 }; 312 313 static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) 314 { 315 BusChild *kid, *next; 316 BusState *bus = qdev_get_parent_bus(DEVICE(s)); 317 int slot = ffs(slots) - 1; 318 bool slot_free = true; 319 320 /* Mark request as complete */ 321 s->pci0_status.down &= ~(1U << slot); 322 323 QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { 324 DeviceState *qdev = kid->child; 325 PCIDevice *dev = PCI_DEVICE(qdev); 326 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 327 if (PCI_SLOT(dev->devfn) == slot) { 328 if (pc->no_hotplug) { 329 slot_free = false; 330 } else { 331 object_unparent(OBJECT(qdev)); 332 } 333 } 334 } 335 if (slot_free) { 336 s->pci0_slot_device_present &= ~(1U << slot); 337 } 338 } 339 340 static void piix4_update_hotplug(PIIX4PMState *s) 341 { 342 BusState *bus = qdev_get_parent_bus(DEVICE(s)); 343 BusChild *kid, *next; 344 345 /* Execute any pending removes during reset */ 346 while (s->pci0_status.down) { 347 acpi_piix_eject_slot(s, s->pci0_status.down); 348 } 349 350 s->pci0_hotplug_enable = ~0; 351 s->pci0_slot_device_present = 0; 352 353 QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { 354 DeviceState *qdev = kid->child; 355 PCIDevice *pdev = PCI_DEVICE(qdev); 356 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); 357 int slot = PCI_SLOT(pdev->devfn); 358 359 if (pc->no_hotplug) { 360 s->pci0_hotplug_enable &= ~(1U << slot); 361 } 362 363 s->pci0_slot_device_present |= (1U << slot); 364 } 365 } 366 367 static void piix4_reset(void *opaque) 368 { 369 PIIX4PMState *s = opaque; 370 PCIDevice *d = PCI_DEVICE(s); 371 uint8_t *pci_conf = d->config; 372 373 pci_conf[0x58] = 0; 374 pci_conf[0x59] = 0; 375 pci_conf[0x5a] = 0; 376 pci_conf[0x5b] = 0; 377 378 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 379 pci_conf[0x80] = 0; 380 381 if (s->kvm_enabled) { 382 /* Mark SMM as already inited (until KVM supports SMM). */ 383 pci_conf[0x5B] = 0x02; 384 } 385 pm_io_space_update(s); 386 piix4_update_hotplug(s); 387 } 388 389 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 390 { 391 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 392 393 assert(s != NULL); 394 acpi_pm1_evt_power_down(&s->ar); 395 } 396 397 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 398 { 399 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 400 PCIDevice *d = PCI_DEVICE(s); 401 MemoryRegion *io_as = pci_address_space_io(d); 402 uint8_t *pci_conf; 403 404 pci_conf = d->config; 405 pci_conf[0x5f] = 0x10 | 406 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 407 pci_conf[0x63] = 0x60; 408 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 409 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 410 } 411 412 static void piix4_pm_add_propeties(PIIX4PMState *s) 413 { 414 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 415 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 416 static const uint32_t gpe0_blk = GPE_BASE; 417 static const uint32_t gpe0_blk_len = GPE_LEN; 418 static const uint16_t sci_int = 9; 419 420 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 421 &acpi_enable_cmd, NULL); 422 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 423 &acpi_disable_cmd, NULL); 424 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 425 &gpe0_blk, NULL); 426 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 427 &gpe0_blk_len, NULL); 428 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 429 &sci_int, NULL); 430 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 431 &s->io_base, NULL); 432 } 433 434 static int piix4_pm_initfn(PCIDevice *dev) 435 { 436 PIIX4PMState *s = PIIX4_PM(dev); 437 uint8_t *pci_conf; 438 439 pci_conf = dev->config; 440 pci_conf[0x06] = 0x80; 441 pci_conf[0x07] = 0x02; 442 pci_conf[0x09] = 0x00; 443 pci_conf[0x3d] = 0x01; // interrupt pin 1 444 445 /* APM */ 446 apm_init(dev, &s->apm, apm_ctrl_changed, s); 447 448 if (s->kvm_enabled) { 449 /* Mark SMM as already inited to prevent SMM from running. KVM does not 450 * support SMM mode. */ 451 pci_conf[0x5B] = 0x02; 452 } 453 454 /* XXX: which specification is used ? The i82731AB has different 455 mappings */ 456 pci_conf[0x90] = s->smb_io_base | 1; 457 pci_conf[0x91] = s->smb_io_base >> 8; 458 pci_conf[0xd2] = 0x09; 459 pm_smbus_init(DEVICE(dev), &s->smb); 460 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 461 memory_region_add_subregion(pci_address_space_io(dev), 462 s->smb_io_base, &s->smb.io); 463 464 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 465 memory_region_set_enabled(&s->io, false); 466 memory_region_add_subregion(pci_address_space_io(dev), 467 0, &s->io); 468 469 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 470 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 471 acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val); 472 acpi_gpe_init(&s->ar, GPE_LEN); 473 474 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 475 qemu_register_powerdown_notifier(&s->powerdown_notifier); 476 477 s->machine_ready.notify = piix4_pm_machine_ready; 478 qemu_add_machine_init_done_notifier(&s->machine_ready); 479 qemu_register_reset(piix4_reset, s); 480 481 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s); 482 483 piix4_pm_add_propeties(s); 484 return 0; 485 } 486 487 Object *piix4_pm_find(void) 488 { 489 bool ambig; 490 Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig); 491 492 if (ambig || !o) { 493 return NULL; 494 } 495 return o; 496 } 497 498 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 499 qemu_irq sci_irq, qemu_irq smi_irq, 500 int kvm_enabled, FWCfgState *fw_cfg) 501 { 502 DeviceState *dev; 503 PIIX4PMState *s; 504 505 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); 506 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 507 508 s = PIIX4_PM(dev); 509 s->irq = sci_irq; 510 s->smi_irq = smi_irq; 511 s->kvm_enabled = kvm_enabled; 512 513 qdev_init_nofail(dev); 514 515 if (fw_cfg) { 516 uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; 517 suspend[3] = 1 | ((!s->disable_s3) << 7); 518 suspend[4] = s->s4_val | ((!s->disable_s4) << 7); 519 520 fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); 521 } 522 523 return s->smb.smbus; 524 } 525 526 static Property piix4_pm_properties[] = { 527 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 528 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 529 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 530 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 531 DEFINE_PROP_END_OF_LIST(), 532 }; 533 534 static void piix4_pm_class_init(ObjectClass *klass, void *data) 535 { 536 DeviceClass *dc = DEVICE_CLASS(klass); 537 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 538 539 k->no_hotplug = 1; 540 k->init = piix4_pm_initfn; 541 k->config_write = pm_write_config; 542 k->vendor_id = PCI_VENDOR_ID_INTEL; 543 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 544 k->revision = 0x03; 545 k->class_id = PCI_CLASS_BRIDGE_OTHER; 546 dc->desc = "PM"; 547 dc->no_user = 1; 548 dc->vmsd = &vmstate_acpi; 549 dc->props = piix4_pm_properties; 550 } 551 552 static const TypeInfo piix4_pm_info = { 553 .name = TYPE_PIIX4_PM, 554 .parent = TYPE_PCI_DEVICE, 555 .instance_size = sizeof(PIIX4PMState), 556 .class_init = piix4_pm_class_init, 557 }; 558 559 static void piix4_pm_register_types(void) 560 { 561 type_register_static(&piix4_pm_info); 562 } 563 564 type_init(piix4_pm_register_types) 565 566 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 567 { 568 PIIX4PMState *s = opaque; 569 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 570 571 PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); 572 return val; 573 } 574 575 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 576 unsigned width) 577 { 578 PIIX4PMState *s = opaque; 579 580 acpi_gpe_ioport_writeb(&s->ar, addr, val); 581 pm_update_sci(s); 582 583 PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); 584 } 585 586 static const MemoryRegionOps piix4_gpe_ops = { 587 .read = gpe_readb, 588 .write = gpe_writeb, 589 .valid.min_access_size = 1, 590 .valid.max_access_size = 4, 591 .impl.min_access_size = 1, 592 .impl.max_access_size = 1, 593 .endianness = DEVICE_LITTLE_ENDIAN, 594 }; 595 596 static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) 597 { 598 PIIX4PMState *s = opaque; 599 uint32_t val = 0; 600 601 switch (addr) { 602 case PCI_UP_BASE - PCI_HOTPLUG_ADDR: 603 /* Manufacture an "up" value to cause a device check on any hotplug 604 * slot with a device. Extra device checks are harmless. */ 605 val = s->pci0_slot_device_present & s->pci0_hotplug_enable; 606 PIIX4_DPRINTF("pci_up_read %" PRIu32 "\n", val); 607 break; 608 case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR: 609 val = s->pci0_status.down; 610 PIIX4_DPRINTF("pci_down_read %" PRIu32 "\n", val); 611 break; 612 case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: 613 /* No feature defined yet */ 614 PIIX4_DPRINTF("pci_features_read %" PRIu32 "\n", val); 615 break; 616 case PCI_RMV_BASE - PCI_HOTPLUG_ADDR: 617 val = s->pci0_hotplug_enable; 618 break; 619 default: 620 break; 621 } 622 623 return val; 624 } 625 626 static void pci_write(void *opaque, hwaddr addr, uint64_t data, 627 unsigned int size) 628 { 629 switch (addr) { 630 case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: 631 acpi_piix_eject_slot(opaque, (uint32_t)data); 632 PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n", 633 addr, data); 634 break; 635 default: 636 break; 637 } 638 } 639 640 static const MemoryRegionOps piix4_pci_ops = { 641 .read = pci_read, 642 .write = pci_write, 643 .endianness = DEVICE_LITTLE_ENDIAN, 644 .valid = { 645 .min_access_size = 4, 646 .max_access_size = 4, 647 }, 648 }; 649 650 static uint64_t cpu_status_read(void *opaque, hwaddr addr, unsigned int size) 651 { 652 PIIX4PMState *s = opaque; 653 CPUStatus *cpus = &s->gpe_cpu; 654 uint64_t val = cpus->sts[addr]; 655 656 return val; 657 } 658 659 static void cpu_status_write(void *opaque, hwaddr addr, uint64_t data, 660 unsigned int size) 661 { 662 /* TODO: implement VCPU removal on guest signal that CPU can be removed */ 663 } 664 665 static const MemoryRegionOps cpu_hotplug_ops = { 666 .read = cpu_status_read, 667 .write = cpu_status_write, 668 .endianness = DEVICE_LITTLE_ENDIAN, 669 .valid = { 670 .min_access_size = 1, 671 .max_access_size = 1, 672 }, 673 }; 674 675 typedef enum { 676 PLUG, 677 UNPLUG, 678 } HotplugEventType; 679 680 static void piix4_cpu_hotplug_req(PIIX4PMState *s, CPUState *cpu, 681 HotplugEventType action) 682 { 683 CPUStatus *g = &s->gpe_cpu; 684 ACPIGPE *gpe = &s->ar.gpe; 685 CPUClass *k = CPU_GET_CLASS(cpu); 686 int64_t cpu_id; 687 688 assert(s != NULL); 689 690 *gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS; 691 cpu_id = k->get_arch_id(CPU(cpu)); 692 if (action == PLUG) { 693 g->sts[cpu_id / 8] |= (1 << (cpu_id % 8)); 694 } else { 695 g->sts[cpu_id / 8] &= ~(1 << (cpu_id % 8)); 696 } 697 pm_update_sci(s); 698 } 699 700 static void piix4_cpu_added_req(Notifier *n, void *opaque) 701 { 702 PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier); 703 704 piix4_cpu_hotplug_req(s, CPU(opaque), PLUG); 705 } 706 707 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, 708 PCIHotplugState state); 709 710 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 711 PCIBus *bus, PIIX4PMState *s) 712 { 713 CPUState *cpu; 714 715 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 716 "acpi-gpe0", GPE_LEN); 717 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 718 719 memory_region_init_io(&s->io_pci, OBJECT(s), &piix4_pci_ops, s, 720 "acpi-pci-hotplug", PCI_HOTPLUG_SIZE); 721 memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR, 722 &s->io_pci); 723 pci_bus_hotplug(bus, piix4_device_hotplug, DEVICE(s)); 724 725 CPU_FOREACH(cpu) { 726 CPUClass *cc = CPU_GET_CLASS(cpu); 727 int64_t id = cc->get_arch_id(cpu); 728 729 g_assert((id / 8) < PIIX4_PROC_LEN); 730 s->gpe_cpu.sts[id / 8] |= (1 << (id % 8)); 731 } 732 memory_region_init_io(&s->io_cpu, OBJECT(s), &cpu_hotplug_ops, s, 733 "acpi-cpu-hotplug", PIIX4_PROC_LEN); 734 memory_region_add_subregion(parent, PIIX4_PROC_BASE, &s->io_cpu); 735 s->cpu_added_notifier.notify = piix4_cpu_added_req; 736 qemu_register_cpu_added_notifier(&s->cpu_added_notifier); 737 } 738 739 static void enable_device(PIIX4PMState *s, int slot) 740 { 741 s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; 742 s->pci0_slot_device_present |= (1U << slot); 743 } 744 745 static void disable_device(PIIX4PMState *s, int slot) 746 { 747 s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; 748 s->pci0_status.down |= (1U << slot); 749 } 750 751 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, 752 PCIHotplugState state) 753 { 754 int slot = PCI_SLOT(dev->devfn); 755 PIIX4PMState *s = PIIX4_PM(qdev); 756 757 /* Don't send event when device is enabled during qemu machine creation: 758 * it is present on boot, no hotplug event is necessary. We do send an 759 * event when the device is disabled later. */ 760 if (state == PCI_COLDPLUG_ENABLED) { 761 s->pci0_slot_device_present |= (1U << slot); 762 return 0; 763 } 764 765 if (state == PCI_HOTPLUG_ENABLED) { 766 enable_device(s, slot); 767 } else { 768 disable_device(s, slot); 769 } 770 771 pm_update_sci(s); 772 773 return 0; 774 } 775