1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 #include "hw/hw.h" 22 #include "hw/i386/pc.h" 23 #include "hw/isa/apm.h" 24 #include "hw/i2c/pm_smbus.h" 25 #include "hw/pci/pci.h" 26 #include "hw/acpi/acpi.h" 27 #include "sysemu/sysemu.h" 28 #include "qemu/range.h" 29 #include "exec/ioport.h" 30 #include "hw/nvram/fw_cfg.h" 31 #include "exec/address-spaces.h" 32 #include "hw/acpi/piix4.h" 33 #include "hw/acpi/pcihp.h" 34 #include "hw/acpi/cpu_hotplug.h" 35 #include "hw/hotplug.h" 36 #include "hw/mem/pc-dimm.h" 37 #include "hw/acpi/memory_hotplug.h" 38 39 //#define DEBUG 40 41 #ifdef DEBUG 42 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 43 #else 44 # define PIIX4_DPRINTF(format, ...) do { } while (0) 45 #endif 46 47 #define GPE_BASE 0xafe0 48 #define GPE_LEN 4 49 50 struct pci_status { 51 uint32_t up; /* deprecated, maintained for migration compatibility */ 52 uint32_t down; 53 }; 54 55 typedef struct PIIX4PMState { 56 /*< private >*/ 57 PCIDevice parent_obj; 58 /*< public >*/ 59 60 MemoryRegion io; 61 uint32_t io_base; 62 63 MemoryRegion io_gpe; 64 ACPIREGS ar; 65 66 APMState apm; 67 68 PMSMBus smb; 69 uint32_t smb_io_base; 70 71 qemu_irq irq; 72 qemu_irq smi_irq; 73 int kvm_enabled; 74 Notifier machine_ready; 75 Notifier powerdown_notifier; 76 77 AcpiPciHpState acpi_pci_hotplug; 78 bool use_acpi_pci_hotplug; 79 80 uint8_t disable_s3; 81 uint8_t disable_s4; 82 uint8_t s4_val; 83 84 AcpiCpuHotplug gpe_cpu; 85 Notifier cpu_added_notifier; 86 87 MemHotplugState acpi_memory_hotplug; 88 } PIIX4PMState; 89 90 #define TYPE_PIIX4_PM "PIIX4_PM" 91 92 #define PIIX4_PM(obj) \ 93 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) 94 95 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 96 PCIBus *bus, PIIX4PMState *s); 97 98 #define ACPI_ENABLE 0xf1 99 #define ACPI_DISABLE 0xf0 100 101 static void pm_tmr_timer(ACPIREGS *ar) 102 { 103 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 104 acpi_update_sci(&s->ar, s->irq); 105 } 106 107 static void apm_ctrl_changed(uint32_t val, void *arg) 108 { 109 PIIX4PMState *s = arg; 110 PCIDevice *d = PCI_DEVICE(s); 111 112 /* ACPI specs 3.0, 4.7.2.5 */ 113 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 114 115 if (d->config[0x5b] & (1 << 1)) { 116 if (s->smi_irq) { 117 qemu_irq_raise(s->smi_irq); 118 } 119 } 120 } 121 122 static void pm_io_space_update(PIIX4PMState *s) 123 { 124 PCIDevice *d = PCI_DEVICE(s); 125 126 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 127 s->io_base &= 0xffc0; 128 129 memory_region_transaction_begin(); 130 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 131 memory_region_set_address(&s->io, s->io_base); 132 memory_region_transaction_commit(); 133 } 134 135 static void smbus_io_space_update(PIIX4PMState *s) 136 { 137 PCIDevice *d = PCI_DEVICE(s); 138 139 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 140 s->smb_io_base &= 0xffc0; 141 142 memory_region_transaction_begin(); 143 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 144 memory_region_set_address(&s->smb.io, s->smb_io_base); 145 memory_region_transaction_commit(); 146 } 147 148 static void pm_write_config(PCIDevice *d, 149 uint32_t address, uint32_t val, int len) 150 { 151 pci_default_write_config(d, address, val, len); 152 if (range_covers_byte(address, len, 0x80) || 153 ranges_overlap(address, len, 0x40, 4)) { 154 pm_io_space_update((PIIX4PMState *)d); 155 } 156 if (range_covers_byte(address, len, 0xd2) || 157 ranges_overlap(address, len, 0x90, 4)) { 158 smbus_io_space_update((PIIX4PMState *)d); 159 } 160 } 161 162 static int vmstate_acpi_post_load(void *opaque, int version_id) 163 { 164 PIIX4PMState *s = opaque; 165 166 pm_io_space_update(s); 167 return 0; 168 } 169 170 #define VMSTATE_GPE_ARRAY(_field, _state) \ 171 { \ 172 .name = (stringify(_field)), \ 173 .version_id = 0, \ 174 .info = &vmstate_info_uint16, \ 175 .size = sizeof(uint16_t), \ 176 .flags = VMS_SINGLE | VMS_POINTER, \ 177 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 178 } 179 180 static const VMStateDescription vmstate_gpe = { 181 .name = "gpe", 182 .version_id = 1, 183 .minimum_version_id = 1, 184 .fields = (VMStateField[]) { 185 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 186 VMSTATE_GPE_ARRAY(en, ACPIGPE), 187 VMSTATE_END_OF_LIST() 188 } 189 }; 190 191 static const VMStateDescription vmstate_pci_status = { 192 .name = "pci_status", 193 .version_id = 1, 194 .minimum_version_id = 1, 195 .fields = (VMStateField[]) { 196 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), 197 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), 198 VMSTATE_END_OF_LIST() 199 } 200 }; 201 202 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) 203 { 204 PIIX4PMState *s = opaque; 205 int ret, i; 206 uint16_t temp; 207 208 ret = pci_device_load(PCI_DEVICE(s), f); 209 if (ret < 0) { 210 return ret; 211 } 212 qemu_get_be16s(f, &s->ar.pm1.evt.sts); 213 qemu_get_be16s(f, &s->ar.pm1.evt.en); 214 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); 215 216 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); 217 if (ret) { 218 return ret; 219 } 220 221 timer_get(f, s->ar.tmr.timer); 222 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); 223 224 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); 225 for (i = 0; i < 3; i++) { 226 qemu_get_be16s(f, &temp); 227 } 228 229 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); 230 for (i = 0; i < 3; i++) { 231 qemu_get_be16s(f, &temp); 232 } 233 234 ret = vmstate_load_state(f, &vmstate_pci_status, 235 &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1); 236 return ret; 237 } 238 239 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) 240 { 241 PIIX4PMState *s = opaque; 242 return s->use_acpi_pci_hotplug; 243 } 244 245 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id) 246 { 247 PIIX4PMState *s = opaque; 248 return !s->use_acpi_pci_hotplug; 249 } 250 251 static bool vmstate_test_use_memhp(void *opaque) 252 { 253 PIIX4PMState *s = opaque; 254 return s->acpi_memory_hotplug.is_enabled; 255 } 256 257 static const VMStateDescription vmstate_memhp_state = { 258 .name = "piix4_pm/memhp", 259 .version_id = 1, 260 .minimum_version_id = 1, 261 .minimum_version_id_old = 1, 262 .fields = (VMStateField[]) { 263 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), 264 VMSTATE_END_OF_LIST() 265 } 266 }; 267 268 /* qemu-kvm 1.2 uses version 3 but advertised as 2 269 * To support incoming qemu-kvm 1.2 migration, change version_id 270 * and minimum_version_id to 2 below (which breaks migration from 271 * qemu 1.2). 272 * 273 */ 274 static const VMStateDescription vmstate_acpi = { 275 .name = "piix4_pm", 276 .version_id = 3, 277 .minimum_version_id = 3, 278 .minimum_version_id_old = 1, 279 .load_state_old = acpi_load_old, 280 .post_load = vmstate_acpi_post_load, 281 .fields = (VMStateField[]) { 282 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 283 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 284 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 285 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 286 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 287 VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), 288 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 289 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 290 VMSTATE_STRUCT_TEST( 291 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 292 PIIX4PMState, 293 vmstate_test_no_use_acpi_pci_hotplug, 294 2, vmstate_pci_status, 295 struct AcpiPciHpPciStatus), 296 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 297 vmstate_test_use_acpi_pci_hotplug), 298 VMSTATE_END_OF_LIST() 299 }, 300 .subsections = (VMStateSubsection[]) { 301 { 302 .vmsd = &vmstate_memhp_state, 303 .needed = vmstate_test_use_memhp, 304 }, 305 VMSTATE_END_OF_LIST() 306 } 307 }; 308 309 static void piix4_reset(void *opaque) 310 { 311 PIIX4PMState *s = opaque; 312 PCIDevice *d = PCI_DEVICE(s); 313 uint8_t *pci_conf = d->config; 314 315 pci_conf[0x58] = 0; 316 pci_conf[0x59] = 0; 317 pci_conf[0x5a] = 0; 318 pci_conf[0x5b] = 0; 319 320 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 321 pci_conf[0x80] = 0; 322 323 if (s->kvm_enabled) { 324 /* Mark SMM as already inited (until KVM supports SMM). */ 325 pci_conf[0x5B] = 0x02; 326 } 327 pm_io_space_update(s); 328 acpi_pcihp_reset(&s->acpi_pci_hotplug); 329 } 330 331 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 332 { 333 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 334 335 assert(s != NULL); 336 acpi_pm1_evt_power_down(&s->ar); 337 } 338 339 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, 340 DeviceState *dev, Error **errp) 341 { 342 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 343 344 if (s->acpi_memory_hotplug.is_enabled && 345 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 346 acpi_memory_plug_cb(&s->ar, s->irq, &s->acpi_memory_hotplug, dev, errp); 347 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 348 acpi_pcihp_device_plug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev, 349 errp); 350 } else { 351 error_setg(errp, "acpi: device plug request for not supported device" 352 " type: %s", object_get_typename(OBJECT(dev))); 353 } 354 } 355 356 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, 357 DeviceState *dev, Error **errp) 358 { 359 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 360 361 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 362 acpi_pcihp_device_unplug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev, 363 errp); 364 } else { 365 error_setg(errp, "acpi: device unplug request for not supported device" 366 " type: %s", object_get_typename(OBJECT(dev))); 367 } 368 } 369 370 static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque) 371 { 372 PIIX4PMState *s = opaque; 373 374 qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort); 375 } 376 377 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 378 { 379 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 380 PCIDevice *d = PCI_DEVICE(s); 381 MemoryRegion *io_as = pci_address_space_io(d); 382 uint8_t *pci_conf; 383 384 pci_conf = d->config; 385 pci_conf[0x5f] = 0x10 | 386 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 387 pci_conf[0x63] = 0x60; 388 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 389 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 390 391 if (s->use_acpi_pci_hotplug) { 392 pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s); 393 } else { 394 piix4_update_bus_hotplug(d->bus, s); 395 } 396 } 397 398 static void piix4_pm_add_propeties(PIIX4PMState *s) 399 { 400 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 401 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 402 static const uint32_t gpe0_blk = GPE_BASE; 403 static const uint32_t gpe0_blk_len = GPE_LEN; 404 static const uint16_t sci_int = 9; 405 406 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 407 &acpi_enable_cmd, NULL); 408 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 409 &acpi_disable_cmd, NULL); 410 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 411 &gpe0_blk, NULL); 412 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 413 &gpe0_blk_len, NULL); 414 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 415 &sci_int, NULL); 416 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 417 &s->io_base, NULL); 418 } 419 420 static int piix4_pm_initfn(PCIDevice *dev) 421 { 422 PIIX4PMState *s = PIIX4_PM(dev); 423 uint8_t *pci_conf; 424 425 pci_conf = dev->config; 426 pci_conf[0x06] = 0x80; 427 pci_conf[0x07] = 0x02; 428 pci_conf[0x09] = 0x00; 429 pci_conf[0x3d] = 0x01; // interrupt pin 1 430 431 /* APM */ 432 apm_init(dev, &s->apm, apm_ctrl_changed, s); 433 434 if (s->kvm_enabled) { 435 /* Mark SMM as already inited to prevent SMM from running. KVM does not 436 * support SMM mode. */ 437 pci_conf[0x5B] = 0x02; 438 } 439 440 /* XXX: which specification is used ? The i82731AB has different 441 mappings */ 442 pci_conf[0x90] = s->smb_io_base | 1; 443 pci_conf[0x91] = s->smb_io_base >> 8; 444 pci_conf[0xd2] = 0x09; 445 pm_smbus_init(DEVICE(dev), &s->smb); 446 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 447 memory_region_add_subregion(pci_address_space_io(dev), 448 s->smb_io_base, &s->smb.io); 449 450 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 451 memory_region_set_enabled(&s->io, false); 452 memory_region_add_subregion(pci_address_space_io(dev), 453 0, &s->io); 454 455 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 456 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 457 acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val); 458 acpi_gpe_init(&s->ar, GPE_LEN); 459 460 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 461 qemu_register_powerdown_notifier(&s->powerdown_notifier); 462 463 s->machine_ready.notify = piix4_pm_machine_ready; 464 qemu_add_machine_init_done_notifier(&s->machine_ready); 465 qemu_register_reset(piix4_reset, s); 466 467 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s); 468 469 piix4_pm_add_propeties(s); 470 return 0; 471 } 472 473 Object *piix4_pm_find(void) 474 { 475 bool ambig; 476 Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig); 477 478 if (ambig || !o) { 479 return NULL; 480 } 481 return o; 482 } 483 484 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 485 qemu_irq sci_irq, qemu_irq smi_irq, 486 int kvm_enabled, FWCfgState *fw_cfg, 487 DeviceState **piix4_pm) 488 { 489 DeviceState *dev; 490 PIIX4PMState *s; 491 492 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); 493 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); 494 if (piix4_pm) { 495 *piix4_pm = dev; 496 } 497 498 s = PIIX4_PM(dev); 499 s->irq = sci_irq; 500 s->smi_irq = smi_irq; 501 s->kvm_enabled = kvm_enabled; 502 503 qdev_init_nofail(dev); 504 505 if (fw_cfg) { 506 uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; 507 suspend[3] = 1 | ((!s->disable_s3) << 7); 508 suspend[4] = s->s4_val | ((!s->disable_s4) << 7); 509 510 fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); 511 } 512 513 return s->smb.smbus; 514 } 515 516 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 517 { 518 PIIX4PMState *s = opaque; 519 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 520 521 PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); 522 return val; 523 } 524 525 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 526 unsigned width) 527 { 528 PIIX4PMState *s = opaque; 529 530 acpi_gpe_ioport_writeb(&s->ar, addr, val); 531 acpi_update_sci(&s->ar, s->irq); 532 533 PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); 534 } 535 536 static const MemoryRegionOps piix4_gpe_ops = { 537 .read = gpe_readb, 538 .write = gpe_writeb, 539 .valid.min_access_size = 1, 540 .valid.max_access_size = 4, 541 .impl.min_access_size = 1, 542 .impl.max_access_size = 1, 543 .endianness = DEVICE_LITTLE_ENDIAN, 544 }; 545 546 static void piix4_cpu_added_req(Notifier *n, void *opaque) 547 { 548 PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier); 549 550 assert(s != NULL); 551 AcpiCpuHotplug_add(&s->ar.gpe, &s->gpe_cpu, CPU(opaque)); 552 acpi_update_sci(&s->ar, s->irq); 553 } 554 555 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 556 PCIBus *bus, PIIX4PMState *s) 557 { 558 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 559 "acpi-gpe0", GPE_LEN); 560 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 561 562 acpi_pcihp_init(&s->acpi_pci_hotplug, bus, parent, 563 s->use_acpi_pci_hotplug); 564 565 AcpiCpuHotplug_init(parent, OBJECT(s), &s->gpe_cpu, 566 PIIX4_CPU_HOTPLUG_IO_BASE); 567 s->cpu_added_notifier.notify = piix4_cpu_added_req; 568 qemu_register_cpu_added_notifier(&s->cpu_added_notifier); 569 570 if (s->acpi_memory_hotplug.is_enabled) { 571 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug); 572 } 573 } 574 575 static Property piix4_pm_properties[] = { 576 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 577 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 578 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 579 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 580 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, 581 use_acpi_pci_hotplug, true), 582 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, 583 acpi_memory_hotplug.is_enabled, true), 584 DEFINE_PROP_END_OF_LIST(), 585 }; 586 587 static void piix4_pm_class_init(ObjectClass *klass, void *data) 588 { 589 DeviceClass *dc = DEVICE_CLASS(klass); 590 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 591 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 592 593 k->init = piix4_pm_initfn; 594 k->config_write = pm_write_config; 595 k->vendor_id = PCI_VENDOR_ID_INTEL; 596 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 597 k->revision = 0x03; 598 k->class_id = PCI_CLASS_BRIDGE_OTHER; 599 dc->desc = "PM"; 600 dc->vmsd = &vmstate_acpi; 601 dc->props = piix4_pm_properties; 602 /* 603 * Reason: part of PIIX4 southbridge, needs to be wired up, 604 * e.g. by mips_malta_init() 605 */ 606 dc->cannot_instantiate_with_device_add_yet = true; 607 dc->hotpluggable = false; 608 hc->plug = piix4_device_plug_cb; 609 hc->unplug = piix4_device_unplug_cb; 610 } 611 612 static const TypeInfo piix4_pm_info = { 613 .name = TYPE_PIIX4_PM, 614 .parent = TYPE_PCI_DEVICE, 615 .instance_size = sizeof(PIIX4PMState), 616 .class_init = piix4_pm_class_init, 617 .interfaces = (InterfaceInfo[]) { 618 { TYPE_HOTPLUG_HANDLER }, 619 { } 620 } 621 }; 622 623 static void piix4_pm_register_types(void) 624 { 625 type_register_static(&piix4_pm_info); 626 } 627 628 type_init(piix4_pm_register_types) 629