1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> 6 * VA Linux Systems Japan K.K. 7 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 8 * 9 * This is based on acpi.c. 10 * 11 * This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU Lesser General Public 13 * License version 2 as published by the Free Software Foundation. 14 * 15 * This library is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * Lesser General Public License for more details. 19 * 20 * You should have received a copy of the GNU Lesser General Public 21 * License along with this library; if not, see <http://www.gnu.org/licenses/> 22 * 23 * Contributions after 2012-01-13 are licensed under the terms of the 24 * GNU GPL, version 2 or (at your option) any later version. 25 */ 26 #include "hw/hw.h" 27 #include "qapi/visitor.h" 28 #include "hw/i386/pc.h" 29 #include "hw/pci/pci.h" 30 #include "qemu/timer.h" 31 #include "sysemu/sysemu.h" 32 #include "hw/acpi/acpi.h" 33 #include "sysemu/kvm.h" 34 #include "exec/address-spaces.h" 35 36 #include "hw/i386/ich9.h" 37 #include "hw/mem/pc-dimm.h" 38 39 //#define DEBUG 40 41 #ifdef DEBUG 42 #define ICH9_DEBUG(fmt, ...) \ 43 do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0) 44 #else 45 #define ICH9_DEBUG(fmt, ...) do { } while (0) 46 #endif 47 48 static void ich9_pm_update_sci_fn(ACPIREGS *regs) 49 { 50 ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs); 51 acpi_update_sci(&pm->acpi_regs, pm->irq); 52 } 53 54 static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width) 55 { 56 ICH9LPCPMRegs *pm = opaque; 57 return acpi_gpe_ioport_readb(&pm->acpi_regs, addr); 58 } 59 60 static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 61 unsigned width) 62 { 63 ICH9LPCPMRegs *pm = opaque; 64 acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val); 65 acpi_update_sci(&pm->acpi_regs, pm->irq); 66 } 67 68 static const MemoryRegionOps ich9_gpe_ops = { 69 .read = ich9_gpe_readb, 70 .write = ich9_gpe_writeb, 71 .valid.min_access_size = 1, 72 .valid.max_access_size = 4, 73 .impl.min_access_size = 1, 74 .impl.max_access_size = 1, 75 .endianness = DEVICE_LITTLE_ENDIAN, 76 }; 77 78 static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width) 79 { 80 ICH9LPCPMRegs *pm = opaque; 81 switch (addr) { 82 case 0: 83 return pm->smi_en; 84 case 4: 85 return pm->smi_sts; 86 default: 87 return 0; 88 } 89 } 90 91 static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val, 92 unsigned width) 93 { 94 ICH9LPCPMRegs *pm = opaque; 95 switch (addr) { 96 case 0: 97 pm->smi_en = val; 98 break; 99 } 100 } 101 102 static const MemoryRegionOps ich9_smi_ops = { 103 .read = ich9_smi_readl, 104 .write = ich9_smi_writel, 105 .valid.min_access_size = 4, 106 .valid.max_access_size = 4, 107 .endianness = DEVICE_LITTLE_ENDIAN, 108 }; 109 110 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base) 111 { 112 ICH9_DEBUG("to 0x%x\n", pm_io_base); 113 114 assert((pm_io_base & ICH9_PMIO_MASK) == 0); 115 116 pm->pm_io_base = pm_io_base; 117 memory_region_transaction_begin(); 118 memory_region_set_enabled(&pm->io, pm->pm_io_base != 0); 119 memory_region_set_address(&pm->io, pm->pm_io_base); 120 memory_region_transaction_commit(); 121 } 122 123 static int ich9_pm_post_load(void *opaque, int version_id) 124 { 125 ICH9LPCPMRegs *pm = opaque; 126 uint32_t pm_io_base = pm->pm_io_base; 127 pm->pm_io_base = 0; 128 ich9_pm_iospace_update(pm, pm_io_base); 129 return 0; 130 } 131 132 #define VMSTATE_GPE_ARRAY(_field, _state) \ 133 { \ 134 .name = (stringify(_field)), \ 135 .version_id = 0, \ 136 .num = ICH9_PMIO_GPE0_LEN, \ 137 .info = &vmstate_info_uint8, \ 138 .size = sizeof(uint8_t), \ 139 .flags = VMS_ARRAY | VMS_POINTER, \ 140 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 141 } 142 143 static bool vmstate_test_use_memhp(void *opaque) 144 { 145 ICH9LPCPMRegs *s = opaque; 146 return s->acpi_memory_hotplug.is_enabled; 147 } 148 149 static const VMStateDescription vmstate_memhp_state = { 150 .name = "ich9_pm/memhp", 151 .version_id = 1, 152 .minimum_version_id = 1, 153 .minimum_version_id_old = 1, 154 .fields = (VMStateField[]) { 155 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, ICH9LPCPMRegs), 156 VMSTATE_END_OF_LIST() 157 } 158 }; 159 160 const VMStateDescription vmstate_ich9_pm = { 161 .name = "ich9_pm", 162 .version_id = 1, 163 .minimum_version_id = 1, 164 .post_load = ich9_pm_post_load, 165 .fields = (VMStateField[]) { 166 VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs), 167 VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs), 168 VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs), 169 VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs), 170 VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs), 171 VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs), 172 VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs), 173 VMSTATE_UINT32(smi_en, ICH9LPCPMRegs), 174 VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs), 175 VMSTATE_END_OF_LIST() 176 }, 177 .subsections = (VMStateSubsection[]) { 178 { 179 .vmsd = &vmstate_memhp_state, 180 .needed = vmstate_test_use_memhp, 181 }, 182 VMSTATE_END_OF_LIST() 183 } 184 }; 185 186 static void pm_reset(void *opaque) 187 { 188 ICH9LPCPMRegs *pm = opaque; 189 ich9_pm_iospace_update(pm, 0); 190 191 acpi_pm1_evt_reset(&pm->acpi_regs); 192 acpi_pm1_cnt_reset(&pm->acpi_regs); 193 acpi_pm_tmr_reset(&pm->acpi_regs); 194 acpi_gpe_reset(&pm->acpi_regs); 195 196 if (kvm_enabled()) { 197 /* Mark SMM as already inited to prevent SMM from running. KVM does not 198 * support SMM mode. */ 199 pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN; 200 } 201 202 acpi_update_sci(&pm->acpi_regs, pm->irq); 203 } 204 205 static void pm_powerdown_req(Notifier *n, void *opaque) 206 { 207 ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier); 208 209 acpi_pm1_evt_power_down(&pm->acpi_regs); 210 } 211 212 static void ich9_cpu_added_req(Notifier *n, void *opaque) 213 { 214 ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, cpu_added_notifier); 215 216 assert(pm != NULL); 217 AcpiCpuHotplug_add(&pm->acpi_regs.gpe, &pm->gpe_cpu, CPU(opaque)); 218 acpi_update_sci(&pm->acpi_regs, pm->irq); 219 } 220 221 void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, 222 qemu_irq sci_irq) 223 { 224 memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE); 225 memory_region_set_enabled(&pm->io, false); 226 memory_region_add_subregion(pci_address_space_io(lpc_pci), 227 0, &pm->io); 228 229 acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); 230 acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); 231 acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, 2); 232 233 acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN); 234 memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm, 235 "acpi-gpe0", ICH9_PMIO_GPE0_LEN); 236 memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe); 237 238 memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm, 239 "acpi-smi", 8); 240 memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi); 241 242 pm->irq = sci_irq; 243 qemu_register_reset(pm_reset, pm); 244 pm->powerdown_notifier.notify = pm_powerdown_req; 245 qemu_register_powerdown_notifier(&pm->powerdown_notifier); 246 247 AcpiCpuHotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci), 248 &pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE); 249 pm->cpu_added_notifier.notify = ich9_cpu_added_req; 250 qemu_register_cpu_added_notifier(&pm->cpu_added_notifier); 251 252 if (pm->acpi_memory_hotplug.is_enabled) { 253 acpi_memory_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci), 254 &pm->acpi_memory_hotplug); 255 } 256 } 257 258 static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v, 259 void *opaque, const char *name, 260 Error **errp) 261 { 262 ICH9LPCPMRegs *pm = opaque; 263 uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS; 264 265 visit_type_uint32(v, &value, name, errp); 266 } 267 268 static bool ich9_pm_get_memory_hotplug_support(Object *obj, Error **errp) 269 { 270 ICH9LPCState *s = ICH9_LPC_DEVICE(obj); 271 272 return s->pm.acpi_memory_hotplug.is_enabled; 273 } 274 275 static void ich9_pm_set_memory_hotplug_support(Object *obj, bool value, 276 Error **errp) 277 { 278 ICH9LPCState *s = ICH9_LPC_DEVICE(obj); 279 280 s->pm.acpi_memory_hotplug.is_enabled = value; 281 } 282 283 void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp) 284 { 285 static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN; 286 pm->acpi_memory_hotplug.is_enabled = true; 287 288 object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE, 289 &pm->pm_io_base, errp); 290 object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32", 291 ich9_pm_get_gpe0_blk, 292 NULL, NULL, pm, NULL); 293 object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN, 294 &gpe0_len, errp); 295 object_property_add_bool(obj, "memory-hotplug-support", 296 ich9_pm_get_memory_hotplug_support, 297 ich9_pm_set_memory_hotplug_support, 298 NULL); 299 } 300 301 void ich9_pm_device_plug_cb(ICH9LPCPMRegs *pm, DeviceState *dev, Error **errp) 302 { 303 if (pm->acpi_memory_hotplug.is_enabled && 304 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 305 acpi_memory_plug_cb(&pm->acpi_regs, pm->irq, &pm->acpi_memory_hotplug, 306 dev, errp); 307 } else { 308 error_setg(errp, "acpi: device plug request for not supported device" 309 " type: %s", object_get_typename(OBJECT(dev))); 310 } 311 } 312 313 void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) 314 { 315 ICH9LPCState *s = ICH9_LPC_DEVICE(adev); 316 317 acpi_memory_ospm_status(&s->pm.acpi_memory_hotplug, list); 318 } 319