1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> 6 * VA Linux Systems Japan K.K. 7 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 8 * 9 * This is based on acpi.c. 10 * 11 * This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU Lesser General Public 13 * License version 2 as published by the Free Software Foundation. 14 * 15 * This library is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * Lesser General Public License for more details. 19 * 20 * You should have received a copy of the GNU Lesser General Public 21 * License along with this library; if not, see <http://www.gnu.org/licenses/> 22 * 23 * Contributions after 2012-01-13 are licensed under the terms of the 24 * GNU GPL, version 2 or (at your option) any later version. 25 */ 26 #include "hw/hw.h" 27 #include "qapi/visitor.h" 28 #include "hw/i386/pc.h" 29 #include "hw/pci/pci.h" 30 #include "qemu/timer.h" 31 #include "sysemu/sysemu.h" 32 #include "hw/acpi/acpi.h" 33 #include "hw/acpi/tco.h" 34 #include "sysemu/kvm.h" 35 #include "exec/address-spaces.h" 36 37 #include "hw/i386/ich9.h" 38 #include "hw/mem/pc-dimm.h" 39 40 //#define DEBUG 41 42 #ifdef DEBUG 43 #define ICH9_DEBUG(fmt, ...) \ 44 do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0) 45 #else 46 #define ICH9_DEBUG(fmt, ...) do { } while (0) 47 #endif 48 49 static void ich9_pm_update_sci_fn(ACPIREGS *regs) 50 { 51 ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs); 52 acpi_update_sci(&pm->acpi_regs, pm->irq); 53 } 54 55 static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width) 56 { 57 ICH9LPCPMRegs *pm = opaque; 58 return acpi_gpe_ioport_readb(&pm->acpi_regs, addr); 59 } 60 61 static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 62 unsigned width) 63 { 64 ICH9LPCPMRegs *pm = opaque; 65 acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val); 66 acpi_update_sci(&pm->acpi_regs, pm->irq); 67 } 68 69 static const MemoryRegionOps ich9_gpe_ops = { 70 .read = ich9_gpe_readb, 71 .write = ich9_gpe_writeb, 72 .valid.min_access_size = 1, 73 .valid.max_access_size = 4, 74 .impl.min_access_size = 1, 75 .impl.max_access_size = 1, 76 .endianness = DEVICE_LITTLE_ENDIAN, 77 }; 78 79 static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width) 80 { 81 ICH9LPCPMRegs *pm = opaque; 82 switch (addr) { 83 case 0: 84 return pm->smi_en; 85 case 4: 86 return pm->smi_sts; 87 default: 88 return 0; 89 } 90 } 91 92 static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val, 93 unsigned width) 94 { 95 ICH9LPCPMRegs *pm = opaque; 96 TCOIORegs *tr = &pm->tco_regs; 97 uint64_t tco_en; 98 99 switch (addr) { 100 case 0: 101 tco_en = pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN; 102 /* once TCO_LOCK bit is set, TCO_EN bit cannot be overwritten */ 103 if (tr->tco.cnt1 & TCO_LOCK) { 104 val = (val & ~ICH9_PMIO_SMI_EN_TCO_EN) | tco_en; 105 } 106 pm->smi_en &= ~pm->smi_en_wmask; 107 pm->smi_en |= (val & pm->smi_en_wmask); 108 break; 109 } 110 } 111 112 static const MemoryRegionOps ich9_smi_ops = { 113 .read = ich9_smi_readl, 114 .write = ich9_smi_writel, 115 .valid.min_access_size = 4, 116 .valid.max_access_size = 4, 117 .endianness = DEVICE_LITTLE_ENDIAN, 118 }; 119 120 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base) 121 { 122 ICH9_DEBUG("to 0x%x\n", pm_io_base); 123 124 assert((pm_io_base & ICH9_PMIO_MASK) == 0); 125 126 pm->pm_io_base = pm_io_base; 127 memory_region_transaction_begin(); 128 memory_region_set_enabled(&pm->io, pm->pm_io_base != 0); 129 memory_region_set_address(&pm->io, pm->pm_io_base); 130 memory_region_transaction_commit(); 131 } 132 133 static int ich9_pm_post_load(void *opaque, int version_id) 134 { 135 ICH9LPCPMRegs *pm = opaque; 136 uint32_t pm_io_base = pm->pm_io_base; 137 pm->pm_io_base = 0; 138 ich9_pm_iospace_update(pm, pm_io_base); 139 return 0; 140 } 141 142 #define VMSTATE_GPE_ARRAY(_field, _state) \ 143 { \ 144 .name = (stringify(_field)), \ 145 .version_id = 0, \ 146 .num = ICH9_PMIO_GPE0_LEN, \ 147 .info = &vmstate_info_uint8, \ 148 .size = sizeof(uint8_t), \ 149 .flags = VMS_ARRAY | VMS_POINTER, \ 150 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 151 } 152 153 static bool vmstate_test_use_memhp(void *opaque) 154 { 155 ICH9LPCPMRegs *s = opaque; 156 return s->acpi_memory_hotplug.is_enabled; 157 } 158 159 static const VMStateDescription vmstate_memhp_state = { 160 .name = "ich9_pm/memhp", 161 .version_id = 1, 162 .minimum_version_id = 1, 163 .minimum_version_id_old = 1, 164 .needed = vmstate_test_use_memhp, 165 .fields = (VMStateField[]) { 166 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, ICH9LPCPMRegs), 167 VMSTATE_END_OF_LIST() 168 } 169 }; 170 171 static bool vmstate_test_use_tco(void *opaque) 172 { 173 ICH9LPCPMRegs *s = opaque; 174 return s->enable_tco; 175 } 176 177 static const VMStateDescription vmstate_tco_io_state = { 178 .name = "ich9_pm/tco", 179 .version_id = 1, 180 .minimum_version_id = 1, 181 .minimum_version_id_old = 1, 182 .needed = vmstate_test_use_tco, 183 .fields = (VMStateField[]) { 184 VMSTATE_STRUCT(tco_regs, ICH9LPCPMRegs, 1, vmstate_tco_io_sts, 185 TCOIORegs), 186 VMSTATE_END_OF_LIST() 187 } 188 }; 189 190 const VMStateDescription vmstate_ich9_pm = { 191 .name = "ich9_pm", 192 .version_id = 1, 193 .minimum_version_id = 1, 194 .post_load = ich9_pm_post_load, 195 .fields = (VMStateField[]) { 196 VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs), 197 VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs), 198 VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs), 199 VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, ICH9LPCPMRegs), 200 VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs), 201 VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs), 202 VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs), 203 VMSTATE_UINT32(smi_en, ICH9LPCPMRegs), 204 VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs), 205 VMSTATE_END_OF_LIST() 206 }, 207 .subsections = (const VMStateDescription*[]) { 208 &vmstate_memhp_state, 209 NULL 210 }, 211 .subsections = (const VMStateDescription*[]) { 212 &vmstate_tco_io_state, 213 NULL 214 } 215 }; 216 217 static void pm_reset(void *opaque) 218 { 219 ICH9LPCPMRegs *pm = opaque; 220 ich9_pm_iospace_update(pm, 0); 221 222 acpi_pm1_evt_reset(&pm->acpi_regs); 223 acpi_pm1_cnt_reset(&pm->acpi_regs); 224 acpi_pm_tmr_reset(&pm->acpi_regs); 225 acpi_gpe_reset(&pm->acpi_regs); 226 227 if (!pm->smm_enabled) { 228 /* Mark SMM as already inited to prevent SMM from running. KVM does not 229 * support SMM mode. */ 230 pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN; 231 } 232 pm->smi_en_wmask = ~0; 233 234 acpi_update_sci(&pm->acpi_regs, pm->irq); 235 } 236 237 static void pm_powerdown_req(Notifier *n, void *opaque) 238 { 239 ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier); 240 241 acpi_pm1_evt_power_down(&pm->acpi_regs); 242 } 243 244 void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, 245 bool smm_enabled, bool enable_tco, 246 qemu_irq sci_irq) 247 { 248 memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE); 249 memory_region_set_enabled(&pm->io, false); 250 memory_region_add_subregion(pci_address_space_io(lpc_pci), 251 0, &pm->io); 252 253 acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); 254 acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); 255 acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, pm->disable_s3, pm->disable_s4, 256 pm->s4_val); 257 258 acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN); 259 memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm, 260 "acpi-gpe0", ICH9_PMIO_GPE0_LEN); 261 memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe); 262 263 memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm, 264 "acpi-smi", 8); 265 memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi); 266 267 pm->smm_enabled = smm_enabled; 268 269 pm->enable_tco = enable_tco; 270 if (pm->enable_tco) { 271 acpi_pm_tco_init(&pm->tco_regs, &pm->io); 272 } 273 274 pm->irq = sci_irq; 275 qemu_register_reset(pm_reset, pm); 276 pm->powerdown_notifier.notify = pm_powerdown_req; 277 qemu_register_powerdown_notifier(&pm->powerdown_notifier); 278 279 acpi_cpu_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci), 280 &pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE); 281 282 if (pm->acpi_memory_hotplug.is_enabled) { 283 acpi_memory_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci), 284 &pm->acpi_memory_hotplug); 285 } 286 } 287 288 static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v, 289 void *opaque, const char *name, 290 Error **errp) 291 { 292 ICH9LPCPMRegs *pm = opaque; 293 uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS; 294 295 visit_type_uint32(v, &value, name, errp); 296 } 297 298 static bool ich9_pm_get_memory_hotplug_support(Object *obj, Error **errp) 299 { 300 ICH9LPCState *s = ICH9_LPC_DEVICE(obj); 301 302 return s->pm.acpi_memory_hotplug.is_enabled; 303 } 304 305 static void ich9_pm_set_memory_hotplug_support(Object *obj, bool value, 306 Error **errp) 307 { 308 ICH9LPCState *s = ICH9_LPC_DEVICE(obj); 309 310 s->pm.acpi_memory_hotplug.is_enabled = value; 311 } 312 313 static void ich9_pm_get_disable_s3(Object *obj, Visitor *v, 314 void *opaque, const char *name, 315 Error **errp) 316 { 317 ICH9LPCPMRegs *pm = opaque; 318 uint8_t value = pm->disable_s3; 319 320 visit_type_uint8(v, &value, name, errp); 321 } 322 323 static void ich9_pm_set_disable_s3(Object *obj, Visitor *v, 324 void *opaque, const char *name, 325 Error **errp) 326 { 327 ICH9LPCPMRegs *pm = opaque; 328 Error *local_err = NULL; 329 uint8_t value; 330 331 visit_type_uint8(v, &value, name, &local_err); 332 if (local_err) { 333 goto out; 334 } 335 pm->disable_s3 = value; 336 out: 337 error_propagate(errp, local_err); 338 } 339 340 static void ich9_pm_get_disable_s4(Object *obj, Visitor *v, 341 void *opaque, const char *name, 342 Error **errp) 343 { 344 ICH9LPCPMRegs *pm = opaque; 345 uint8_t value = pm->disable_s4; 346 347 visit_type_uint8(v, &value, name, errp); 348 } 349 350 static void ich9_pm_set_disable_s4(Object *obj, Visitor *v, 351 void *opaque, const char *name, 352 Error **errp) 353 { 354 ICH9LPCPMRegs *pm = opaque; 355 Error *local_err = NULL; 356 uint8_t value; 357 358 visit_type_uint8(v, &value, name, &local_err); 359 if (local_err) { 360 goto out; 361 } 362 pm->disable_s4 = value; 363 out: 364 error_propagate(errp, local_err); 365 } 366 367 static void ich9_pm_get_s4_val(Object *obj, Visitor *v, 368 void *opaque, const char *name, 369 Error **errp) 370 { 371 ICH9LPCPMRegs *pm = opaque; 372 uint8_t value = pm->s4_val; 373 374 visit_type_uint8(v, &value, name, errp); 375 } 376 377 static void ich9_pm_set_s4_val(Object *obj, Visitor *v, 378 void *opaque, const char *name, 379 Error **errp) 380 { 381 ICH9LPCPMRegs *pm = opaque; 382 Error *local_err = NULL; 383 uint8_t value; 384 385 visit_type_uint8(v, &value, name, &local_err); 386 if (local_err) { 387 goto out; 388 } 389 pm->s4_val = value; 390 out: 391 error_propagate(errp, local_err); 392 } 393 394 static bool ich9_pm_get_enable_tco(Object *obj, Error **errp) 395 { 396 ICH9LPCState *s = ICH9_LPC_DEVICE(obj); 397 return s->pm.enable_tco; 398 } 399 400 static void ich9_pm_set_enable_tco(Object *obj, bool value, Error **errp) 401 { 402 ICH9LPCState *s = ICH9_LPC_DEVICE(obj); 403 s->pm.enable_tco = value; 404 } 405 406 void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp) 407 { 408 static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN; 409 pm->acpi_memory_hotplug.is_enabled = true; 410 pm->disable_s3 = 0; 411 pm->disable_s4 = 0; 412 pm->s4_val = 2; 413 414 object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE, 415 &pm->pm_io_base, errp); 416 object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32", 417 ich9_pm_get_gpe0_blk, 418 NULL, NULL, pm, NULL); 419 object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN, 420 &gpe0_len, errp); 421 object_property_add_bool(obj, "memory-hotplug-support", 422 ich9_pm_get_memory_hotplug_support, 423 ich9_pm_set_memory_hotplug_support, 424 NULL); 425 object_property_add(obj, ACPI_PM_PROP_S3_DISABLED, "uint8", 426 ich9_pm_get_disable_s3, 427 ich9_pm_set_disable_s3, 428 NULL, pm, NULL); 429 object_property_add(obj, ACPI_PM_PROP_S4_DISABLED, "uint8", 430 ich9_pm_get_disable_s4, 431 ich9_pm_set_disable_s4, 432 NULL, pm, NULL); 433 object_property_add(obj, ACPI_PM_PROP_S4_VAL, "uint8", 434 ich9_pm_get_s4_val, 435 ich9_pm_set_s4_val, 436 NULL, pm, NULL); 437 object_property_add_bool(obj, ACPI_PM_PROP_TCO_ENABLED, 438 ich9_pm_get_enable_tco, 439 ich9_pm_set_enable_tco, 440 NULL); 441 } 442 443 void ich9_pm_device_plug_cb(ICH9LPCPMRegs *pm, DeviceState *dev, Error **errp) 444 { 445 if (pm->acpi_memory_hotplug.is_enabled && 446 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 447 acpi_memory_plug_cb(&pm->acpi_regs, pm->irq, &pm->acpi_memory_hotplug, 448 dev, errp); 449 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 450 acpi_cpu_plug_cb(&pm->acpi_regs, pm->irq, &pm->gpe_cpu, dev, errp); 451 } else { 452 error_setg(errp, "acpi: device plug request for not supported device" 453 " type: %s", object_get_typename(OBJECT(dev))); 454 } 455 } 456 457 void ich9_pm_device_unplug_request_cb(ICH9LPCPMRegs *pm, DeviceState *dev, 458 Error **errp) 459 { 460 if (pm->acpi_memory_hotplug.is_enabled && 461 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 462 acpi_memory_unplug_request_cb(&pm->acpi_regs, pm->irq, 463 &pm->acpi_memory_hotplug, dev, errp); 464 } else { 465 error_setg(errp, "acpi: device unplug request for not supported device" 466 " type: %s", object_get_typename(OBJECT(dev))); 467 } 468 } 469 470 void ich9_pm_device_unplug_cb(ICH9LPCPMRegs *pm, DeviceState *dev, 471 Error **errp) 472 { 473 if (pm->acpi_memory_hotplug.is_enabled && 474 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 475 acpi_memory_unplug_cb(&pm->acpi_memory_hotplug, dev, errp); 476 } else { 477 error_setg(errp, "acpi: device unplug for not supported device" 478 " type: %s", object_get_typename(OBJECT(dev))); 479 } 480 } 481 482 void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) 483 { 484 ICH9LPCState *s = ICH9_LPC_DEVICE(adev); 485 486 acpi_memory_ospm_status(&s->pm.acpi_memory_hotplug, list); 487 } 488