1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> 6 * VA Linux Systems Japan K.K. 7 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 8 * 9 * This is based on acpi.c. 10 * 11 * This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU Lesser General Public 13 * License version 2 as published by the Free Software Foundation. 14 * 15 * This library is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * Lesser General Public License for more details. 19 * 20 * You should have received a copy of the GNU Lesser General Public 21 * License along with this library; if not, see <http://www.gnu.org/licenses/> 22 * 23 * Contributions after 2012-01-13 are licensed under the terms of the 24 * GNU GPL, version 2 or (at your option) any later version. 25 */ 26 #include "hw/hw.h" 27 #include "hw/i386/pc.h" 28 #include "hw/pci/pci.h" 29 #include "qemu/timer.h" 30 #include "sysemu/sysemu.h" 31 #include "hw/acpi/acpi.h" 32 #include "sysemu/kvm.h" 33 #include "exec/address-spaces.h" 34 35 #include "hw/i386/ich9.h" 36 37 //#define DEBUG 38 39 #ifdef DEBUG 40 #define ICH9_DEBUG(fmt, ...) \ 41 do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0) 42 #else 43 #define ICH9_DEBUG(fmt, ...) do { } while (0) 44 #endif 45 46 static void pm_update_sci(ICH9LPCPMRegs *pm) 47 { 48 int sci_level, pm1a_sts; 49 50 pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs); 51 52 sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) & 53 (ACPI_BITMASK_RT_CLOCK_ENABLE | 54 ACPI_BITMASK_POWER_BUTTON_ENABLE | 55 ACPI_BITMASK_GLOBAL_LOCK_ENABLE | 56 ACPI_BITMASK_TIMER_ENABLE)) != 0); 57 qemu_set_irq(pm->irq, sci_level); 58 59 /* schedule a timer interruption if needed */ 60 acpi_pm_tmr_update(&pm->acpi_regs, 61 (pm->acpi_regs.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && 62 !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS)); 63 } 64 65 static void ich9_pm_update_sci_fn(ACPIREGS *regs) 66 { 67 ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs); 68 pm_update_sci(pm); 69 } 70 71 static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width) 72 { 73 ICH9LPCPMRegs *pm = opaque; 74 return acpi_gpe_ioport_readb(&pm->acpi_regs, addr); 75 } 76 77 static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 78 unsigned width) 79 { 80 ICH9LPCPMRegs *pm = opaque; 81 acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val); 82 } 83 84 static const MemoryRegionOps ich9_gpe_ops = { 85 .read = ich9_gpe_readb, 86 .write = ich9_gpe_writeb, 87 .valid.min_access_size = 1, 88 .valid.max_access_size = 4, 89 .impl.min_access_size = 1, 90 .impl.max_access_size = 1, 91 .endianness = DEVICE_LITTLE_ENDIAN, 92 }; 93 94 static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width) 95 { 96 ICH9LPCPMRegs *pm = opaque; 97 switch (addr) { 98 case 0: 99 return pm->smi_en; 100 case 4: 101 return pm->smi_sts; 102 default: 103 return 0; 104 } 105 } 106 107 static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val, 108 unsigned width) 109 { 110 ICH9LPCPMRegs *pm = opaque; 111 switch (addr) { 112 case 0: 113 pm->smi_en = val; 114 break; 115 } 116 } 117 118 static const MemoryRegionOps ich9_smi_ops = { 119 .read = ich9_smi_readl, 120 .write = ich9_smi_writel, 121 .valid.min_access_size = 4, 122 .valid.max_access_size = 4, 123 .endianness = DEVICE_LITTLE_ENDIAN, 124 }; 125 126 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base) 127 { 128 ICH9_DEBUG("to 0x%x\n", pm_io_base); 129 130 assert((pm_io_base & ICH9_PMIO_MASK) == 0); 131 132 pm->pm_io_base = pm_io_base; 133 memory_region_transaction_begin(); 134 memory_region_set_enabled(&pm->io, pm->pm_io_base != 0); 135 memory_region_set_address(&pm->io, pm->pm_io_base); 136 memory_region_transaction_commit(); 137 } 138 139 static int ich9_pm_post_load(void *opaque, int version_id) 140 { 141 ICH9LPCPMRegs *pm = opaque; 142 uint32_t pm_io_base = pm->pm_io_base; 143 pm->pm_io_base = 0; 144 ich9_pm_iospace_update(pm, pm_io_base); 145 return 0; 146 } 147 148 #define VMSTATE_GPE_ARRAY(_field, _state) \ 149 { \ 150 .name = (stringify(_field)), \ 151 .version_id = 0, \ 152 .num = ICH9_PMIO_GPE0_LEN, \ 153 .info = &vmstate_info_uint8, \ 154 .size = sizeof(uint8_t), \ 155 .flags = VMS_ARRAY | VMS_POINTER, \ 156 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 157 } 158 159 const VMStateDescription vmstate_ich9_pm = { 160 .name = "ich9_pm", 161 .version_id = 1, 162 .minimum_version_id = 1, 163 .minimum_version_id_old = 1, 164 .post_load = ich9_pm_post_load, 165 .fields = (VMStateField[]) { 166 VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs), 167 VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs), 168 VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs), 169 VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs), 170 VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs), 171 VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs), 172 VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs), 173 VMSTATE_UINT32(smi_en, ICH9LPCPMRegs), 174 VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs), 175 VMSTATE_END_OF_LIST() 176 } 177 }; 178 179 static void pm_reset(void *opaque) 180 { 181 ICH9LPCPMRegs *pm = opaque; 182 ich9_pm_iospace_update(pm, 0); 183 184 acpi_pm1_evt_reset(&pm->acpi_regs); 185 acpi_pm1_cnt_reset(&pm->acpi_regs); 186 acpi_pm_tmr_reset(&pm->acpi_regs); 187 acpi_gpe_reset(&pm->acpi_regs); 188 189 if (kvm_enabled()) { 190 /* Mark SMM as already inited to prevent SMM from running. KVM does not 191 * support SMM mode. */ 192 pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN; 193 } 194 195 pm_update_sci(pm); 196 } 197 198 static void pm_powerdown_req(Notifier *n, void *opaque) 199 { 200 ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier); 201 202 acpi_pm1_evt_power_down(&pm->acpi_regs); 203 } 204 205 void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, 206 qemu_irq sci_irq) 207 { 208 memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE); 209 memory_region_set_enabled(&pm->io, false); 210 memory_region_add_subregion(pci_address_space_io(lpc_pci), 211 0, &pm->io); 212 213 acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); 214 acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); 215 acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, 2); 216 217 acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN); 218 memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm, 219 "apci-gpe0", ICH9_PMIO_GPE0_LEN); 220 memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe); 221 222 memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm, 223 "apci-smi", 8); 224 memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi); 225 226 pm->irq = sci_irq; 227 qemu_register_reset(pm_reset, pm); 228 pm->powerdown_notifier.notify = pm_powerdown_req; 229 qemu_register_powerdown_notifier(&pm->powerdown_notifier); 230 } 231