1/*
2 * QEMU float support
3 *
4 * The code in this source file is derived from release 2a of the SoftFloat
5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
6 * some later contributions) are provided under that license, as detailed below.
7 * It has subsequently been modified by contributors to the QEMU Project,
8 * so some portions are provided under:
9 *  the SoftFloat-2a license
10 *  the BSD license
11 *  GPL-v2-or-later
12 *
13 * Any future contributions to this file after December 1st 2014 will be
14 * taken to be licensed under the Softfloat-2a license unless specifically
15 * indicated otherwise.
16 */
17
18/*
19===============================================================================
20This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
21Arithmetic Package, Release 2a.
22
23Written by John R. Hauser.  This work was made possible in part by the
24International Computer Science Institute, located at Suite 600, 1947 Center
25Street, Berkeley, California 94704.  Funding was partially provided by the
26National Science Foundation under grant MIP-9311980.  The original version
27of this code was written as part of a project to build a fixed-point vector
28processor in collaboration with the University of California at Berkeley,
29overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
30is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
31arithmetic/SoftFloat.html'.
32
33THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort
34has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
35TIMES RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO
36PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
37AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
38
39Derivative works are acceptable, even for commercial purposes, so long as
40(1) they include prominent notice that the work is derivative, and (2) they
41include prominent notice akin to these four paragraphs for those parts of
42this code that are retained.
43
44===============================================================================
45*/
46
47/* BSD licensing:
48 * Copyright (c) 2006, Fabrice Bellard
49 * All rights reserved.
50 *
51 * Redistribution and use in source and binary forms, with or without
52 * modification, are permitted provided that the following conditions are met:
53 *
54 * 1. Redistributions of source code must retain the above copyright notice,
55 * this list of conditions and the following disclaimer.
56 *
57 * 2. Redistributions in binary form must reproduce the above copyright notice,
58 * this list of conditions and the following disclaimer in the documentation
59 * and/or other materials provided with the distribution.
60 *
61 * 3. Neither the name of the copyright holder nor the names of its contributors
62 * may be used to endorse or promote products derived from this software without
63 * specific prior written permission.
64 *
65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
68 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
69 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
70 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
71 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
72 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
73 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
74 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
75 * THE POSSIBILITY OF SUCH DAMAGE.
76 */
77
78/* Portions of this work are licensed under the terms of the GNU GPL,
79 * version 2 or later. See the COPYING file in the top-level directory.
80 */
81
82/*
83 * Define whether architecture deviates from IEEE in not supporting
84 * signaling NaNs (so all NaNs are treated as quiet).
85 */
86static inline bool no_signaling_nans(float_status *status)
87{
88#if defined(TARGET_XTENSA)
89    return status->no_signaling_nans;
90#else
91    return false;
92#endif
93}
94
95/* Define how the architecture discriminates signaling NaNs.
96 * This done with the most significant bit of the fraction.
97 * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
98 * the msb must be zero.  MIPS is (so far) unique in supporting both the
99 * 2008 revision and backward compatibility with their original choice.
100 * Thus for MIPS we must make the choice at runtime.
101 */
102static inline bool snan_bit_is_one(float_status *status)
103{
104#if defined(TARGET_MIPS)
105    return status->snan_bit_is_one;
106#elif defined(TARGET_HPPA) || defined(TARGET_SH4)
107    return 1;
108#else
109    return 0;
110#endif
111}
112
113/*----------------------------------------------------------------------------
114| For the deconstructed floating-point with fraction FRAC, return true
115| if the fraction represents a signalling NaN; otherwise false.
116*----------------------------------------------------------------------------*/
117
118static bool parts_is_snan_frac(uint64_t frac, float_status *status)
119{
120    if (no_signaling_nans(status)) {
121        return false;
122    } else {
123        bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
124        return msb == snan_bit_is_one(status);
125    }
126}
127
128/*----------------------------------------------------------------------------
129| The pattern for a default generated deconstructed floating-point NaN.
130*----------------------------------------------------------------------------*/
131
132static void parts64_default_nan(FloatParts64 *p, float_status *status)
133{
134    bool sign = 0;
135    uint64_t frac;
136
137#if defined(TARGET_SPARC) || defined(TARGET_M68K)
138    /* !snan_bit_is_one, set all bits */
139    frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
140#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
141    || defined(TARGET_MICROBLAZE)
142    /* !snan_bit_is_one, set sign and msb */
143    frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
144    sign = 1;
145#elif defined(TARGET_HPPA)
146    /* snan_bit_is_one, set msb-1.  */
147    frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
148#elif defined(TARGET_HEXAGON)
149    sign = 1;
150    frac = ~0ULL;
151#else
152    /*
153     * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
154     * S390, SH4, TriCore, and Xtensa.  Our other supported targets,
155     * CRIS and Nios2, do not have floating-point.
156     */
157    if (snan_bit_is_one(status)) {
158        /* set all bits other than msb */
159        frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
160    } else {
161        /* set msb */
162        frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
163    }
164#endif
165
166    *p = (FloatParts64) {
167        .cls = float_class_qnan,
168        .sign = sign,
169        .exp = INT_MAX,
170        .frac = frac
171    };
172}
173
174static void parts128_default_nan(FloatParts128 *p, float_status *status)
175{
176    /*
177     * Extrapolate from the choices made by parts64_default_nan to fill
178     * in the quad-floating format.  If the low bit is set, assume we
179     * want to set all non-snan bits.
180     */
181    FloatParts64 p64;
182    parts64_default_nan(&p64, status);
183
184    *p = (FloatParts128) {
185        .cls = float_class_qnan,
186        .sign = p64.sign,
187        .exp = INT_MAX,
188        .frac_hi = p64.frac,
189        .frac_lo = -(p64.frac & 1)
190    };
191}
192
193/*----------------------------------------------------------------------------
194| Returns a quiet NaN from a signalling NaN for the deconstructed
195| floating-point parts.
196*----------------------------------------------------------------------------*/
197
198static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status)
199{
200    g_assert(!no_signaling_nans(status));
201
202    /* The only snan_bit_is_one target without default_nan_mode is HPPA. */
203    if (snan_bit_is_one(status)) {
204        frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
205        frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
206    } else {
207        frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
208    }
209    return frac;
210}
211
212static void parts64_silence_nan(FloatParts64 *p, float_status *status)
213{
214    p->frac = parts_silence_nan_frac(p->frac, status);
215    p->cls = float_class_qnan;
216}
217
218static void parts128_silence_nan(FloatParts128 *p, float_status *status)
219{
220    p->frac_hi = parts_silence_nan_frac(p->frac_hi, status);
221    p->cls = float_class_qnan;
222}
223
224/*----------------------------------------------------------------------------
225| The pattern for a default generated extended double-precision NaN.
226*----------------------------------------------------------------------------*/
227floatx80 floatx80_default_nan(float_status *status)
228{
229    floatx80 r;
230
231    /* None of the targets that have snan_bit_is_one use floatx80.  */
232    assert(!snan_bit_is_one(status));
233#if defined(TARGET_M68K)
234    r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
235    r.high = 0x7FFF;
236#else
237    /* X86 */
238    r.low = UINT64_C(0xC000000000000000);
239    r.high = 0xFFFF;
240#endif
241    return r;
242}
243
244/*----------------------------------------------------------------------------
245| The pattern for a default generated extended double-precision inf.
246*----------------------------------------------------------------------------*/
247
248#define floatx80_infinity_high 0x7FFF
249#if defined(TARGET_M68K)
250#define floatx80_infinity_low  UINT64_C(0x0000000000000000)
251#else
252#define floatx80_infinity_low  UINT64_C(0x8000000000000000)
253#endif
254
255const floatx80 floatx80_infinity
256    = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low);
257
258/*----------------------------------------------------------------------------
259| Returns 1 if the half-precision floating-point value `a' is a quiet
260| NaN; otherwise returns 0.
261*----------------------------------------------------------------------------*/
262
263bool float16_is_quiet_nan(float16 a_, float_status *status)
264{
265    if (no_signaling_nans(status)) {
266        return float16_is_any_nan(a_);
267    } else {
268        uint16_t a = float16_val(a_);
269        if (snan_bit_is_one(status)) {
270            return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
271        } else {
272
273            return ((a >> 9) & 0x3F) == 0x3F;
274        }
275    }
276}
277
278/*----------------------------------------------------------------------------
279| Returns 1 if the bfloat16 value `a' is a quiet
280| NaN; otherwise returns 0.
281*----------------------------------------------------------------------------*/
282
283bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status)
284{
285    if (no_signaling_nans(status)) {
286        return bfloat16_is_any_nan(a_);
287    } else {
288        uint16_t a = a_;
289        if (snan_bit_is_one(status)) {
290            return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
291        } else {
292            return ((a >> 6) & 0x1FF) == 0x1FF;
293        }
294    }
295}
296
297/*----------------------------------------------------------------------------
298| Returns 1 if the half-precision floating-point value `a' is a signaling
299| NaN; otherwise returns 0.
300*----------------------------------------------------------------------------*/
301
302bool float16_is_signaling_nan(float16 a_, float_status *status)
303{
304    if (no_signaling_nans(status)) {
305        return 0;
306    } else {
307        uint16_t a = float16_val(a_);
308        if (snan_bit_is_one(status)) {
309            return ((a >> 9) & 0x3F) == 0x3F;
310        } else {
311            return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
312        }
313    }
314}
315
316/*----------------------------------------------------------------------------
317| Returns 1 if the bfloat16 value `a' is a signaling
318| NaN; otherwise returns 0.
319*----------------------------------------------------------------------------*/
320
321bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status)
322{
323    if (no_signaling_nans(status)) {
324        return 0;
325    } else {
326        uint16_t a = a_;
327        if (snan_bit_is_one(status)) {
328            return ((a >> 6) & 0x1FF) == 0x1FF;
329        } else {
330            return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
331        }
332    }
333}
334
335/*----------------------------------------------------------------------------
336| Returns 1 if the single-precision floating-point value `a' is a quiet
337| NaN; otherwise returns 0.
338*----------------------------------------------------------------------------*/
339
340bool float32_is_quiet_nan(float32 a_, float_status *status)
341{
342    if (no_signaling_nans(status)) {
343        return float32_is_any_nan(a_);
344    } else {
345        uint32_t a = float32_val(a_);
346        if (snan_bit_is_one(status)) {
347            return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
348        } else {
349            return ((uint32_t)(a << 1) >= 0xFF800000);
350        }
351    }
352}
353
354/*----------------------------------------------------------------------------
355| Returns 1 if the single-precision floating-point value `a' is a signaling
356| NaN; otherwise returns 0.
357*----------------------------------------------------------------------------*/
358
359bool float32_is_signaling_nan(float32 a_, float_status *status)
360{
361    if (no_signaling_nans(status)) {
362        return 0;
363    } else {
364        uint32_t a = float32_val(a_);
365        if (snan_bit_is_one(status)) {
366            return ((uint32_t)(a << 1) >= 0xFF800000);
367        } else {
368            return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
369        }
370    }
371}
372
373/*----------------------------------------------------------------------------
374| Select which NaN to propagate for a two-input operation.
375| IEEE754 doesn't specify all the details of this, so the
376| algorithm is target-specific.
377| The routine is passed various bits of information about the
378| two NaNs and should return 0 to select NaN a and 1 for NaN b.
379| Note that signalling NaNs are always squashed to quiet NaNs
380| by the caller, by calling floatXX_silence_nan() before
381| returning them.
382|
383| aIsLargerSignificand is only valid if both a and b are NaNs
384| of some kind, and is true if a has the larger significand,
385| or if both a and b have the same significand but a is
386| positive but b is negative. It is only needed for the x87
387| tie-break rule.
388*----------------------------------------------------------------------------*/
389
390static int pickNaN(FloatClass a_cls, FloatClass b_cls,
391                   bool aIsLargerSignificand, float_status *status)
392{
393#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) || \
394    defined(TARGET_LOONGARCH64) || defined(TARGET_S390X)
395    /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
396     * the first of:
397     *  1. A if it is signaling
398     *  2. B if it is signaling
399     *  3. A (quiet)
400     *  4. B (quiet)
401     * A signaling NaN is always quietened before returning it.
402     */
403    /* According to MIPS specifications, if one of the two operands is
404     * a sNaN, a new qNaN has to be generated. This is done in
405     * floatXX_silence_nan(). For qNaN inputs the specifications
406     * says: "When possible, this QNaN result is one of the operand QNaN
407     * values." In practice it seems that most implementations choose
408     * the first operand if both operands are qNaN. In short this gives
409     * the following rules:
410     *  1. A if it is signaling
411     *  2. B if it is signaling
412     *  3. A (quiet)
413     *  4. B (quiet)
414     * A signaling NaN is always silenced before returning it.
415     */
416    if (is_snan(a_cls)) {
417        return 0;
418    } else if (is_snan(b_cls)) {
419        return 1;
420    } else if (is_qnan(a_cls)) {
421        return 0;
422    } else {
423        return 1;
424    }
425#elif defined(TARGET_PPC) || defined(TARGET_M68K)
426    /* PowerPC propagation rules:
427     *  1. A if it sNaN or qNaN
428     *  2. B if it sNaN or qNaN
429     * A signaling NaN is always silenced before returning it.
430     */
431    /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
432     * 3.4 FLOATING-POINT INSTRUCTION DETAILS
433     * If either operand, but not both operands, of an operation is a
434     * nonsignaling NaN, then that NaN is returned as the result. If both
435     * operands are nonsignaling NaNs, then the destination operand
436     * nonsignaling NaN is returned as the result.
437     * If either operand to an operation is a signaling NaN (SNaN), then the
438     * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
439     * is set in the FPCR ENABLE byte, then the exception is taken and the
440     * destination is not modified. If the SNaN exception enable bit is not
441     * set, setting the SNaN bit in the operand to a one converts the SNaN to
442     * a nonsignaling NaN. The operation then continues as described in the
443     * preceding paragraph for nonsignaling NaNs.
444     */
445    if (is_nan(a_cls)) {
446        return 0;
447    } else {
448        return 1;
449    }
450#elif defined(TARGET_XTENSA)
451    /*
452     * Xtensa has two NaN propagation modes.
453     * Which one is active is controlled by float_status::use_first_nan.
454     */
455    if (status->use_first_nan) {
456        if (is_nan(a_cls)) {
457            return 0;
458        } else {
459            return 1;
460        }
461    } else {
462        if (is_nan(b_cls)) {
463            return 1;
464        } else {
465            return 0;
466        }
467    }
468#else
469    /* This implements x87 NaN propagation rules:
470     * SNaN + QNaN => return the QNaN
471     * two SNaNs => return the one with the larger significand, silenced
472     * two QNaNs => return the one with the larger significand
473     * SNaN and a non-NaN => return the SNaN, silenced
474     * QNaN and a non-NaN => return the QNaN
475     *
476     * If we get down to comparing significands and they are the same,
477     * return the NaN with the positive sign bit (if any).
478     */
479    if (is_snan(a_cls)) {
480        if (is_snan(b_cls)) {
481            return aIsLargerSignificand ? 0 : 1;
482        }
483        return is_qnan(b_cls) ? 1 : 0;
484    } else if (is_qnan(a_cls)) {
485        if (is_snan(b_cls) || !is_qnan(b_cls)) {
486            return 0;
487        } else {
488            return aIsLargerSignificand ? 0 : 1;
489        }
490    } else {
491        return 1;
492    }
493#endif
494}
495
496/*----------------------------------------------------------------------------
497| Select which NaN to propagate for a three-input operation.
498| For the moment we assume that no CPU needs the 'larger significand'
499| information.
500| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
501*----------------------------------------------------------------------------*/
502static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
503                         bool infzero, float_status *status)
504{
505#if defined(TARGET_ARM)
506    /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
507     * the default NaN
508     */
509    if (infzero && is_qnan(c_cls)) {
510        float_raise(float_flag_invalid | float_flag_invalid_imz, status);
511        return 3;
512    }
513
514    /* This looks different from the ARM ARM pseudocode, because the ARM ARM
515     * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
516     */
517    if (is_snan(c_cls)) {
518        return 2;
519    } else if (is_snan(a_cls)) {
520        return 0;
521    } else if (is_snan(b_cls)) {
522        return 1;
523    } else if (is_qnan(c_cls)) {
524        return 2;
525    } else if (is_qnan(a_cls)) {
526        return 0;
527    } else {
528        return 1;
529    }
530#elif defined(TARGET_MIPS)
531    if (snan_bit_is_one(status)) {
532        /*
533         * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
534         * case sets InvalidOp and returns the default NaN
535         */
536        if (infzero) {
537            float_raise(float_flag_invalid | float_flag_invalid_imz, status);
538            return 3;
539        }
540        /* Prefer sNaN over qNaN, in the a, b, c order. */
541        if (is_snan(a_cls)) {
542            return 0;
543        } else if (is_snan(b_cls)) {
544            return 1;
545        } else if (is_snan(c_cls)) {
546            return 2;
547        } else if (is_qnan(a_cls)) {
548            return 0;
549        } else if (is_qnan(b_cls)) {
550            return 1;
551        } else {
552            return 2;
553        }
554    } else {
555        /*
556         * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
557         * case sets InvalidOp and returns the input value 'c'
558         */
559        if (infzero) {
560            float_raise(float_flag_invalid | float_flag_invalid_imz, status);
561            return 2;
562        }
563        /* Prefer sNaN over qNaN, in the c, a, b order. */
564        if (is_snan(c_cls)) {
565            return 2;
566        } else if (is_snan(a_cls)) {
567            return 0;
568        } else if (is_snan(b_cls)) {
569            return 1;
570        } else if (is_qnan(c_cls)) {
571            return 2;
572        } else if (is_qnan(a_cls)) {
573            return 0;
574        } else {
575            return 1;
576        }
577    }
578#elif defined(TARGET_LOONGARCH64)
579    /*
580     * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
581     * case sets InvalidOp and returns the input value 'c'
582     */
583    if (infzero) {
584        float_raise(float_flag_invalid | float_flag_invalid_imz, status);
585        return 2;
586    }
587    /* Prefer sNaN over qNaN, in the c, a, b order. */
588    if (is_snan(c_cls)) {
589        return 2;
590    } else if (is_snan(a_cls)) {
591        return 0;
592    } else if (is_snan(b_cls)) {
593        return 1;
594    } else if (is_qnan(c_cls)) {
595        return 2;
596    } else if (is_qnan(a_cls)) {
597        return 0;
598    } else {
599        return 1;
600    }
601#elif defined(TARGET_PPC)
602    /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
603     * to return an input NaN if we have one (ie c) rather than generating
604     * a default NaN
605     */
606    if (infzero) {
607        float_raise(float_flag_invalid | float_flag_invalid_imz, status);
608        return 2;
609    }
610
611    /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
612     * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
613     */
614    if (is_nan(a_cls)) {
615        return 0;
616    } else if (is_nan(c_cls)) {
617        return 2;
618    } else {
619        return 1;
620    }
621#elif defined(TARGET_RISCV)
622    /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
623    if (infzero) {
624        float_raise(float_flag_invalid | float_flag_invalid_imz, status);
625    }
626    return 3; /* default NaN */
627#elif defined(TARGET_XTENSA)
628    /*
629     * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
630     * an input NaN if we have one (ie c).
631     */
632    if (infzero) {
633        float_raise(float_flag_invalid | float_flag_invalid_imz, status);
634        return 2;
635    }
636    if (status->use_first_nan) {
637        if (is_nan(a_cls)) {
638            return 0;
639        } else if (is_nan(b_cls)) {
640            return 1;
641        } else {
642            return 2;
643        }
644    } else {
645        if (is_nan(c_cls)) {
646            return 2;
647        } else if (is_nan(b_cls)) {
648            return 1;
649        } else {
650            return 0;
651        }
652    }
653#else
654    /* A default implementation: prefer a to b to c.
655     * This is unlikely to actually match any real implementation.
656     */
657    if (is_nan(a_cls)) {
658        return 0;
659    } else if (is_nan(b_cls)) {
660        return 1;
661    } else {
662        return 2;
663    }
664#endif
665}
666
667/*----------------------------------------------------------------------------
668| Returns 1 if the double-precision floating-point value `a' is a quiet
669| NaN; otherwise returns 0.
670*----------------------------------------------------------------------------*/
671
672bool float64_is_quiet_nan(float64 a_, float_status *status)
673{
674    if (no_signaling_nans(status)) {
675        return float64_is_any_nan(a_);
676    } else {
677        uint64_t a = float64_val(a_);
678        if (snan_bit_is_one(status)) {
679            return (((a >> 51) & 0xFFF) == 0xFFE)
680                && (a & 0x0007FFFFFFFFFFFFULL);
681        } else {
682            return ((a << 1) >= 0xFFF0000000000000ULL);
683        }
684    }
685}
686
687/*----------------------------------------------------------------------------
688| Returns 1 if the double-precision floating-point value `a' is a signaling
689| NaN; otherwise returns 0.
690*----------------------------------------------------------------------------*/
691
692bool float64_is_signaling_nan(float64 a_, float_status *status)
693{
694    if (no_signaling_nans(status)) {
695        return 0;
696    } else {
697        uint64_t a = float64_val(a_);
698        if (snan_bit_is_one(status)) {
699            return ((a << 1) >= 0xFFF0000000000000ULL);
700        } else {
701            return (((a >> 51) & 0xFFF) == 0xFFE)
702                && (a & UINT64_C(0x0007FFFFFFFFFFFF));
703        }
704    }
705}
706
707/*----------------------------------------------------------------------------
708| Returns 1 if the extended double-precision floating-point value `a' is a
709| quiet NaN; otherwise returns 0. This slightly differs from the same
710| function for other types as floatx80 has an explicit bit.
711*----------------------------------------------------------------------------*/
712
713int floatx80_is_quiet_nan(floatx80 a, float_status *status)
714{
715    if (no_signaling_nans(status)) {
716        return floatx80_is_any_nan(a);
717    } else {
718        if (snan_bit_is_one(status)) {
719            uint64_t aLow;
720
721            aLow = a.low & ~0x4000000000000000ULL;
722            return ((a.high & 0x7FFF) == 0x7FFF)
723                && (aLow << 1)
724                && (a.low == aLow);
725        } else {
726            return ((a.high & 0x7FFF) == 0x7FFF)
727                && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
728        }
729    }
730}
731
732/*----------------------------------------------------------------------------
733| Returns 1 if the extended double-precision floating-point value `a' is a
734| signaling NaN; otherwise returns 0. This slightly differs from the same
735| function for other types as floatx80 has an explicit bit.
736*----------------------------------------------------------------------------*/
737
738int floatx80_is_signaling_nan(floatx80 a, float_status *status)
739{
740    if (no_signaling_nans(status)) {
741        return 0;
742    } else {
743        if (snan_bit_is_one(status)) {
744            return ((a.high & 0x7FFF) == 0x7FFF)
745                && ((a.low << 1) >= 0x8000000000000000ULL);
746        } else {
747            uint64_t aLow;
748
749            aLow = a.low & ~UINT64_C(0x4000000000000000);
750            return ((a.high & 0x7FFF) == 0x7FFF)
751                && (uint64_t)(aLow << 1)
752                && (a.low == aLow);
753        }
754    }
755}
756
757/*----------------------------------------------------------------------------
758| Returns a quiet NaN from a signalling NaN for the extended double-precision
759| floating point value `a'.
760*----------------------------------------------------------------------------*/
761
762floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
763{
764    /* None of the targets that have snan_bit_is_one use floatx80.  */
765    assert(!snan_bit_is_one(status));
766    a.low |= UINT64_C(0xC000000000000000);
767    return a;
768}
769
770/*----------------------------------------------------------------------------
771| Takes two extended double-precision floating-point values `a' and `b', one
772| of which is a NaN, and returns the appropriate NaN result.  If either `a' or
773| `b' is a signaling NaN, the invalid exception is raised.
774*----------------------------------------------------------------------------*/
775
776floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
777{
778    bool aIsLargerSignificand;
779    FloatClass a_cls, b_cls;
780
781    /* This is not complete, but is good enough for pickNaN.  */
782    a_cls = (!floatx80_is_any_nan(a)
783             ? float_class_normal
784             : floatx80_is_signaling_nan(a, status)
785             ? float_class_snan
786             : float_class_qnan);
787    b_cls = (!floatx80_is_any_nan(b)
788             ? float_class_normal
789             : floatx80_is_signaling_nan(b, status)
790             ? float_class_snan
791             : float_class_qnan);
792
793    if (is_snan(a_cls) || is_snan(b_cls)) {
794        float_raise(float_flag_invalid, status);
795    }
796
797    if (status->default_nan_mode) {
798        return floatx80_default_nan(status);
799    }
800
801    if (a.low < b.low) {
802        aIsLargerSignificand = 0;
803    } else if (b.low < a.low) {
804        aIsLargerSignificand = 1;
805    } else {
806        aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
807    }
808
809    if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
810        if (is_snan(b_cls)) {
811            return floatx80_silence_nan(b, status);
812        }
813        return b;
814    } else {
815        if (is_snan(a_cls)) {
816            return floatx80_silence_nan(a, status);
817        }
818        return a;
819    }
820}
821
822/*----------------------------------------------------------------------------
823| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
824| NaN; otherwise returns 0.
825*----------------------------------------------------------------------------*/
826
827bool float128_is_quiet_nan(float128 a, float_status *status)
828{
829    if (no_signaling_nans(status)) {
830        return float128_is_any_nan(a);
831    } else {
832        if (snan_bit_is_one(status)) {
833            return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
834                && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
835        } else {
836            return ((a.high << 1) >= 0xFFFF000000000000ULL)
837                && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
838        }
839    }
840}
841
842/*----------------------------------------------------------------------------
843| Returns 1 if the quadruple-precision floating-point value `a' is a
844| signaling NaN; otherwise returns 0.
845*----------------------------------------------------------------------------*/
846
847bool float128_is_signaling_nan(float128 a, float_status *status)
848{
849    if (no_signaling_nans(status)) {
850        return 0;
851    } else {
852        if (snan_bit_is_one(status)) {
853            return ((a.high << 1) >= 0xFFFF000000000000ULL)
854                && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
855        } else {
856            return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
857                && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));
858        }
859    }
860}
861